TI1 LMK00101SQE Ultra-low jitter lvcmos fanout buffer/level translator with universal input Datasheet

LMK00101
Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator
with Universal Input
1.0 General Description
3.0 Features
The LMK00101 is a high performance, low noise LVCMOS
fanout buffer which can distribute 10 ultra-low jitter clocks
from a differential, single ended, or crystal input. The
LMK00101 supports synchronous output enable for glitch free
operation. The ultra low-skew, low-jitter, and high PSRR
make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference
distribution, medical and test equipment applications.
The core voltage can be set to 2.5 or 3.3 V, while the output
voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00101
can be easily configured through pin programming.
■ 10 LVCMOS/LVTTL Outputs, DC to 200 MHz
■ Universal Input
2.0 Target Applications
■
■
■
■
■
■
■
■
LO Reference Distribution for RRU Applications
SONET, Ethernet, Fibre Channel Line Cards
Optical Transport Networks
GPON OLT/ONU
Server and Storage Area Networking
Medical Imaging
Portable Test and Measurement
High-end A/V
■
■
■
■
■
■
■
— LVPECL
— LVDS
— HCSL
— SSTL
— LVCMOS / LVTTL
Crystal Oscillator Interface
— Crystal Input Frequency: 10 to 40 MHz
Output Skew: 6 ps
Additive Phase Jitter
— 30 fs at 156.25 MHz (12 kHz to 20 MHz)
Low Propagation Delay
Operates with 3.3 or 2.5 V Core Supply Voltage
Adjustable Output Power Supply
— 1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank
32 pin LLP Package 5.0 x 5.0 x 0.8 mm
4.0 Functional Block Diagram
30146901
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301469 SNAS572
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LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
January 16, 2012
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
5.0 Connection Diagram
32-Pin LLP Package
30146902
6.0 Pin Descriptions
Pin #
Pin Name
Type
DAP
DAP
-
Description
The DAP should be grounded
1
CLKout0
Output
LVCMOS Output
2, 6
Vddo
Power
Power Supply for Bank A (CLKout0 to CLKout4) CLKout pins.
19,23
Vddo
Power
Power Supply for Bank B (CLKout5 to CLKout9) CLKout pins.
3
CLKout1
Output
LVCMOS Output
4,9,15,16,
21,25,26,32
GND
GND
5
CLKout2
Output
LVCMOS Output
7
CLKout3
Output
LVCMOS Output
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Ground
8
CLKout4
Output
LVCMOS Output
10
Vdd
Power
Supply for operating core and input buffer
11
OSCin
Input
12
OSCout
Output
13
CLKin0
Input
Input Pin
14
CLKin0*
Input
Optional complimentary input pin
17
CLKout5
Output
LVCMOS Output
18
CLKout6
Output
LVCMOS Output
20
CLKout7
Output
LVCMOS Output
22
CLKout8
Output
LVCMOS Output
24
CLKout9
Output
LVCMOS Output
27
CLKin1*
Input
Optional Complimentary Input Pin
28
CLKin1
Input
Input Pin
29
SEL1
Input
MSB for Input Clock Selection. This pin has an internal pull-down
resistor.
30
SEL0
Input
LSB for Input Clock Selection. This pin has an internal pull-down
resistor.
31
OE
Input
Output Enable. This pin has an internal pull-down resistor.
Input for Crystal
Output for Crystal
2
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
Parameter
Core Supply Voltage
Output Supply Voltage
Ratings
-0.3 to 3.6
-0.3 to 3.6
Units
V
V
Input Voltage
Symbol
Vdd
Vddo
VIN
-0.3 to Vdd + 0.3
V
Storage Temperature Range
TSTG
-65 to 150
°C
Lead Temperature (solder 4 s)
TL
+260
°C
Junction Temperature
TJ
+125
°C
8.0 Recommended Operating Conditions
Symbol
TA
Min
Typ
Max
Units
Ambient Temperature
Parameter
-40
25
85
°C
Core Supply Voltage
Output Supply Voltage (Note 3)
Vdd
Vddo
2.375
1.425
3.3
3.3
3.45
Vdd
V
V
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work
stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.
Note 3: Vddo should be less than or equal to Vdd (Vddo ≤ Vdd)
9.0 Package Thermal Resistance
32-Lead LLP
Package
Symbols
Ratings
Units
Thermal resistance from junction to ambient
on 4-layer Jedec board (Note 4)
θJA
50
° C/W
Thermal resistance from junction to case
(Note 5)
θJC (DAP)
20
° C/W
Note 4: Specification assumes 5 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias play a key role in
improving the thermal performance of the LLP. For best thermal dissipation it is recommended that the maximum number of vias be used on the board layout.
Note 5: Case is defined as the DAP (die attach pad).
3
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LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
7.0 Absolute Maximum Ratings (Note 1, Note 2)
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
10.0 Electrical Characteristics
(2.375 V ≤ Vdd ≤ 3.45 V, 1.425 ≤ Vddo ≤ Vdd, -40 °C ≤ TA ≤ 85 °C, Differential inputs. Typical values represent most likely
parametric norms at Vdd = Vddo = 3.3 V, TA = 25 °C, at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 Ω unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Total Device Characteristics
Vdd
Core Supply Voltage
2.375
2.5 or
3.3
3.45
V
Vddo
Output Supply Voltage
1.425
1.5,1.8,
2.5, or
3.3
Vdd
V
No CLKin
16
25
Vddo = 3.3 V, Ftest = 100 MHz
24
Vddo = 2.5 V, Ftest = 100 MHz
20
Vddo = 2.5 V,
OE = High, Ftest = 100 MHz
5
IVdd
Core Current
IVddo[n]
Current for Each Output
Vddo= 3.3 V,
OE = High, Ftest = 100 MHz
7
OE = Low
0.1
IVdd + IVddo
Total Device Current with Loads on
all outputs
OE = High @ 100 MHz
95
OE = Low
16
mA
mA
mA
Power Supply Ripple Rejection (PSRR)
PSRR
Ripple Induced
Phase Spur Level
100 kHz, 100 mVpp
Ripple Injected on
Vdd, Vddo = 2.5 V
-44
dBc
6
ps
Outputs (Note 6)
Skew
Output Skew
fCLKout
Output Frequency
(Note 7)
tRise
VCLKoutLow
Rise/Fall Time
Measured between outputs,
referenced to CLKout0
DC
200
Vdd = 3.3 V, Vddo = 1.8 V, CL = 10 pF
500
Vdd = 2.5 V, Vddo = 2.5 V, CL = 10 pF
300
Vdd = 3.3 V, Vddo = 3.3 V, CL = 10 pF
200
Output Low Voltage
VCLKoutHigh
Output High Voltage
RCLKout
Output Resistance
tj
RMS Additive Jitter
MHz
ps
0.1
V
Vddo0.1
50
ohm
30
fs
fCLKout = 156.25 MHz,
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CMOS input slew rate ≥ 2 V/ns
CL = 5 pF, BW = 12 kHz to 20 MHz
4
Parameter
VLow
Input Low Voltage
VHigh
Input High Voltage
IIH
High Level Input Current
IIL
Low Level Input Current
Test Conditions
Min
Typ
Max
Units
Digital Inputs (OE, SEL0, SEL1)
Vdd = 2.5 V
0.4
Vdd = 2.5 V
1.3
Vdd = 3.3 V
1.6
V
50
-5
5
uA
CLKin0/0* and CLKin1/1* Input Clock Specifications, (Note 9, Note 10)
IIH
High Level Input Current
VCLKin = Vdd
IIL
Low Level Input Current
(Note 8)
VCLKin = 0 V
VIH
Input High Voltage
VIL
Input Low Voltage
VCM
VID
-20
uA
uA
Vdd
GND
V
VID = 150 mV
0.5
Vdd1.2
VID = 350 mV
0.5
Vdd1.1
VID = 800 mV
0.5
Vdd0.9
CLKin driven differentially
0.15
1.5
V
DC
200
MHz
10
40
MHz
Differential Input
Common Mode Input Voltage
(Note 12)
Differential Input Voltage Swing
20
V
OSCin/OSCout Pins
fOSCin
Input Frequency (Note 7)
Single-Ended Input, OSCout floating
fXTAL
Crystal Frequency Input Range
ESR < 200 Ω ( fXtal ≤ 30 MHz )
COSCin
Shunt Capacitance
Fundamental Mode Crystal
ESR < 120 Ω ( fXtal > 30 MHz )
(Note 11, Note 7)
1
pF
Note 6: AC Parameters for CMOS are dependent upon output capacitive loading
Note 7: Guaranteed by characterization.
Note 8: VIL should not go below -0.3 volts.
Note 9: See Section 12.1 Differential Voltage Measurement Terminology for definition of VID and VOD.
Note 10: Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.
Note 11: The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However, lower ESR values
for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal.
Note 12: When using differential signals with VCM outside of the acceptable range for the specified VID, the clock must be AC coupled.
5
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LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
Symbol
Unless otherwise specified: Vdd = Vddo = 3.3 V, TA = 20 °C, CL = 5 pF, CLKin driven differentially, input slew rate ≥ 2 V/ns.
RMS Jitter vs. CLKin Slew Rate @ 100 MHz
-40 C
25 C
85 C
CLKin Source
450
RMS JITTER (fs)
400
Noise Floor vs. CLKin Slew Rate @ 100 MHz
-140
Fclk-100 MHz
Int. BW=1-20 MHz
NOISE FLOOR (dBc/Hz)
500
350
300
250
200
150
100
50
0
-40 C
25 C
85 C
CLKin Source
-145
Fclk=100 MHz
Foffset=20 MHz
-150
-155
-160
-165
-170
0.5
1.0
1.5
2.0
2.5
3.0
DIFFERENTIAL INPUT SLEW RATE (V/ns)
0.5
1.0
1.5
2.0
2.5
3.0
DIFFERENTIAL INPUT SLEW RATE (V/ns)
30146941
30146974
LVCMOS Output Swing vs. Frequency
LVCMOS Phase Noise @ 100 MHz (Note 13)
OUTPUT SWING (V)
3.5
3.0
Vddo=1.5 V
Vddo=1.8 V
Vddo=2.5 V
Vddo=3.3 V
2.5
Rterm=50 Ω
2.0
1.5
1.0
0.5
0.0
0
200
400
600
800
FREQUENCY (MHz)
Iddo per Output vs Frequency
15
Vddo = 1.5 V
Vddo = 1.8 V
Vddo = 2.5 V
Vddo = 3.3 V
Cload = 10 pF
10
5
0
0
50
100
150
200
FREQUENCY (MHz)
250
30146976
Note 13: Test conditions: LVCMOS Input, slew rate ≥ 2 V/ns, CL = 5 pF in parallel with 50 Ω, BW = 1 MHz to 20 MHz.
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1000
30146975
30146942
CURRENT (mA)
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
11.0 Typical Performance Characteristics
6
12.1 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions causing confusion when
reading datasheets or communicating with other engineers.
This section will address the measurement and description of
a differential signal so that the reader will be able to understand and discern between the two different definitions when
used.
The first definition used to describe a differential signal is the
absolute value of the voltage potential between the inverting
and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output
voltage is being described.
The second definition used to describe a differential signal is
to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second
30146912
FIGURE 1. Two Different Definitions for Differential Input Signals
30146913
FIGURE 2. Two Different Definitions for Differential Output Signals
7
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LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
measurement is VSS and is a calculated parameter. Nowhere
in the IC does this signal exist with respect to ground, it only
exists in reference to its differential pair. VSS can be measured
directly by oscilloscopes with floating references, otherwise
this value can be calculated as twice the value of VOD as described in the first section
Figure 1 illustrates the two different definitions side-by-side
for inputs and Figure 2 illustrates the two different definitions
side-by-side for outputs. The VID and VOD definitions show
VA and VB DC levels that the non-inverting and inverting signals toggle between with respect to ground. VSS input and
output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal
voltage potential is now increasing and decreasing above and
below the non-inverting reference. Thus the peak-to-peak
voltage of the differential signal can be measured.
VID and VOD are often defined in volts (V) and VSS is often
defined as volts peak-to-peak (VPP).
12.0 Measurement Definitions
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
and CLKin1/1* Input Clock Specifications” portion of the Section 10.0 Electrical Characteristics and (Note 12). Refer to
Section 14.1 Driving the Clock Inputs for more details on driving the LMK00101 inputs.
In the event that a Crystal mode is not selected and the CLKin
pins do not have an AC signal applied to them, Table 2 following will be the state of the outputs.
13.0 Functional Description
The LMK00101 is a 10 output LVCMOS clock fanout buffer
with low additive jitter that can operate up to 200 MHz. It features a 3:1 input multiplexer with a crystal oscillator input,
single supply or dual supply (lower power) operation, and pinprogrammable device configuration. The device is offered in
a 32-pin LLP package.
TABLE 2. CLKinX Input vs. Output States
13.1 Vdd and Vddo Power Supplies (Note 14, Note 15)
Separate core and output supplies allow the output buffers to
operate at the same supply as the Vdd core supply (3.3 V or
2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or
1.5 V). Compared to single-supply operation, dual supply operation enables lower power consumption and output-level
compatibility.
Bank A (CLKout0 to CLKout4) and Bank B (CLKout5 to CLKout9) may also be operated at different Vddo voltages, provided neither Vddo voltage exceeds Vdd.
CLKinX
13.2 CLOCK INPUTS
The LMK00101 has three different inputs, CLKin0/CLKin0*,
CLKin1/CLKin1*, and OSCin that can be driven in different
manners that are described in the following sections.
Input
CLKin0, CLKin0*
0
1
CLKin1, CLKin1*
1
X
OSCin
(Crystal Mode)
Logic Low
Logic High
Logic Low
Logic High
Logic Low
OE
Outputs
Low
Disabled (Hi-Z)
High
Enabled
13.3.2 Using Less than Ten Outputs
Although the LMK00101 has 10 outputs, not all applications
will require all of these. In this case, the unused outputs
should be left floating with a minimum copper length (Note
16) to minimize capacitance. In this way, this output will consume minimal output current because it has no load.
13.2.1.1 CLKin/CLKin* Pins
The LMK00101 has two differential inputs (CLKin0/CLKin0*
and CLKin1/CLKin1*) that can be driven single-ended or differentially. They can accept AC or DC coupled 3.3V/2.5V
LVPECL, LVDS, or other differential and singled ended signals that meet the input requirements under the “CLKin0/0*
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Logic Low
Logic High
The OE pin is synchronized to the input clock to ensure that
there are no runt pulses. When OE is changed from Low to
High, the outputs will initially have an impedance of about
400 Ω to ground until the second falling edge of the input
clock. Starting with the second falling edge of the input clock,
the outputs will buffer the input. If the OE pin is taken from
Low to High when there is no input clock present, the outputs
will either go High or Low and stay a that state; they will not
oscillate. When the OE pin is taken from High to Low the outputs will become Low after the second falling edge of the clock
input and then will go to a Disabled (Hi-Z) state starting after
the next rising edge.
TABLE 1. Input Selection
0
Open
Logic Low
TABLE 3. Output Enable Pin States
13.2.1 SELECTION OF CLOCK INPUT
Clock input selection is controlled using the SEL0 and SEL1
pins as shown in Table 1. Refer to Section 14.1 Driving the
Clock Inputs for clock input requirements. When CLKin0 or
CLKin1 is selected, the crystal circuit is powered down. When
OSCin is selected, the crystal oscillator will start-up and its
clock will be distributed to all outputs. Refer to Section 14.2
Crystal Interface for more information. Alternatively, OSCin
may be driven by a single ended clock, up to 200 MHz, instead
of a crystal.
SEL0
Logic Low
Open
Logic Low
13.3.1 Output Enable Pin
When the output enable pin is held High, the outputs are enabled. When it is held Low, the outputs are held in a Low state
as shown in Table 3.
Note 15: DO NOT DISCONNECT OR GROUND ANY OF THE Vddo PINS
as the Vddo pins are internally connected within an output bank.
0
Output State
13.3 CLOCK OUTPUTS
The LMK00101 has 10 LVCMOS outputs.
Note 14: Care should be taken to ensure the Vddo voltage does not exceed
the Vdd voltage to prevent turning-on the internal ESD protection circuitry.
SEL1
CLKinX*
Note 16: For best soldering practices, the minimum trace length should
extend to include the pin solder mask. This way during reflow, the solder has
the same copper area as connected pins. This allows for good, uniform fillet
solder joints helping to keep the IC level during reflow.
8
14.1 Driving the Clock Inputs
The LMK00101 has two differential inputs (CLKin0/CLKin0*
and CLKin1/CLKin1*) that can accept AC or DC coupled 3.3V/
2.5V LVPECL, LVDS, and other differential and single ended
signals that meet the input requirements specified in Section 10.0 Electrical Characteristics. The device can accept a
wide range of signals due to its wide input common mode
voltage range (VCM) and input voltage swing (VID)/dynamic
range. AC coupling may also be employed to shift the input
signal to within the VCM range.
To achieve the best possible phase noise and jitter performance, it is mandatory for the input to have a high slew rate
of 2 V/ns (differential) or higher. Driving the input with a lower
slew rate will degrade the noise floor and jitter. For this reason, a differential input signal is recommended over singleended because it typically provides higher slew rate and
common-mode noise rejection.
While it is recommended to drive CLKin0 and CLKin1 with a
differential signal input, it is possible to drive them with a single ended clock. The single-ended input slew rate should be
as high as possible to minimize performance degradation.
The CLKinX input has an internal bias voltage of about 1.4 V,
so the input can be AC coupled as shown in Figure 3, Figure
4, or Figure 5 depending upon the application.
30146944
FIGURE 5. Single-Ended LVCMOS Input, AC Coupling,
Far End Termination
A single ended clock may also be DC coupled to CLKinX as
shown in Figure 6. If the DC coupled input swing has a common mode level near the devices internal bias of 1.4 V, then
only a 0.1 µF bypass cap is required on CLKinX*. Otherwise,
if the input swing is not optimally centered near the internal
bias voltage, then CLKinX* should be externally biased to the
midpoint voltage of the input swing. This can be achieved using external biasing resistors, RB1 and RB2, or another lownoise voltage reference. The external bias voltage should be
within the specified input common voltage (VCM) range. This
will ensure the input swing crosses the threshold voltage at a
point where the input slew rate is the highest.
30146938
30146939
FIGURE 3. Single-Ended LVCMOS Input, AC Coupling,
Near and Far End Termination
FIGURE 6. Single-Ended LVCMOS Input, DC Coupling
with Common Mode Biasing
If the crystal oscillator circuit is not used, it is possible to drive
the OSCin input with an single-ended external clock as shown
in Figure 7. Configurations similar to Figure 4 or Figure 5 could
also be used as long as the OSCout pin is left floating. The
input clock should be AC coupled to the OSCin pin, which has
an internally generated input bias voltage, and the OSCout
pin should be left floating. While OSCin provides an alternative input to multiplex an external clock, it is recommended to
use either differential input (CLKinX) since it offers higher operating frequency, better common mode, improved power
supply noise rejection, and greater performance over supply
voltage and temperature variations.
30146943
FIGURE 4. Single-Ended LVCMOS Input, AC Coupling,
Near End Termination
9
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LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
14.0 Application Information
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
•
C0 is the minimum shunt capacitance specified for the
crystal.
IRMS can be measured using a current probe (e.g. Tektronix
CT-6 or equivalent) placed on the leg of the crystal connected
to OSCout with the oscillation circuit active.
As shown in Figure 8, an external resistor, RLIM, can be used
to limit the crystal drive level if necessary. If the power dissipated in the selected crystal is higher than the drive level
specified for the crystal with RLIM shorted, then a larger resistor value is mandatory to avoid overdriving the crystal. However, if the power dissipated in the crystal is less than the drive
level with RLIM shorted, then a zero value for RLIM can be used.
As a starting point, a suggested value for RLIM is 1.5 kΩ
30146903
FIGURE 7. Driving OSCin with a Single-Ended External
Clock
14.2 Crystal Interface
The LMK00101 has an integrated crystal oscillator circuit that
supports a fundamental mode, AT-cut crystal. The crystal interface is shown in Figure 8.
14.3 Power Supply Ripple Rejection
In practical system applications, power supply noise (ripple)
can be generated from switching power supplies, digital
ASICs or FPGAs, etc. While power supply bypassing will help
filter out some of this noise, it is important to understand the
effect of power supply ripple on the device performance.
When a single-tone sinusoidal signal is applied to the power
supply of a clock distribution device, such as LMK00101, it
can produce narrow-band phase modulation as well as amplitude modulation on the clock output (carrier). In the singleside band phase noise spectrum, the ripple-induced phase
modulation appears as a phase spur level relative to the carrier (measured in dBc).
For the LMK00101, power supply ripple rejection (PSRR),
was measured as the single-sideband phase spur level (in
dBc) modulated onto the clock output when a ripple signal
was injected onto the Vddo supply. The PSRR test setup is
shown in Figure 9.
30146904
FIGURE 8. Crystal Interface
The load capacitance (CL) is specific to the crystal, but usually
on the order of 18 to 20 pF. While CL is specified for the crystal, the OSCin input capacitance (CIN = 1 pF typical) of the
device and PCB stray capacitance (CSTRAY ~ 1 to 3 pF) can
affect the discrete load capacitor values, C1 and C2. For the
parallel resonant circuit, the discrete capacitor values can be
calculated as follows:
CL = (C1 * C2) / (C1 + C2) + CIN + CSTRAY
(1)
Typically, C1 = C2 for optimum symmetry, so Equation 1 can
be rewritten in terms of C1only:
CL = C12 / (2 * C1 ) + CIN + CSTRAY
(2)
Finally, solve for C1:
C1 = (CL - CIN - CSTRAY) * 2
(3)
30146940
Section 10.0 Electrical Characteristics provides crystal interface specifications with conditions that ensure start-up of the
crystal, but it does not specify crystal power dissipation. The
designer will need to ensure the crystal power dissipation
does not exceed the maximum drive level specified by the
crystal manufacturer. Overdriving the crystal can cause premature aging, frequency shift, and eventual failure. Drive level
should be held at a sufficient level necessary to start-up and
maintain steady-state operation.
The power dissipated in the crystal, PXTAL, can be computed
by:
PXTAL = IRMS2 * RESR * (1 + C0 / CL)2
FIGURE 9. PSRR Test Setup
A signal generator was used to inject a sinusoidal signal onto
the Vddo supply of the DUT board, and the peak-to-peak ripple
amplitude was measured at the Vddo pins of the device. A limiting amplifier was used to remove amplitude modulation on
the differential output clock and convert it to a single-ended
signal for the phase noise analyzer. The phase spur level
measurements were taken for clock frequencies of 100 MHz
under the following power supply ripple conditions:
• Ripple amplitude: 100 mVpp on Vddo = 2.5 V
• Ripple frequency: 100 kHz
Assuming no amplitude modulation effects and small index
modulation, the peak-to-peak deterministic jitter (DJ) can be
calculated using the measured single-sideband phase spur
level (PSRR) as follows:
(4)
Where:
• IRMS is the RMS current through the crystal.
• RESR is the maximum equivalent series resistance
specified for the crystal.
• CL is the load capacitance specified for the crystal.
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10
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 10 should connect these top and bottom
copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
(5)
14.4 Power Supply Bypassing
The Vdd and Vddo power supplies should have a high frequency bypass capacitor, such as 100 pF, placed very close to
each supply pin. Placing the bypass capacitors on the same
layer as the LMK00101 improves input sensitivity and performance. All bypass and decoupling capacitors should have
short connections to the supply and ground plane through a
short trace or via to minimize series inductance.
14.5 Thermal Management
For reliability and performance reasons the die temperature
should be limited to a maximum of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to a printed circuit board. To maximize the removal
of heat from the package a thermal land pattern including
multiple vias to a ground plane must be incorporated on the
PCB within the footprint of the package. The exposed pad
must be soldered down to ensure adequate heat conduction
out of the package.
A recommended land and via pattern is shown in Figure 10.
More information on soldering LLP packages and gerber footprints can be obtained: http://www.national.com/en/packaging/index.html.
A recommended footprint including recommended solder
mask and solder paste layers can be found at: http://
www.national.com/en/packaging/gerber.html
for
the
SQA32A package.
30146973
FIGURE 10. Recommended Land and Via Pattern
11
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LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
DJ (ps pk-pk) = [(2 * 10(PSRR/20)) / (π * fclk)] * 1012
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
15.0 Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (Bottom View)
32 Pin LLP Package
16.0 Ordering Information
Order Number
Package Marking
LMK00101SQX
LMK00101SQ
2500 Unit Tape and Reel
K00101
1000 Unit Tape and Reel
LMK00101SQE
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Packaging
250 Unit Tape and Reel
12
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13
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
Notes
LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
Notes
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