IDT IDT72V17320 3.3v multimedia fifo 16 bit v-iii, 32 bit vx-iii family up to 1 mb density Datasheet

IDT72V15160
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V19160
3.3V MULTIMEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
•
•
•
FEATURES:
•
•
•
•
Choose among the following memory organizations: Commercial
•
V-III
Vx-III
IDT72V15160 - 4,096 x 16
IDT72V16160 - 8,192 x 16
IDT72V17160 - 16,384 x 16
IDT72V18160 - 32,768 x 16
IDT72V19160 - 65,536 x 16
IDT72V14320 - 1,024 x 32
IDT72V15320 - 2,048 x 32
IDT72V16320 - 4,096 x 32
IDT72V17320 - 8,192 x 32
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32
•
•
•
•
•
•
Up to 100 MHz Operation of the Clocks
5V input tolerant
Auto power down minimizes standby power consumption
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags through serial input
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function (PBGA Only)
Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
Industrial temperature range (–40°°C to +85°°C)
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*Available on the Vx-III PBGA package only.
MRS
WCLK
WEN
WRITE
CONTROL
PRS
RCLK
READ
CONTROL
RESET LOGIC
REN
OE
D0 - Dn
Data In
x16, x32
*
*
**
*
TCK
TRST
TMS
TDI
TDO
Q0 - Qn
Data Out
x16, x32
FIFO ARRAY
JTAG CONTROL
(BOUNDARY
SCAN)
*
FLAG LOGIC
LD
SEN
SI
PFM
FSEL1 EF
FSEL0
HF
PAE
FF
PAF
6163 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
NOVEMBER 2003
INDUSTRIAL TEMPERATURE RANGE
1
 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6163/2
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded with the serial interface to any user desired value or by default values.
Eight default offset settings are provided, so that PAE can be set to switch at a
predefined number of locations from the empty boundary and the PAF threshold
can also be set at similar predefined values from the full boundary. The default
offset values are set during Master Reset by the state of the FSEL0, FSEL1, and
LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI).
During Master Reset (MRS) the read and write pointers are set to the first
location of the FIFO.
DESCRIPTION:
The IDT V-III and Vx-III Multimedia FIFOs are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with independent clocked
read and write controls and high density offerings up to 1 Mbit.
Each FIFO has a data input port (Dn) and a data output port (Qn). The
frequencies of both the RCLK (read port clock) and the WCLK (write port
clock) signals may vary from 0 to f S(MAX) with complete independence.
There are no restrictions on the frequency of the one clock input with respect
to the other.
These FIFOs have five flag pins, EF (Empty Flag), FF (Full Flag), HF (Halffull Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable
Almost-Full flag).
WCLK
PRS
MRS
LD
SI
FF
PAF
GND
FSEL0
HF
FSEL1
GND
GND
VCC
PAE
PFM
EF
GND
RCLK
REN
PIN CONFIGURATIONS (16-BIT V-III FAMILY)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
INDEX
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
OE
VCC
Q0
Q1
GND
GND
DNC(1)
Q2
VCC
Q3
Q4
GND
Q5
GND
Q6
VCC
Q7
Q8
Q9
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
WEN
SEN
DNC(1)
VCC
DNC(1)
GND
GND
D0
VCC
D1
GND
D2
D3
GND
D4
D5
D6
D7
D8
VCC
D9
GND
GND
D10
D11
D12
D13
D14
D15
GND
Q15
Q14
GND
Q13
Q12
VCC
Q11
Q10
GND
DNC(1)
6163 drw02
NOTE:
1. DNC = Do Not Connect.
TQFP (PN80-1, order code: PF)
TOP VIEW
2
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT V-III and Vx-III family of FIFOs are fabricated using IDT’s high
speed submicron CMOS technology.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the programmable flag settings existing before
Partial Reset remain unchanged. PRS is useful for resetting a device in midoperation, when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
WCLK
PRS
MRS
LD
SI
FF
VCC
PAF
GND
GND
FS0
HF
GND
FS1
GND
GND
GND
VCC
PAE
PFM
EF
GND
GND
RCLK
REN
VCC
PIN CONFIGURATIONS (32-BIT Vx-III FAMILY)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
D22
D23
D24
D25
GND
GND
D26
D27
D28
VCC
D29
D30
D31
GND
Q31
Q30
Q29
Q28
Q27
Q26
GND
DNC(1)
VCC
Q25
Q24
Q23
DNC(1)
VCC
DNC(1)
GND
D0
D1
D2
D3
VCC
D4
D5
GND
D6
D7
D8
GND
D9
D10
GND
GND
D11
VCC
D12
D13
D14
D15
GND
D16
D17
GND
D18
D19
VCC
D20
GND
D21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
WEN
SEN
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
INDEX
NOTE:
1. DNC - Do Not Connect.
TQFP: (PK128-1, order code: PF)
TOP VIEW
3
OE
VCC
VCC
Q0
Q1
Q2
Q3
GND
GND
Q4
Q5
Q6
Q7
Q8
DNC(1)
VCC
Q9
Q10
GND
GND
DNC(1)
Q11
Q12
Q13
Q14
Q15
GND
Q16
Q17
VCC
VCC
DNC(1)
Q18
Q19
Q20
GND
Q21
Q22
6163 drw03
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN CONFIGURATIONS-CONTINUED (32-BIT VX-III FAMILY)
A1 BALL PAD CORNER
A
VCC
WEN
WCLK
PAF
FF
HF
GND
EF
RCLK
REN
OE
Q0
SEN
GND
PRS
LD
MRS
FS0
FS1
VCC
GND
PFM
VCC
Q1
D0
D1
D2
SI
GND
VCC
VCC
GND
PAE
GND
Q3
Q2
D3
D4
D5
VCC
VCC
GND
GND
VCC
VCC
Q6
Q5
Q4
D6
D7
D8
VCC
GND
GND
GND
GND
VCC
Q9
Q8
Q7
D9
D10
D11
VCC
GND
GND
GND
GND
VCC
Q12
Q11
Q10
D14
D13
D12
VCC
GND
GND
GND
GND
VCC
Q13
Q14
Q15
D17
D16
D15
VCC
GND
GND
GND
GND
VCC
Q16
Q17
Q18
D20
D19
D18
VCC
VCC
GND
GND
VCC
VCC
Q19
Q20
Q21
D23
D22
D21
D28
D31
VCC
VCC
TDO
Q29
Q22
Q23
DNC
GND
GND
D25
D27
D30
TMS
TCK
Q31
Q28
Q26
DNC
DNC
GND
GND
D24
D26
D29
TRST
TDI
Q30
Q27
Q25
Q24
DNC
1
2
3
4
5
6
7
8
9
10
11
B
C
D
E
F
G
H
J
K
L
M
12
6163 drw03b
NOTE:
1. DNC - Do Not Connect.
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
4
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
D0–Dn
EF
FF
FSEL0(1)
Name
Data Inputs
Empty Flag
Full Flag
Flag Select Bit 0
I/O
I
O
O
I
FSEL1(1)
Flag Select Bit 1
I
HF
Half-Full Flag
O
LD
Load
I
MRS
Master Reset
I
OE
PAE
I
O
PRS
Output Enable
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Programmable
Flag Mode
Partial Reset
Q0–Qn
RCLK
REN
SEN
Data Outputs
Read Clock
Read Enable
Serial Enable
O
I
I
I
SI
WCLK
WEN
V CC
GND
Serial In
Write Clock
Write Enable
+3.3V Supply
Ground
I
I
I
I
I
PAF
PFM(1)
O
I
I
Description
Data inputs for a 16 or 32-bit bus
EF indicates the FIFO memory is empty. See Table 2.
FF indicates the FIFO memory is full. See Table 2.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
HF indicates the FIFO memory is more than half-full. HF is asserted when the number of words written into the FIFO
reaches N÷2+1, where N is the total depth of the FIFO. See Table 2.
During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines one of eight default offset
values for the PAE and PAF flags and serial programming mode. After Master Reset, LD must be high and should
only toggle LOW together with SEN to start serial loading of the flag offsets.
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for one of eight programmable flag default settings, serial programming of the offset settings and
synchronous versus asynchronous programmable flag timing modes.
OE controls the output line drivers.
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
will select Synchronous Programmable flag timing mode.
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the serial programming method or programmable flag settings are all retained.
Data outputs for an 16 or 32-bit bus. Outputs are not 5V tolerant regardless of the state of OE.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory.
REN enables RCLK for reading data from the FIFO memory.
SEN enables serial loading of programmable flag offsets. SEN must be high during Master Reset and should only
toggle LOW together with LD to start serial loading of the flag offsets.
At Maser Reset this pin is LOW. After Master Reset, this pin functions as a serial input for loading offset registers.
Enabled by WEN, the rising edge of WCLK writes data into the FIFO.
WEN enables WCLK for writing data into the FIFO memory.
These are VCC supply inputs and must be connected to the 3.3V supply rail.
Ground Pins.
NOTE:
1. Inputs should not change state after Master Reset.
**Please continue to next page for more Pin descriptions for PBGA package.
5
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN DESCRIPTION (32-BIT VX-III PBGA PACKAGE ONLY)
Symbol
(1)
Name
I/O
Description
JTAG Clock
I
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(1)
JTAG Test Data
Input
I
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(1)
JTAG Test Data
Output
O
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(1)
JTAG Mode Select
I
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(1)
JTAG Reset
I
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used
but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the
JTAG function is not used then this signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if
left unconnected.
TCK
NOTE:
1. These pins are for the JTAG port. Please refer to pages 15-19 and Figures 2-4.
6
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM(2)
TSTG
IOUT
Rating
Terminal Voltage
with respect to GND
Industrial
–0.5 to +4.5
Storage
Temperature
–55 to +125
DC Output Current
–50 to +50
INDUSTRIAL
TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Unit
V
Symbol
Parameter
VCC(1) Supply Voltage Industrial
°C
mA
Typ.
Max.
Unit
3.15
3.3
3.45
V
GND
Supply Voltage Industrial
0
0
0
V
VIH(2)
Input High Voltage Industrial
2.0
—
5.5
V
Input Low Voltage Industrial
—
—
0.8
V
Operating Temperature Industrial
-40
—
85
°C
VIL
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminal only.
Min.
(3)
TA
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V15160,
IDT72V16160,
IDT72V17160,
IDT72V18160,
IDT72V19160,
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
Industrial
tCLK = 10ns
Symbol
(1)
ILI
ILO(2)
VOH
VOL
ICC1(3,4,5)
ICC2(3,6)
Parameter
Input Leakage Current
Output Leakage Current
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
Standby Current
Min.
Max.
Unit
–1
–10
2.4
—
—
—
1
10
—
0.4
40
15
µA
µA
V
V
mA
mA
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 4.2 + 1.4*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
6. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
7
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Industrial
IDT72V15160L10
IDT72V16160L10
IDT72V17160L10
IDT72V18160L10
IDT72V19160L10
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tLDS
tLDH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
tSKEW1
tSKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
Reset Pulse Width(1)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to FF
Read Clock to EF
Clock to Asynchronous Programmable Almost-Full Flag
Write Clock to Synchronous Programmable Almost-Full Flag
Clock to Asynchronous Programmable Almost-Empty Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Clock to HF
Skew time between RCLK and WCLK for EF and FF
Skew time between RCLK and WCLK for PAE and PAF
Min.
—
2
10
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
15
10
—
0
2
2
—
—
—
—
—
—
—
7
10
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
8
IDT72V14320L10
IDT72V15320L10
IDT72V16320L10
IDT72V17320L10
IDT72V18320L10
IDT72V19320L10
Max
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
6
6
6.5
6.5
16
6.5
16
6.5
16
—
—
Unit
Mhz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
AC TEST CONDITIONS
INDUSTRIAL
TEMPERATURE RANGE
AC TEST LOADS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load for tCLK = 10ns
GND to 3.0V
3ns(1)
1.5V
1.5V
See Figure 1
3.3V
330Ω
D.U.T.
510Ω
30pF*
6163 drw04
Figure 1. Output Load
* Includes jig and scope capacitances.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE & tOLZ
Output VCC
Normally
2
LOW
Output
Normally VCC
2
HIGH
tOHZ
VCC
2
100mV
100mV
VOL
VOH
100mV
100mV
VCC
2
6163 drw04a
NOTE:
1. REN is HIGH.
9
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
FUNCTIONAL DESCRIPTION
To write data into to the FIFO, Write Enable (WEN) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The
Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where “n” is the empty offset value. The default setting
for these values are stated in the footnote of Table 1. This parameter is also user
programmable.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
D/2+1 (D= total number of words) was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go
LOW. Again, if no reads are performed, the PAF will go LOW after (D-m). The
offset “m” is the full offset value. The default setting for these values are stated
in the footnote of Table 1. This parameter is also user programmable.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH. If further read
operations occur, without write operations, PAE will go LOW when there are
n words in the FIFO, where n is the empty offset value. Continuing read
operations will cause the FIFO to become empty. When the last word has been
read from the FIFO, the EF will go LOW inhibiting further read operations. REN
is ignored when the FIFO is empty.
The EF and FF outputs are double register-buffered outputs.
TABLE 1 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72V14320, 72V15360
LD
L
L
L
L
H
H
H
H
SERIAL PROGRAMMING MODE
Offset values can also be programmed into the FIFO by serial loading
method. The offset registers may be programmed (and reprogrammed) any
time after Master Reset. Valid programming ranges are from 0 to D-1.
Serial programming of offset values (LD,SEN pins): In order to select
serial programming the LD pin has to be HIGH during master. Both, LD and
SEN pin have to toggle to LOW in order to initial the serial programming. LD
should be high during normal FIFO operation.
If Serial Programming mode has been selected then programming of PAE
and PAF values can be achieved by using a combination of the LD, SEN, WCLK
and SI input pins. Programming PAE and PAF proceeds as follows: when LD
and SEN are set LOW, data on the SI input are written, one bit for each WCLK
rising edge, starting with the Empty Offset LSB and ending with the Full Offset
MSB.
FSEL1
H
L
L
H
L
H
L
H
FSEL0
L
H
L
H
L
L
H
H
Offsets n,m
511
255
127
63
31
15
7
3
IDT72V16320, 72V17320, 72V18320, 72V19320
IDT72V15160, 72V16160, 72V17160, 72V18160
LD
H
L
L
L
L
H
H
H
FSEL1
L
H
L
L
H
H
L
H
FSEL0
L
L
H
L
H
L
H
H
Offsets n,m
1,023
511
255
127
63
31
15
7
IDT72V19160
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT V-III
and Vx-III FIFOs have internal registers for these offsets.
There are two ways to program the flag offset values. Selecting one of the
eight pre-set values during master reset or serial programming.
DEFAULT FLAG OFFSETS
There are eight default offset values selectable during Master Reset. These
offset values are shown in Table 1.
Programming offsets with default values (LD, SEN pins): With the
LD pin together with the FSEL0 and FSEL1 the user has the option to choose
one of eight preset values for both offset registers. During master reset the LD
pin can be either HIGH or LOW depending on the selected value. After Master
Reset, LD must be high and should not change state. SEN should be high during
and after Master Reset and should not change state.
INDUSTRIAL
TEMPERATURE RANGE
LD
H
L
L
L
L
H
H
H
FSEL1
L
H
L
L
H
H
L
H
LD
All Devices
FSEL1
FSEL0
H
X
FSEL0
L
L
H
L
H
L
H
H
Offsets n,m
1,023
8,191
16,383
127
4,095
511
2,047
255
Program Mode
X
Serial(3)
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
A total of
20 bits for the IDT72V14320
22 bits for the IDT72V15320
24 bits for the IDT72V15160, IDT72V16320
26 bits for the IDT72V16160, IDT72V17320
28 bits for the IDT72V17160, IDT72V18320
30 bits for the IDT72V18160, IDT72V19320
32 bits for the IDT72V19160
has to be loaded serial for the two (PAF, PAE) registers.
10
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
TABLE 2  STATUS FLAGS FOR IDT STANDARD MODE
IDT72V15160
IDT72V14320
0
Number of
Words in
FIFO
IDT72V16320
0
(1)
0
(1)
(1)
FF PAF HF PAE EF
H
H
H
L
L
1 to n
1 to n
1 to n
H
H
H
L
H
(n+1) to 512
(n+1) to 1,024
(n+1) to 2,048
H
H
H
H
H
2,049 to (4,096-(m+1))
H
H
L
H
H
L
H
H
L
H
H
513 to (1,024-(m+1))
1,025 to (2,048-(m+1))
(2,048-m) to 2,047
(4,096m) to 4,095
H
L
1,024
2,048
4,096
L
L
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V17320
IDT72V18320
IDT72V19320
(1,024-m) to 1,023
IDT72V19160
FF PAF HF PAE EF
H
H
H
L
L
1 to n
1 to n
1 to n
1 to n
H
H
H
L
H
(n+1) to 4,096
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 32,768
H
H
H
H
H
32,769 to (65,536-(m+1))
H
H
L
H
H
H
L
L
H
H
L
L
L
H
H
0
Number of
Words in
FIFO
IDT72V15320
0
0
(1)
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
(1)
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
0
(1)
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
16,384
(1)
(65,536-m) to 65,535
65,536
6163 drw05
NOTE:
1. See Table 1 for values for n, m.
11
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
TABLE 3 — FLAG OFFSET PROGRAMMING, STATE OF LD AND
SEN AFTER MASTER RESET
LD
WEN
REN
SEN
0
1
1
0
WCLK
RCLK
Operation
Serial Flag Programming
X
X
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Write Memory
1
0
X
X
1
X
0
X
X
X
1
1
1
X
X
No Operation
1
1
1
X
X
X
No Operation
0
0
1
1
X
Invalid Operation
0
1
0
1
Read Memory
X
Invalid Operation
6163 drw06
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
Refer also to LD Signal description for more information on flag offset
programming and state requirements for LD and SEN pins
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT V-III and Vx-III can be configured during the Master Reset cycle
with either synchronous or asynchronous timing for PAF and PAE flags by use
of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK.
12
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
SIGNAL DESCRIPTION
INPUTS:
The OE input is used to provide Asynchronous control of the three-state Qn
outputs.
DATA IN (D0 - Dn)
Data inputs for 16 or 32-bit wide data.
READ ENABLE ( REN )
When Read Enable is LOW, data is loaded from the FIFO array into the
output register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
Every word accessed at Qn, including the first word written to an empty FIFO,
must be requested using REN. When the last word has been read from the FIFO,
the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is
ignored when the FIFO is empty. Once a write is performed, EF will go HIGH
allowing a read to occur. The EF flag is updated by two RCLK cycles + tSKEW
after the valid WCLK cycle.
CONTROLS:
MASTER RESET ( MRS )
A Master Reset is accomplished whenever the MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, HF will go HIGH, EF
will go LOW and FF will go HIGH.
SI is supposed to be LOW during master reset.
PFM control settings are defined during the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
SERIAL ENABLE ( SEN )
The SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset. SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT.
Refer to LOAD (LD) pin and section “Programming Flag Offsets” for more
information on offset programming.
PARTIAL RESET ( PRS )
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
HF goes HIGH, FF will go HIGH and EF will go LOW. The output register is
initialized to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Qn) goes
into a high impedance state.
SERIAL IN (SI)
At the time of Master Reset, SI must be LOW.
After Master Reset, SI acts as a serial input for loading PAE and PAF offsets
into the programmable registers.
LOAD ( LD )
This is a dual purpose pin. During Master Reset, the state of the LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the serial programming option for these offset
registers (see Table 3).
After Master Reset, the LD pin is used in conjunction with the SEN pin to
activate the programming process of the flag offset values PAE and PAF. Pulling
LD LOW will begin a serial loading of these offset values.
Depending on the default or serial programming option the state of LD and
SEN have to be considered before and after master reset. Refer also to section
“Programming Flag Offsets” for more information on offset programming.
Programming offsets with default values: With the LD pin together with
the FSEL0 and FSEL1 the user has the option to choose one of eight preset
values for both offset registers. During master reset the LD pin can be either
HIGH or LOW depending on the selected value. After Master Reset, LD must
be high and should not change state. SEN should be high during and after
Master Reset and should not change state.
Serial programming of offset values: In order to select serial programming the LD pin has to be HIGH during master. Both, LD and SEN pin have
to toggle to LOW in order to initial the serial programming. LD should be high
during normal FIFO operation.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF,
PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
WRITE ENABLE ( WEN )
When the WEN input is LOW, data may be loaded into the FIFO array on
the rising edge of every WCLK cycle if the device is not full. Data is stored in
the FIFO array sequentially and independently of any ongoing read operation.
When WEN is HIGH, no new data is written in the FIFO array on each WCLK
cycle.
To prevent data overflow, FF will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF is updated by two WCLK cycles + tSKEW after the RCLK cycle.
WEN is ignored when the FIFO is full.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the EF, PAE and HF flags will not
be updated. (Note that RCLK is only capable of updating the HF flag to HIGH).
The Write and Read Clocks can be independent or coincident.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable
flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,
13
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
OUTPUTS:
FULL FLAG ( FF )
When the FIFO is full, FF will go LOW, inhibiting further write operations.
When FF is HIGH, the FIFO is not full. If no reads are performed after a reset
(either MRS or PRS), FF will go LOW after D writes to the FIFO (D = total number
of words).
FF is synchronous and updated on the rising edge of WCLK. FF is a double
register-buffered output.
EMPTY FLAG ( EF )
When the FIFO is empty, EF will go LOW, inhibiting further read operations.
When EF is HIGH, the FIFO is not empty.
EF is synchronous and updated on the rising edge of RCLK. EF is a double
register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. If no reads are performed after reset (MRS),
PAF will go LOW after (D - m) words are written to the FIFO. (D=total number
INDUSTRIAL
TEMPERATURE RANGE
of words, m = full offset value). The default setting for this value is stated in the
footnote of Table 1.
If asynchronous PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. PAE will go LOW when there are n words
or less in the FIFO. The offset “n” is the empty offset value. The default setting
for this value is stated in the footnote of Table 1.
If asynchronous PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK.
HALF-FULL FLAG ( HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
If no reads are performed after reset (MRS or PRS), HF will go LOW after
(D/2 + 1) writes to the FIFO, where D = total number of words available in the
FIFO.
Because HF is updated by both RCLK and WCLK, it is considered
asynchronous.
DATA OUTPUTS (Q0-Qn)
(Q0-Qn) are data outputs for 16-bit or 32-bit wide data.
14
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
6163 drw07
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
t5
Figure 2. Standard JTAG Timing
JTAG
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)
SYSTEM INTERFACE PARAMETERS
Parameter
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
Parameter
Symbol
Data Output
tDO(1)
Data Output Hold
tDOH(1)
Data Input
tDS
tDH
Test Conditions
Min.
-
trise=3ns
tfall=3ns
Test
Conditions
Min.
Max. Units
20
Symbol
ns
0
-
ns
10
10
-
ns
-
NOTE:
1. 50pf loading on external output signals.
JTAG Clock Input Period tTCK
-
100
-
ns
JTAG Clock HIGH
tTCKHIGH
-
40
-
ns
JTAG Clock Low
tTCKLOW
-
40
-
ns
JTAG Clock Rise Time
tTCKRISE
-
-
5(1)
ns
(1)
ns
JTAG Clock Fall Time
tTCKFALL
-
-
5
JTAG Reset
tRST
-
50
-
ns
JTAG Reset Recovery
tRSR
-
50
-
ns
NOTE:
1. Guaranteed by design.
15
Max. Units
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
The Standard JTAG interface consists of four basic elements:
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
JTAG INTERFACE
•
•
•
•
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V14320/72V15320/
72V16320/72V17320/72V18320/72V19320 incorporates the necessary tap
controller and modified pad cells to implement the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
TMS
TCLK
TRST
P
TAP
clkDR, ShiftDR
UpdateDR
Controller
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
6163 drw08
Figure 3. Boundary Scan Architecture
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
16
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
1
Test-Logic
Reset
0
0
INDUSTRIAL
TEMPERATURE RANGE
Run-Test/
Idle
1
SelectDR-Scan
1
SelectIR-Scan
1
0
1
0
Capture-IR
1
Capture-DR
0
0 0
Shift-DR
Shift-IR
1
1
EXit1-DR
Input = TMS
1
0
1
Exit2-DR
Exit2-IR
0
1
1
Update-IR
Update-DR
0
0
Pause-IR
1
1
1
Exit1-IR
0 0
Pause-DR
0
0
1
0
6163 drw09
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 4. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling the
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
17
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at UpdateIR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
IDT72V14320/15320/16320/17320/18320/19320 JTAG Device Identification Register
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
•
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Hex
Value
0x00
0x02
0x01
0x03
0x0F
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
Instruction
Function
EXTEST
IDCODE
SAMPLE/PRELOAD
HIGH-IMPEDANCE
BYPASS
Select Boundary Scan Register
Select Chip Identification data register
Select Boundary Scan Register
JTAG
Select Bypass Register
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
For the IDT72V14320/72V15320/72V16320/72V17320/72V18320/
72V19320, the Part Number field contains the following values:
Device
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
INDUSTRIAL
TEMPERATURE RANGE
IIDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST pin or by otherwise moving to the
Test-Logic-Reset state.
Part# Field
04E5
04E4
04E3
04E2
04E1
04E0
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
18
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
INDUSTRIAL
TEMPERATURE RANGE
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
19
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
tRS
MRS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN
WEN
SI
LD
tRSS
FSEL0,
FSEL1
tRSS
PFM
tRSS
SEN
tRSF
EF
tRSF
FF
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
Figure 5. Master Reset Timing
20
6163 drw10
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
tRS
PRS
tRSS
tRSR
REN
tRSS
tRSR
WEN
tRSS
SEN
tRSF
EF
tRSF
FF
tRSF
PAE
tRSF
PAF,
HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
Figure 6. Partial Reset Timing
21
6163 drw11
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
tCLK
tCLKH
NO WRITE
WCLK
tSKEW1
NO WRITE
tCLKL
2
1
1
(1)
(1)
tDS
D0 - Dn
2
tSKEW1
tDH
tDS
DX
tWFF
tWFF
tWFF
tWFF
tDH
DX+1
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
tA
Q0 - Qn
tA
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
6163 drw12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing
tCLK
tCLKH
1
RCLK
tENS
tCLKL
2
tENH
tENS
REN
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
LAST WORD
Q0 - Qn
tOLZ
OE
LAST WORD
tA
D0
D1
tOLZ
tOHZ
tOE
(1)
tSKEW1
WCLK
tENS
tENH
tENS
tDH
tDS
tENH
WEN
tDS
D0 Dn
D0
tDH
D1
6163 drw13
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing
22
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
WCLK
tENS
tENH
tENH
SEN
tLDS
tLDH
tLDH
LD
tDH
tDS
BIT 0
SI
BIT X
(1)
BIT 0
BIT X
EMPTY OFFSET
(1)
6163 drw20
FULL OFFSET
NOTE:
1. X = 9 for the IDT72V14320 (total of 20 bits), X = 10 for the IDT72V15320 (total of 22 bits), X = 11 for the IDT72V15160 and IDT72V16320 (total of 24 bits), X = 12 for the IDT72V16160,
and IDT72V17320 (total of 26 bits), X = 13 for the IDT72V17160 and IDT72V18320 (total of 28 bits), X = 14 for the IDT72V18160 and IDT72V19320 (total of 30 bits), X = 15 for the
IDT72V19160 (total of 32 bits).
Figure 9. Serial Loading of Programmable Flag Registers
tCLKL
tCLKL
WCLK
1
tENS
1
2
2
tENH
WEN
tPAFS
PAF
D - (m+1) words in FIFO
tPAFS
(2)
D - m words in FIFO
(3)
tSKEW2
(2)
D-(m+1) words
in FIFO(2)
RCLK
tENS
tENH
REN
6163 drw23
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 10. Synchronous Programmable Almost-Full Flag Timing
23
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
tCLKH
INDUSTRIAL
TEMPERATURE RANGE
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO ,
tSKEW2
RCLK
n words in FIFO
n+1 words in FIFO
(2)
1
tPAES
tPAES
2
1
tENS
2
tENH
REN
6163 drw24
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. PAE is asserted and updated on the rising edge of WCLK only.
4. Select this mode by setting PFM HIGH during Master Reset.
Figure 11. Synchronous Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAFA
PAF
D - m words
in FIFO
D - (m + 1) words in FIFO
D - (m + 1)
words in FIFO
tPAFA
RCLK
tENS
REN
6163 drw25
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 12. Asynchronous Programmable Almost-Full Flag Timing
24
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
tCLKH
INDUSTRIAL
TEMPERATURE RANGE
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
PAE
n + 1 words in FIFO
n words in FIFO
n words in FIFO
tPAEA
RCLK
tENS
REN
6163 drw26
NOTES:
1. n = PAE offset.
2. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
3. Select this mode by setting PFM LOW during Master Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
tHF
HF
D/2 words in FIFO
D/2 + 1 words in FIFO
D/2 words in FIFO
tHF
RCLK
tENS
REN
6163 drw27
NOTES:
1. D = maximum FIFO depth.
V-III: D = 4,096 for the IDT72V15160 and 8,192 for the IDT72V16160, 16,384 for the IDT72V17160 and 32,768 for the IDT72V18160, 65,526 for the IDT72V19160.
Vx-III: D = 1,024 for the IDT72V14320, 2,048 for the IDT72V15320, 4,096 for the IDT72V16320 and 8,192 for the IDT72V17320, 16,384 for the IDT72V18320 and 32,768 for the
IDT72V19320.
Figure 14. Half-Full Flag Timing
25
ORDERING INFORMATION
IDT
XXXXX
X
Device Type
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
I
Industrial (-40°C to +85°C)
PF
BB
Thin Plastic Quad Flatpack (TQFP, PN80-1, PK128-1)
Plastic Ball Grid Array (PBGA, BB144-1, Vx-III only)
10
Industrial
L
Low Power
72V15160
72V16160
72V17160
72V18160
72V19160
4,096 x 16  3.3V Multimedia FIFO, V-III
8,192 x 16  3.3V Multimedia FIFO, V-III
16,384 x 16  3.3V Multimedia FIFO, V-III
32,768 x 16  3.3V Multimedia FIFO, V-III
65,526 x 16  3.3V Multimedia FIFO, V-III
72V14320
72V15320
72V16320
72V17320
72V18320
72V19320
1,024 x 32  3.3V Multimedia FIFO, Vx-III
2,048 x 32  3.3V Multimedia FIFO, Vx-III
4,096 x 32  3.3V Multimedia FIFO, Vx-III
8,192 x 32  3.3V Multimedia FIFO, Vx-III
16,384 x 32  3.3V Multimedia FIFO, Vx-III
32,768 x 32  3.3V Multimedia FIFO, Vx-III
Clock Cycle Time (tCLK)
Speed in Nanoseconds
6163 drw05
DATASHEET DOCUMENT HISTORY
11/17/2003
pg. 1.
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26
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