Maxim MAX1858EEG Dual 180â° out-of-phase pwm step-down controller with power sequencing and por Datasheet

19-2432; Rev 0; 7/02
ANUAL
N KIT M
IO
T
A
U
EVAL
BLE
AVAILA
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
The MAX1858 dual, synchronized, step-down controller
generates two outputs from input supplies ranging from
4.75V to 23V. Each output is adjustable from sub-1V to
18V and supports loads of 10A or higher. Input voltage
ripple and total RMS input ripple current are reduced by
synchronized 180° out-of-phase operation.
The switching frequency is adjustable from 100kHz to
600kHz with an external resistor. Alternatively, the controller can be synchronized to an external clock generated to another MAX1858 or a system clock. One
MAX1858 can be set to generate an in-phase, or 90°
out-of-phase, clock signal for synchronization with additional controllers. This allows two controllers to operate
either as an interleaved two- or four-phase system with
each output shifted by 90°. The device also features
“first-on/last-off” power sequencing for compatibility
with DSPs, ASICs, and FPGAs, as well as soft-start and
soft-stop to ensure reliable and repeatable power
sequencing.
The MAX1858 eliminates the need for current-sense
resistors by utilizing the low-side MOSFET’s on-resistance
as a current-sense element. This protects the DC-DC
components from damage during output-overload conditions or when output short-circuit faults without requiring a
current-sense resistor. Adjustable foldback current limit
reduces power dissipation during short-circuit condition.
A power-on reset output signals the system when both
outputs reach regulation.
The MAX1858 is available in a 24-pin QSOP package.
An evaluation kit is available to speed designs.
Features
♦ Two Independent Output Voltages
♦ 180° Out-of-Phase Operation
♦ 90° Out-of-Phase Operation
(Using Two MAX1858s)
♦ Foldback Current Limit
♦ 4.75V to 23V Input Supply Range
♦ 0 to 18V Output-Voltage Range (Up to 10A)
♦ >90% Efficiency
♦ Fixed-Frequency Pulse-Width Modulation (PWM)
Operation
♦ Adjustable 100kHz to 600kHz Switching
Frequency
♦ External SYNC Input
♦ Clock Output for Master/Slave Synchronization
♦ Power-On/-Off Sequencing with Soft-Start and
Soft-Stop
♦ RST Output with 140ms Minimum Delay
♦ Lossless Current Limit (No Sense Resistor)
Ordering Information
PART
MAX1858EEG
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
24 QSOP
Applications
Pin Configuration
Network Power Supplies
Telecom Power Supplies
DSP, ASIC, and FPGA Power Supplies
Set-Top Boxes
Broadband Routers
Servers
TOP VIEW
COMP2 1
24 EN
FB2 2
23 DH2
ILIM2 3
22 LX2
OSC 4
21 BST2
V+ 5
REF 6
Typical Operating Circuit appears at end of data sheet.
20 DL2
MAX1858
19 VL
GND 7
18 PGND
CKO 8
17 DL1
SYNC 9
16 BST1
ILIM1 10
15 LX1
FB1 11
14 DH1
COMP1 12
13 RST
QSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1858
General Description
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +25V
PGND to GND .......................................................-0.3V to +0.3V
VL to GND ..................-0.3V to the lower of +6V and (V+ + 0.3V)
BST1, BST2 to GND ...............................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
DL1, DL2 to PGND........................................-0.3V to (VL + 0.3V)
CKO, REF, OSC, ILIM1, ILIM2,
COMP1, COMP2 to GND ..........................-0.3V to (VL + 0.3V)
FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V
VL to GND Short Circuit..............................................Continuous
REF to GND Short Circuit ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60kΩ,
compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
V+ Operating Range
(Note 2)
4.75
23
VL = V+ (Note 2)
4.75
5.5
V
V+ Operating Supply Current
VL unloaded, no MOSFETs connected
3.5
6
mA
V+ Standby Supply Current
EN = LX_ = FB_ = 0V
ROSC = 60kΩ
0.3
0.6
mA
Thermal Shutdown
Rising temperature, typical hysteresis = 10°C
160
Current-Limit Threshold
PGND - LX_
VL REGULATOR
Output Voltage
°C
ILIM_ = VL
75
100
RILIM_ = 100kΩ
32
50
62
RILIM_ = 600kΩ
225
300
375
5.5V < V+ < 23V, 1mA < ILOAD < 50mA
4.75
5
5.25
V
4.4
4.55
4.7
V
1.98
2.00
2.02
V
0
4
10
mV
VL Undervoltage Lockout
Trip Level
125
mV
REFERENCE
Output Voltage
IREF = 0µA
Reference Load Regulation
0µA < IREF < 50µA
SOFT-START
Digital Ramp Period
Internal 6-bit DAC for one converter to ramp from 0V to
full scale (Note 3)
Soft-Start Steps
1024
DC-DC
Clocks
64
Steps
FREQUENCY
2
Low End of Range
ROSC = 60kΩ
High End of Range
ROSC = 10kΩ
DH_ Minimum Off-Time
ROSC = 10kΩ
0°C to +85°C
84
100
115
-40°C to +85°C
80
100
120
540
600
660
kHz
250
303
ns
_______________________________________________________________________________________
kHz
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL = 0mA, PGND = GND, CREF = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 60kΩ,
compensation components for COMP_ are from Figure 1, TA = -40°C to +85°C (Note 1), unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
SYNC Range
Internal oscillator nominal frequency must be set to half
of SYNC frequency
200
SYNC Input Pulse Width
(Note 3)
SYNC Rise/Fall Time
(Note 3)
High
100
Low
100
TYP
MAX
UNITS
1200
kHz
ns
100
ns
250
nA
ERROR AMPLIFIER
FB_ Input Bias Current
FB_ Input Voltage Set Point
FB_ to COMP_ Transconductance
0°C to +85°C
0.985
1.00
1.015
-40°C to +85°C
0.98
1.00
1.02
0°C to +85°C
1.25
1.8
2.70
-40°C to +85°C
1.2
1.8
2.9
V
mS
DRIVERS
DL_, DH_ Break-Before-Make Time
DH_ On-Resistance
DL_ On-Resistance
CLOAD = 5nF
30
ns
Low
1.5
2.5
High
3
5
Low
0.6
1.5
High
3
5
Ω
Ω
LOGIC INPUTS (EN, SYNC)
Input Low Level
Typical 15% hysteresis, VL = 4.75V
Input High Level
VL = 5.5V
2.4
Input High/Low Bias Current
VEN = 0 or 5.5V
-1
0.8
V
+1
µA
0.4
V
V
0.1
LOGIC OUTPUTS (CKO)
Output Low Level
VL = 5V, sinking 5mA
Output High Level
VL = 5V, sourcing 5mA
4.0
V
COMP_
Pulldown Resistance During
Shutdown and Current Limit
Ω
17
RST OUTPUT
Output-Voltage Trip Level
Output Low Level
Both FBs must be over this to allow the reset timer to
start; there is no hysteresis
0.87
0.9
0.93
VL = 5V, sinking 3.2mA
0.4
VL = 1V, sinking 0.4mA
0.3
Output Leakage
V+ = VL = 5V, V RST = 5.5V, VFB = 1V
Reset Timeout Period
VFB_=1V
FB_ to Reset Delay
FB_ overdrive from 1V to 0.85V
140
315
4
V
V
1
µA
560
ms
µs
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Operating supply range is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation.
Note 3: Guaranteed by design and not production tested.
_______________________________________________________________________________________
3
MAX1858
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Circuit of Figure 1, VIN = 12V, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD
OUTPUT-VOLTAGE ACCURACY vs. LOAD
EFFICIENCY (%)
OUT1
70
60
50
40
30
20
MAX1858 toc02
OUT2
80
1.0
0.8
OUTPUT VOLTAGE ACCURACY (%)
90
MAX1858 toc01
100
10
0.6
0.4
0.2
OUT2
0
-0.2
OUT1
-0.4
-0.6
-0.8
-1.0
0
0.1
1
10
0
100
5
LOAD (A)
15
10
LOAD (A)
VL VOLTAGE ACCURACY
vs. LOAD CURRENT
SWITCHING FREQUENCY vs. ROSC
-0.5
-1.0
-1.5
MAX1858 toc04
0
600
SWITCHING FREQUENCY (kHz)
MAX1858 toc03
0.5
VL VOLTAGE ACCURACY
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
500
400
300
200
100
-2.0
0
0
50
100
150
LOAD CURRENT (mA)
0
10
20
30
40
50
LOAD TRANSIENT RESPONSE (OUTPUT 2)
LOAD TRANSIENT RESPONSE (OUTPUT 1)
MAX1858 toc06
MAX1858 toc05
VOUT1
50mV/div
AC-COUPLED
VOUT2
50mV/div
AC-COUPLED
10µs/div
4
60
ROSC (kΩ)
VOUT2
50mV/div
AC-COUPLED
VOUT1
50mV/div
AC-COUPLED
10A
IOUT1
10A
IOUT2
0A
0A
10µs/div
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
RESET TIMEOUT
SOFT-START AND SOFT-STOP WAVEFORM
MAX1858 toc07
OUT-OF-PHASE WAVEFORM
MAX1858 toc08
5V
VEN
0V
MAX1858 toc09
VOUT1
20mV/div
5V/div
EN
0V
12V
VLX1
VOUT2
VOUT2
1V/div
0V
12V
VLX2
0V
VOUT1
0V
0V
0V
VRST
0V
VOUT1
1V/div
0V
VOUT2
20mV/div
100ms/div
1ms/div
EXTERNALLY SYNCHRONIZED
SWITCHING WAVEFORM
MAX1858 toc10
1µs/div
CKO OUTPUT WAVEFORM
MAX1858 toc11
5V
VSYNC
0V
SYNC = GND
5V
VCK0
0V
5V
VCK0
0V
10V
VLX1
0V
10V
VLX1
0V
VOUT1
10mV/div
AC-COUPLED
VOUT1
10mV/div
AC-COUPLED
400ns/div
400ns/div
SHORT-CIRCUIT CURRENT
FOLDBACK AND RECOVERY
CKO OUTPUT WAVEFORM
MAX1858 toc12
MAX1858 toc13
SYNC = VL
IOUT1 = 10A (5A/div)
VOUT1 = 1.8V (1V/div)
5V
VCK0
0V
10V
VLX1
0V
SHORT
VOUT2
VOUT2 = 2.5V (1V/div)
IOUT2 = 10A (5A/div)
VOUT1
10mV/div
400ns/div
_______________________________________________________________________________________
5
MAX1858
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN = 12V, TA = +25°C, unless otherwise noted.)
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
MAX1858
Pin Description
PIN
NAME
FUNCTION
1
COMP2
Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series
resistor (RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor
(CCOMP2B) as shown in Figure 1.
2
3
4
ILIM2
Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to
100mV if ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the
REG2’s current-limit threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ). See
the Setting the Valley Current Limit section.
OSC
Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the
oscillator, so the switching frequency equals half the synchronization frequency (fSW = fOSC/2).
Connect a resistor from OSC to GND (ROSC) to set the switching frequency from 100kHz (ROSC =
60kΩ) to 600kHz (ROSC = 10kΩ). The controller still requires ROSC when an external clock is
connected to SYNC. When using SYNC, set ROSC for one half of the SYNC input.
5
V+
Input Supply Voltage. 4.75V to 23V.
6
REF
2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.
7
GND
Analog Ground
8
CKO
Clock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization
(SYNC, CKO) section).
SYNC
Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect
SYNC to a 200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase
operation as a master controller. Connect SYNC to VL for 4-phase operation as a master controller
(see the Clock Synchronization (SYNC, CKO) section).
ILIM1
Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to
100mV if ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s
current-limit threshold (VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ). See the
Setting the Valley Current Limit section.
11
FB1
Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1’s output
and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,
connect FB1 to a resistive voltage-divider from REF and REG1’s output. See the Setting the Output
Voltage section.
12
COMP1
9
10
13
6
FB2
Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2’s output
and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,
connect FB2 to a resistive voltage-divider from REF to REG2’s output. See the Setting the Output
Voltage section.
RST
Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series
resistor (RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor
(CCOMP1B) as shown in Figure 1.
Open-Drain Reset Output. RST is low when either output voltage is more than 10% below its
regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output
voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high
impedance as long as both outputs maintain regulation. Connect a resistor between RST and the
logic supply for logic-level voltages.
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
PIN
NAME
14
DH1
High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1.
15
LX1
External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the
inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver.
16
BST1
Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic
capacitor and diode according to Figure 1.
17
DL1
Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL.
18
PGND
19
VL
20
DL2
Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL.
21
BST2
Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic
capacitor and diode according to Figure 1.
22
LX2
23
DH2
24
EN
FUNCTION
Power Ground
Internal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers
and external boost circuitry for the high-side gate drivers.
External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the
inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver.
High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2.
Active-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on
operation.
Detailed Description
DC-DC PWM Controller
The MAX1858 step-down converters use a PWM voltage-mode control scheme (Figure 2) for each out-ofphase controller. The controller generates the clock
signal by dividing down the internal oscillator or SYNC
input when driven by an external clock, so each controller’s switching frequency equals half the oscillator
frequency (fSW = fOSC/2). An internal transconductance
error amplifier produces an integrated error voltage at
the COMP pin, providing high DC accuracy. The voltage at COMP sets the duty cycle using a PWM comparator and a ramp generator. At each rising edge of
the clock, REG1’s high-side N-channel MOSFET turns
on and remains on until either the appropriate duty
cycle or until the maximum duty cycle is reached.
REG2 operates out-of-phase, so the second high-side
MOSFET turns on at each falling edge of the clock.
During each high-side MOSFET’s on-time, the associated inductor current ramps up.
During the second-half of the switching cycle, the highside MOSFET turns off and the low-side N-channel
MOSFET turns on. Now the inductor releases the stored
energy as its current ramps down, providing current to
the output. Under overload conditions, when the induc-
tor current exceeds the selected valley current-limit
(see the Current-Limit Circuit (ILIM_) section), the highside MOSFET does not turn on at the appropriate clock
edge and the low-side MOSFET remains on to let the
inductor current ramp down.
Synchronized Out-of-Phase Operation
The two independent regulators in the MAX1858 operate 180° out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (EMI), and
improve efficiency. This effectively lowers component
cost and saves board space, making the MAX1858
ideal for cost-sensitive applications.
Dual-switching regulators typically operate both controllers in-phase, and turn on both high-side MOSFETs
at the same time. The input capacitor must then support the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current when compared to a single switching regulator. The higher RMS ripple current lowers efficiency due to power loss associated with the input
capacitor’s effective series resistance (ESR). This typically requires more low-ESR input capacitors in parallel
to minimize input voltage ripple and ESR-related losses, or to meet the necessary ripple-current rating.
_______________________________________________________________________________________
7
MAX1858
Pin Description (continued)
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
VIN
6V - 23V
RV+
4.7Ω
0.1µF
V+
CV+
0.22µF
CIN1
2 × 10µF
VL
4.7Ω
BST1
COUT1
4 × 220µF
NH1*
L1
1µH
R1A
8.06kΩ
**
NL1*
CIN2
2 × 10µF
BST2
CBST2
0.1µF
CBST1
0.1µF
OUTPUT1
VOUT = 1.8V
CVL
4.7µF
4.7Ω
DH1
DH2
LX1
LX2
DL1
DL2
NH2*
L2
1.2µH
**
NL2*
OUTPUT2
VOUT = 2.5V
R2A
15kΩ
COUT2
4 × 220µF
PGND
FB1
FB2
RCOMP1
5.9kΩ
R1B
10kΩ
RCOMP2
8.2kΩ
COMP1
CCOMP1B
100pF
CCOMP1A
10nF
R2B
10kΩ
COMP2
CCOMP2B
100pF
D2
CMSSH-3
MAX1858
REF
OSC
CCOMP2A
6.8nF
D3
CMSSH-3
CREF
0.22µF
GND
CLOCK OUTPUT
CKO
RESET OUTPUT
RST
SYNC
VL
118kΩ
96.5kΩ
ILIM1
ON
EN
ILIM2
OFF
140kΩ
*IRF7811W
**OPTIONAL
84.5kΩ
Figure 1. Standard Application Circuit
With dual synchronized out-of-phase operation, the
MAX1858’s high-side MOSFETs turn on 180° out-ofphase. The instantaneous input current peaks of both
regulators no longer overlap, resulting in reduced RMS
ripple current and input voltage ripple. This reduces the
required input capacitor ripple-current rating, allowing
fewer or less expensive capacitors, and reduces shielding requirements for EMI. The Out-of-Phase Waveforms
in the Typical Operating Characteristics demonstrate
synchronized 180° out-of-phase operation.
8
Internal 5V Linear Regulator (VL)
All MAX1858 functions are internally powered from an
on-chip, low-dropout 5V regulator. The maximum regulator input voltage (V+) is 23V. Bypass the regulator’s
output (VL) with a 4.7µF ceramic capacitor to PGND.
The VL dropout voltage is typically 500mV, so when V+
is greater than 5.5V, VL is typically 5V. The MAX1858
also employs an undervoltage lockout circuit that disables both regulators when V L falls below 4.5V. V L
should also be bypassed to GND with 0.1µF.
_______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
MAX1858
REF
VREF
2V
V+
5V LINEAR
REGULATOR
MAX1858
GND
VL
COMP1
BST1
FB1
CONVERTER 1
DH1
SOFT-START
DAC
SEQUENCING
LX1
R
Q
S
Q
DL1
PGND
OSC
SYNC
OSCILLATOR
CK0
5µA
RST
ILIM1
RESET
EN
VREF
UVLO
AND
SHUTDOWN
VL - 0.5V
VL
BST2
DH2
CONVERTER 2
LX2
DL2
COMP2
FB2
ILIM2
Figure 2. Functional Diagram
The internal VL linear regulator can source over 50mA
to supply the IC, power the low-side gate driver, charge
the external boost capacitor, and supply small external
loads. When driving large FETs, little or no regulator current may be available for external loads. For example,
when switched at 600kHz, a single large FET with 18nC
total gate charge requires 18nC x 600kHz = 11mA. To
drive larger MOSFETs, or deliver larger loads, connect
VL to an external power supply from 4.75V to 5.5V.
_______________________________________________________________________________________
9
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
High-Side Gate-Drive Supply (BST_)
Gate-drive voltages for the high-side N-channel switches are generated by the flying-capacitor boost circuits
(Figure 3). A boost capacitor (connected from BST_ to
LX_) provides power to the high-side MOSFET driver.
On startup, the synchronous rectifier (low-side
MOSFET) forces LX_ to ground and charges the boost
capacitor to 5V. On the second half-cycle, after the lowside MOSFET turns off, the high-side MOSFET is turned
on by closing an internal switch between BST_ and
DH_. This provides the necessary gate-to-source voltage to turn on the high-side switch, an action that
boosts the 5V gate-drive signal above VIN. The current
required to drive the high-side MOSFET gates
(fSWITCH ✕ QG) is ultimately drawn from VL.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moderate-size N-channel high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor seen
with large VIN - VOUT differential. The DL_ low-side drive
waveform is always the complement of the DH_ high-side
drive waveform (with controlled dead time to prevent
cross-conduction or “shoot-through”). An adaptive deadtime circuit monitors the DL_ output and prevents the
high-side FET from turning on until DL_ is fully off. There
must be a low-resistance, low-inductance path from the
DL_ driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the sense
circuitry in the MAX1858 interprets the MOSFET gate as
“off” while there is actually charge still left on the gate.
Use very short, wide traces (50mils to 100mils wide if the
MOSFET is 1in from the device). The dead time at the
DH-off edge is determined by a fixed 30ns internal delay.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch.
Additionally, the MAX1858 uses the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal.
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5Ω (typ) on-resistance. This low onresistance helps prevent DL_ from being pulled up during the fast rise-time of the LX_ node, due to capacitive
coupling from the drain to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current
applications, some combinations of high- and low-side
FETs can cause excessive gate-drain coupling, leading
to poor efficiency, EMI, and shoot-through currents.
This can be remedied by adding a resistor (typically
less than 5Ω) in series with BST_, which increases the
turn-on time of the high-side FET without degrading the
turn-off time (Figure 3).
10
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” currentsensing algorithm that uses the on-resistance of the
low-side MOSFET as a current-sensing element. If the
current-sense signal is above the current-limit threshold, the MAX1858 does not initiate a new cycle (Figure
4). Since valley current sensing is employed, the actual
peak current is greater than the current-limit threshold
by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the low-side
MOSFET’s on-resistance, current-limit threshold, inductor value, and input voltage. The reward for this uncertainty is robust, lossless overcurrent sensing that does
not require costly sense resistors.
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section). The current-limit threshold is adjusted with an external resistor at ILIM_ (Figure
1). The adjustment range is from 50mV to 300mV, corresponding to resistor values of 100kΩ to 600kΩ. In
adjustable mode, the current-limit threshold across the
low-side MOSFET is precisely 1/10th the voltage seen
at ILIM_. However, the current-limit threshold defaults
to 100mV when ILIM is tied to VL. The logic threshold
for switchover to this 100mV default value is approximately V L - 0.5V. Adjustable foldback current limit
reduces power dissipation during short-circuit conditions (see the Design Procedure section).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the current-sense signals seen by LX_ and PGND. The IC
must be mounted close to the low-side MOSFET with
short, direct traces making a Kelvin sense connection
so that trace resistance does not add to the intended
sense resistance of the low-side MOSFET.
Undervoltage Lockout and Startup
If VL drops below 4.5V, the MAX1858 assumes that the
supply and reference voltages are too low to make
valid decisions and activates the undervoltage lockout
(UVLO) circuitry which forces DL and DH low to inhibit
switching. RST is also forced low during UVLO. After VL
rises above 4.5V, the controller powers up the outputs.
Enable (EN), Soft-Start, and Soft-Stop
Pull EN high to enable or low to shutdown both regulators. During shutdown the supply current drops to 1mA
(max), LX enters a high-impedance state (DH_ connected to LX_, and DL_ connected to PGND), and
COMP_ is discharged to GND through a 17Ω resistor.
VL and REF remain active in shutdown. For “always-on”
operation, connect EN to VL.
______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ply voltage. A 100kΩ resistor works well for most applications. If unused, leave RST grounded or unconnected.
Clock Synchronization (SYNC, CKO)
VL
BST_
5Ω
DH_
LX_
MAX1858
Figure 3. Reducing the Switching-Node Rise Time
On the rising edge of EN both controllers enter softstart. Soft-start gradually ramps up to the reference
voltage seen by the error amplifier in order to control
the outputs’ rate of rise and reduce input surge currents during startup. The soft-start period is 1024 clock
cycles (1024/f SW ), and the internal soft-start DAC
ramps up the voltage in 64 steps. The output reaches
regulation when soft-start is completed. On the falling
edge of EN both controllers simultaneously enter softstop, which reverses the soft-start ramp. The part
enters shutdown after soft-stop is complete.
Output-Voltage Sequencing
After the startup circuitry enables the controller, the
MAX1858 begins the startup sequence. Regulator 1
(OUT1) powers up with soft-start enabled. Once the first
converter’s soft-start sequence ends, Regulator 2 (OUT2)
powers up with soft-start enabled. Finally, when both converters complete soft-start and both output voltages
exceed 90% of their nominal values, the reset output
(RST) goes high (see the Reset Output section). Soft-stop
is initiated by pulling EN low. Soft-stop occurs in reverse
order of soft-start, allowing last-on/first-off operation.
Reset Output
RST is an open-drain output. RST pulls low when either
output falls below 90% of its nominal regulation voltage.
Once both outputs exceed 90% of their nominal regulation voltages and both soft-start cycles are completed,
RST goes high impedance. To obtain a logic-voltage output, connect a pullup resistor from RST to the logic sup-
SYNC serves two functions: SYNC selects the clock output (CKO) type used to synchronize slave controllers, or
it serves as a clock input so the MAX1858 can be synchronized with an external clock signal. This allows the
MAX1858 to function as either a master or slave. CKO
provides a clock signal synchronized to the MAX1858’s
switching frequency, allowing either in-phase (SYNC =
GND) or 90° out-of-phase (SYNC = VL) synchronization
of additional DC-DC controllers (Figure 5). The
MAX1858 supports the following three operating modes:
• SYNC = GND: The CKO output frequency equals
REG1’s switching frequency (fCKO = fDH1) and the
CKO signal is in phase with REG1’s switching frequency. This provides 2-phase operation when synchronized with a second slave controller.
• SYNC = VL: The CKO output frequency equals two
times REG1’s switching frequency (fCKO = 2fDH1)
and the CKO signal is phase shifted by 90° with
respect to REG1’s switching frequency. This provides 4-phase operation when synchronized with a
second MAX1858 (slave controller).
• SYNC Driven by External Oscillator: The controller
generates the clock signal by dividing down the
SYNC input signal, so the switching frequency equals
half the synchronization frequency (fSW = fSYNC/2).
REG1’s conversion cycles initiate on the rising edge
of the internal clock signal. The CKO output frequency and phase match REG1’s switching frequency
(fCKO = fDH1) and the CKO signal is in phase. Note
that the MAX1858 still requires ROSC when SYNC is
externally clocked and the internal oscillator frequency should be set to 50% of the synchronization frequency (fOSC = 0.5fSYNC).
Thermal Overload Protection
Thermal overload protection limits total power dissipation
in the MAX1858. When the device’s die-junction temperature exceeds TJ = +160°C, an on-chip thermal sensor
shuts down the device, forcing DL_ and DH_ low, allowing the IC to cool. The thermal sensor turns the part on
again after the junction temperature cools by 10°C.
During thermal shutdown, the regulators shut down, RST
goes low, and soft-start is reset. If the VL linear-regulator
output is short-circuited, thermal-overload protection is
triggered.
______________________________________________________________________________________________________
11
MAX1858
INPUT
(VIN)
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
-IPEAK
INDUCTOR CURRENT
ILOAD
ILIMIT
0
where tON(MIN) is 100ns. The minimum input voltage is
limited by the switching frequency and minimum offtime, which determine the maximum duty cycle
(DMAX = 1 - fSWtOFF(MIN)):
V
+ VDROP1 
VIN(MIN) =  OUT
 + VDROP2 - VDROP1
 1- fSW t OFF(MIN) 
where VDROP1 is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances. VDROP2 is the
sum of the resistances in the charging path, including
high-side switch, inductor, and PC board resistances.
TIME
Setting the Output Voltage
Figure 4. “Valley” Current-Limit Threshold Point
Design Procedure
Effective Input Voltage Range
Although, the MAX1858 controller can operate from
input supplies ranging from 4.75V to 23V, the input voltage range can be effectively limited by the MAX1858’s
duty-cycle limitations. The maximum input voltage is
limited by the minimum on-time (tON(MIN)):
VIN(MAX) ≤
For 1V or greater output voltages, set the MAX1858 output voltage by connecting a voltage-divider from the
output to FB_ to GND (Figure 6). Select R_B (FB_ to
GND resistor) to between 1kΩ and 10kΩ. Calculate
R_A (OUT_ to FB_ resistor) with the following equation:
 V
 
R _ A = R _ B  OUT  -1
 VSET  
where VSET = 1.00V (see the Electrical Characteristics)
and VOUT can range from VSET to 18V.
VOUT
t ON(MIN)fSW
MAX1858
MAX1858
CK0
OSC
SYNC
CK0
OSC
SYNC
VL
MASTER
MAX1858
SYNC
OSC
SYNC
VL
SLAVE
SLAVE
MASTER
2-PHASE SYSTEM
180° PHASE SHIFT
4-PHASE SYSTEM
90° PHASE SHIFT
DH1
MASTER
DH1
MASTER
DH2
DH2
DH1
SLAVE
DH1
SLAVE
DH2
DH2
Figure 5. Synchronized Controllers
12
______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
V

-V
R _ A = -R _ C  SET OUT 
 VREF - VSET 
where V SET = 1V, V REF = 2V (see the Electrical
Characteristics), and VOUT can range from 0 to VSET.
Setting the Switching Frequency
The controller generates the clock signal by dividing
down the internal oscillator or SYNC input signal when
driven by an external oscillator, so the switching frequency equals half the oscillator frequency (fSW = fOSC/2).
The internal oscillator frequency is set by a resistor
(ROSC) connected from OSC to GND. The relationship
between fSW and ROSC is:
ROSC =
6 × 109
Ω - Hz
S
fSW
where fSW is in Hz, fOSC is in Hz, and ROSC is in Ω. For
example, a 600kHz switching frequency is set with
ROSC = 10kΩ. Higher frequencies allow designs with
lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase.
A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate,
returning the switching frequency to that set by ROSC.
This maintains output regulation even with intermittent
SYNC signals. When an external synchronization signal
is used, ROSC should set the switching frequency to
one half SYNC rate (fSYNC).
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX1858: inductance value (L),
peak-inductor current (I PEAK ), and DC resistance
(RDC). The following equation assumes a constant ratio
of inductor peak-to-peak AC current to DC average
current (LIR). For LIR values too high, the RMS currents
are high, and therefore I 2 R losses are high. Large
inductances must be used to achieve very low LIR values. Typically inductance is proportional to resistance
(for a given package type) which again makes I2R losses high for very low LIR values. A good compromise
between size and loss is a 30% peak-to-peak ripple
current to average-current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and
selected LIR determine the inductor value as follows:
V
(V - V
)
L = OUT IN OUT
VINfSWIOUTLIR
where VIN, VOUT, and IOUT are typical values (so that
efficiency is optimum for typical conditions). The switching frequency is set by R OSC (see the Setting the
Switching Frequency section). The exact inductor value
is not critical and can be adjusted in order to make
trade-offs among size, cost, and efficiency. Lower
inductor values minimize size and cost, but also
improve transient response and reduce efficiency due
to higher peak currents. On the other hand, higher
inductance increases efficiency by reducing the RMS
current. However, resistive losses due to extra wire turns
can exceed the benefit gained from lower AC current
levels, especially when the inductance is increased
without also allowing larger inductor dimensions.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The
inductor’s saturation rating must exceed the peakinductor current at the maximum defined load current
(ILOAD(MAX)):
 LIR 
IPEAK = ILOAD(MAX ) + 
I
 2  LOAD(MAX )
Setting the Valley Current Limit
The minimum current-limit threshold must be high enough
to support the maximum expected load current with the
worst-case low-side MOSFET on-resistance value since
the low-side MOSFET’s on-resistance is used as the current-sense element. The inductor’s valley current occurs
at ILOAD(MAX) minus half of the ripple current. The current-sense threshold voltage (VITH) should be greater
than voltage on the low-side MOSFET during the ripplecurrent valley:
 LIR 
VITH > RDS(ONMAX

,
) × ILOAD(MAX) × 1
2 
where R DS(ON) is the on-resistance of the low-side
MOSFET (NL). Use the maximum value for RDS(ON)
from the low-side MOSFET’s data sheet, and additional
margin to account for RDS(ON) rise with temperature is
also recommended. A good general rule is to allow
0.5% additional resistance for each °C of the MOSFET
junction temperature rise.
______________________________________________________________________________________
13
MAX1858
For output voltages below 1V, set the MAX1858 output
voltage by connecting a voltage-divider from the output
to FB_ to REF (Figure 6). Select R_C (FB to REF resistor) in the 1kΩ to 10kΩ range. Calculate R_A with the
following equation:
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Connect ILIM_ to VL for the default 100mV (typ) currentlimit threshold. For an adjustable threshold, connect a
resistor (RILIM_) from ILIM_ to GND. The relationship
between the current-limit threshold (VITH_) and RILIM_ is:
OUT_
REF
R_A
RILIM _ =
FB_
0.5µA
where RILIM_ is in Ω and VITH_ is in V. An RILIM resistance range of 100kΩ to 600kΩ corresponds to a currentlimit threshold of 50mV to 300mV. When adjusting the
current limit, 1% tolerance resistors minimizes error in the
current-limit threshold. For foldback current limit, a resistor (RFBI) is added from ILIM pin to output. The value of
RILIM and RFBI can then be calculated as follows:
First select the percentage of foldback (PFB) from 15%
to 30%, then:
RFBI =
and
PFB × VOUT
5 × 10-6 (1 - PFB )
10 × VITH (1 - PFB ) × RFBI
RILIM =
[VOUT - 10 × VITH (1 - PFB )]
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
as defined by the following equation:
IRMS = ILOAD
VOUT (VIN - VOUT )
VIN
I RMS has a maximum value when the input voltage
equals twice the output voltage (V IN = 2V OUT ), so
IRMS(MAX) = ILOAD / 2. For most applications, nontantalum capacitors (ceramic, aluminum, polymer, or
OSCON) are preferred at the input due to their robustness with high inrush currents typical of systems that can
be powered from very low impedance sources.
Additionally, two (or more) smaller-value low-ESR capacitors can be connected in parallel for lower cost. Choose
an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal longterm reliability.
14
R_C
VITH _
FB_
R_B
R_A
OUT_
MAX1858
MAX1858
VOUT_ > 1V
VOUT_ < 1V
Figure 6. Adjustable Output Voltage
Output Capacitor
The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple voltage, and transient response. The output ripple has two
components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor’s ESR caused by the current flowing in to and out of
the capacitor.
VRIPPLE ≅ VRIPPLE(ESR) + VRIPPLE(C)
The output voltage ripple as a consequence of the ESR
and output capacitance is:
VRIPPLE(ESR) = IP-PRESR
VRIPPLE(C) =
IP-P
8COUT fSW
 V -V
 V

IP-P =  IN OUT   OUT 
 fSWL   VIN 
where IP-P is the peak-to-peak inductor current (see the
Inductor Selection section). These equations are suitable
for initial capacitor selection, but final values should be
verified by testing in a prototype or evaluation circuit.
As a general rule, a smaller inductor ripple current
results in less output ripple voltage. Since inductor ripple current depends on the inductor value and input
voltage, the output ripple voltage decreases with larger
inductance and increases with higher input voltages.
However, the inductor ripple current also impacts transient-response performance, especially at low
VIN - VOUT differentials. Low inductor values allow the
inductor current to slew faster, replenishing charge
______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
 V


L(ILOAD1 - ILOAD2 )2  OUT  + t OFF(MIN) 
 VINfSW 

VSAG =
 VIN - VOUT 

2COUT VOUT 
 - t OFF(MIN) 
 VINfSW 

where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics), and fSW is set by ROSC (see
the Setting the Switching Frequency section).
Compensation
Each voltage-mode controller section employs a
transconductance error amplifier whose output is the
compensation point of the control loop. The control
loop is shown in Figure 7. For frequencies much lower
than Nyquist, the PWM block can be simplified to a
voltage amplifier. Connect RCOMP_ and CCOMP_A from
COMP to GND to compensate the loop (see Figure 7).
The inductor, output capacitor, compensation resistor,
and compensation capacitors determine the loop stability. Since the inductor and output capacitor are chosen based on performance, size, and cost, select the
compensation resistor and capacitors to optimize control-loop stability.
To determine the loop gain (AL), consider the gain from
FB to COMP (A COMP/FB ), from COMP to LX
(ALX/COMP), and from LX to FB (AFB/LX). The total loop
gain is:
AL = A COMP / FB × ALX / COMP × AFB / LX
where:
gM _ COMP
V
A COMP / FB = COMP ≅
VFB
SCCOMP
1+ sRCOMPCCOMP _ A
×
1+ sRCOMPCCOMP _ B
assuming an ideal integrator, and assuming that
CCOMP_B is much less than CCOMP_A.
ALX / COMP =
VLX
VCOMP
=
for frequencies lower than Nyquist.
VIN
VRAMP
1+ sRESRCOUT
V
V
AFB / LX = FB = SET
2
VLX VOUT S LCOUT + SRESRCOUT + 1
V
1+ SRESRCOUT
≅ SET
VOUT VOUT S2LCOUT + 1
Therefore:
AL ≅
gM _ COMP
SCCOMP _ A
×
1 + SRCOMPCCOMP _ A
1 + SRCOMPCCOMP _ B
×
VIN
VRAMP
V
1 + SRESR COUT
× SET ×
VOUT
S2 LC
+1
OUT
For an ideal integrator, this loop gain approaches infinity at DC. In reality the gM amplifier has a finite output
impedance which imposes a finite, but large, loop gain.
It is this large loop gain that provides DC load accuracy. The dominant pole occurs due to the integrator, and
for this analysis, it can be approximated to occur at DC.
RCOMP creates a zero at:
fZ _ COMP _ A =
1
2π × RCOMP _ CCOMP _ A
The inductor and capacitor form a double pole at:
fLC =
1
2π × LCOUT
At some higher frequency the output capacitor’s
impedance becomes insignificant compared to its ESR,
and the LC system becomes more like an LR system,
turning a double pole into a single pole. This zero
occurs at:
fESR =
1
2π × RESRCOUT
A final pole is added using C COMP_B to reduce the
gain and attenuate noise after crossover. This pole
(fCOMP_B) occurs at:
fCOMP _ B =
1
2π × RCOMPCCOMP _ B
Figure 8 shows a Bode plot of the poles and zeros in
their relative locations.
Near crossover the following approximations can be
made to simplify the loop-gain equation:
______________________________________________________________________________________
15
MAX1858
removed from the output filter capacitors by a sudden
load step. The amount of output-voltage sag is also a
function of the maximum duty factor, which can be calculated from the minimum off-time and switching frequency:
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
P
DH
GAIN = +VIN/VRAMP FOR
FREQUENCIES LOWER
THAN NYQUIST
N
L
W
VC
M
DL
LX
N
FB
COMP_
LX
RESR
RESR
=
FB
COUT
COMP_
gM_GROUP
COUT
gM_GROUP
VSET
RCOMP_
CCOMP_A
L
VOUT
VSET
RCOMP_
CCOMP_A
CCOMP_B
CCOMP_B
Figure 7. Fixed-Frequency Voltage-Mode Control Loop
• RCOMP has much higher impedance than CCOMP_A.
This is true if, and only if, crossover occurs above
fZ_COMP_A. If this is true, CCOMP_A can be ignored
(as a short to ground).
• RESR is much higher impedance than COUT. This is
true if, and only if, crossover occurs well after the output capacitor’s ESR zero. If this is true, C OUT
becomes an insignificant part of the loop gain and can
be ignored (as a short to ground).
• CCOMP_B is much higher impedance than RCOMP
and can be ignored (as an open circuit). This is true
if, and only if, crossover occurs far below fCOMP_B.
The following loop-gain equation can be found by using
these previous approximations with Figure 7:
AL ≅
gM _ COMP × RCOMP × RESR
V
× SET ×
VRAMP VOUT
sL
CCOMP _ A =
2 × LCOUT
RCOMP
Choose CCOMP_B so that fCOMP_B occurs at 3 times
fCO using the following equation:
CCOMP _ B =
1
2π × (3 × fCO ) × RCOMP
VIN
Setting the loop gain to 1 and solving for the crossover
frequency yields:
VIN
V
× SET
VRAMP VOUT
gM _ COMP × RCOMP × RESR
fCO = GBW =
×
2π × L
To ensure stability, select RCOMP to meet the following
criteria:
16
• Unity-gain crossover must occur below 1/5th of the
switching frequency.
• For reasonable phase margin using type 1 compensation, fCO must be larger than 5 ✕ fESR.
Choose CCOMP_A so that fZ_COMP_A equals half fLC
using the following equation:
MOSFET Selection
The MAX1858’s step-down controller drives two external logic-level N-channel MOSFETs as the circuit switch
elements. The key selection parameters are:
• On-resistance (RDS(ON))
• Maximum drain-to-source voltage (VDS(MAX))
• Minimum threshold voltage (VTH(MIN))
• Total gate charge (Qg)
• Reverse transfer capacitance (CRSS)
• Power dissipation
______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
50
fLC
40
30
fESR
GAIN (dB)
20
10
fZ-COMP_A
fCO
fSWITCH
0
-10
-20
fCOMP_B
IGATE is the average DH driver output current capability
determined by:
-30
-40
0.001
0.01
0.1
 Q + QGD 
V I
f
PNH(SWITCHING) = IN LOAD OSC  GS

2
 IGATE 
1
FREQUENCY (MHz)
Figure 8. Voltage-Mode Loop Analysis
All four N-channel MOSFETs must be a logic-level type
with guaranteed on-resistance specifications at VGS ≥
4.5V. For maximum efficiency, choose a high-side
MOSFET (NH_) that has conduction losses equal to the
switching losses at the optimum input voltage. Check to
ensure that the conduction losses at minimum input
voltage do not exceed MOSFET package thermal limits,
or violate the overall thermal budget. Also, check to
ensure that the conduction losses plus switching losses
at the maximum input voltage do not exceed package
ratings or violate the overall thermal budget.
Ensure that the MAX1858 DL _ gate driver can drive
NL _. In particular, check that the dv/dt caused by NH_
turning on does not pull up the NL _ gate through NL _’s
drain-to-gate capacitance. This is the most frequent
cause of cross-conduction problems.
Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. All MOSFETs must be selected
so that their total gate charge is low enough that VL can
power all four drivers without overheating the IC:
PVL = VIN × QG _ TOTAL × fSW
MOSFET package power dissipation often becomes a
dominant design factor. I2R power losses are the greatest heat contributor for both high-side and low-side
MOSFETs. I2R losses are distributed between NH_ and
NL _ according to duty factor as shown in the equations
below. Switching losses affect only the high-side
MOSFET, since the low-side MOSFET is a zero-voltage
switched device when used in the buck topology.
IGATE =
(
VL
2 RDS(ON)DH + RGATE
)
where RDS(ON)DH is the high-side MOSFET driver’s onresistance (5Ω max), and RGATE is any series resistance between DH and BST (Figure 3).
V

PNH(CONDUCTION) = ILOAD2RDS(ON)NH  OUT 
 VIN 
PNH(TOTAL) = PNH(SWITCHING) + PNH(CONDUCTION)
 V

PNL = ILOAD2RDS(ON)NL 1-  OUT  
  VIN  
where PNH(CONDUCTION) is the conduction power loss
in the high-side MOSFET, and PNL is the total low-side
power loss.
To reduce EMI caused by switching noise, add a 0.1µF
ceramic capacitor from the high-side switch drain to
the low-side switch source or add resistors in series
with DL_ and DH_ to increase the MOSFETs’ turn-on
and turn-off times.
Applications Information
Dropout Performance
When working with low input voltages, the output-voltage
adjustable range for continuous-conduction operation is
restricted by the minimum off-time (tOFF(MIN)). For best
dropout performance, use the lowest (100kHz) switchingfrequency setting. Manufacturing tolerances and internal
propagation delays introduce an error to the switching
frequency and minimum off-time specifications. This error
is more significant at higher frequencies. Also, keep in
mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output
______________________________________________________________________________________
17
MAX1858
Calculate MOSFET temperature rise according to package thermal-resistance specifications to ensure that
both MOSFETs are within their maximum junction temperature at high ambient temperature. The worst-case
dissipation for the high-side MOSFET (PNH) occurs at
both extremes of input voltage, and the worst-case dissipation for the low-side MOSFET (PNL) occurs at maximum input voltage.
BODE PLOT FOR VOLTAGEMODE CONTROLLERS
MAX1858
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
capacitance must often be added (see the VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the maximum on-time
(∆IUP). The ratio h = ∆IUP/∆IDOWN is an indicator of the
ability to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V SAG greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
V
+ VDROP1 
VIN(MIN) =  OUT
 + VDROP2 - VDROP1
 1- hfSW t OFF(MIN) 
where VDROP1 is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the resistances in the charging path, including high-side switch, inductor, and PC board resistances; and t OFF(MIN) is from the Electrical
Characteristics. The absolute minimum input voltage is
calculated with h = 1.
If the calculated V+(MIN) is greater than the required minimum input voltage, then reduce the operating frequency
or add output capacitance to obtain an acceptable
VSAG. If operation near dropout is anticipated, calculate
VSAG to be sure of adequate transient response.
Dropout Design Example:
VOUT = 5V
fSW = 600kHz
tOFF(MIN) = 250ns
VDROP1 = VDROP2 = 100mV
h = 1.5


5V + 100mV
VIN(MIN) = 

.
(
)(
)
kHz
ns
1
1
5
600
250


+ 100mV - 100mV = 6.58V
Calculating again with h = 1 gives the absolute limit of
dropout:
18


5V + 100mV
VIN(MIN) = 

(
)(
)
kHz
ns
1
600
250


+ 100mV - 100mV = 6V
Therefore, VIN must be greater than 6V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 6.58V.
Improving Noise Immunity
Applications where the MAX1858 must operate in noisy
environments can typically adjust their controller’s compensation to improve the system’s noise immunity. In particular, high-frequency noise coupled into the feedback
loop causes jittery duty cycles. One solution is to lower
the crossover frequency (see the Compensation section).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially
true for dual converters where one channel can affect
the other. Refer to the MAX1858 EV kit data sheet for a
specific layout example.
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
• Isolate the power components on the top side from
the analog components on the bottom side with a
ground shield. Use a separate PGND plane under
the OUT1 and OUT2 sides (referred to as PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run the
power plane ground currents on the top side only.
• Use a star ground connection on the power plane to
minimize the crosstalk between OUT1 and OUT2.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
• Connect GND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
step 4 of the Layout Procedure section.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency by 1% or more.
• LX_ and PGND connections to the synchronous rectifiers for current limiting must be made using Kelvin
sense connections to guarantee the current-limit
accuracy. With 8-pin SO MOSFETs, this is best done
______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
all these connections on the top layer with wide, copper-filled areas (2oz copper recommended).
2) Mount the controller IC adjacent to the synchronous
rectifier MOSFETs (NL _), preferably on the back
side in order to keep LX_, PGND_, and DL_ traces
short and wide. The DL_ gate trace must be short
and wide, measuring 50mils to 100mils wide if the
low-side MOSFET is 1in from the controller IC.
3) Group the gate-drive components (BST_ diodes and
capacitors, and VL bypass capacitor) together near
the controller IC.
4) Make the DC-DC controller ground connections as
follows: create a small analog ground plane near the
IC. Connect this plane to GND and use this plane for
the ground connection for the reference (REF), V+
bypass capacitor, compensation components, feedback dividers, OSC resistor, and ILIM_ resistors (if
any). Connect GND and PGND together under the
IC (this is the only connection between GND and
PGND).
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
• Make all pin-strap control input connections (ILIM_,
SYNC, and EN) to analog ground (GND) rather than
power ground (PGND).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (NL _ source, CIN_, and COUT_). Make
Chip Information
TRANSISTOR COUNT: 6688
PROCESS: BiCMOS
______________________________________________________________________________________
19
MAX1858
by routing power to the MOSFETs from outside
using the top copper layer, while connecting PGND
and LX_ underneath the 8-pin SO package.
• When trade-offs in trace lengths must be made,
allow the inductor-charging path to be made longer
than the discharge path. Since the average input
current is lower than the average output current in
step-down converters, this minimizes the power dissipation and voltage drops caused by board resistance. For example, allow some extra distance
between the input capacitors and the high-side
MOSFET rather than to allow distance between the
inductor and the low-side MOSFET or between the
inductor and the output filter capacitor.
• Ensure that the feedback connection to C OUT_ is
short and direct.
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from the sensitive analog areas
(REF, COMP_, ILIM_, and FB_). Use PGND1 and
PGND2 as EMI shields to keep radiated noise away
from the IC, feedback dividers, and analog bypass
capacitors.
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
MAX1858
Typical Operating Circuit
VIN 4.75V TO 23V
V+
VL
BST1
BST2
DH1
DH2
NH2
OUTPUT1 = 1.8V, 10A
OUTPUT2 = 2.5V, 10A
LX1
NL1
DL1
MAX1858
LX2
DL2
NL2
PGND
FB1
COMP1
FB2
COMP2
REF
OSC
GND
CLOCK OUTPUT
CK0
RESET OUTPUT
RST
SYNC
VL
ILIM1
ON
EN
ILIM2
OFF
20
______________________________________________________________________________________
Dual 180° Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1858
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
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