CLARE M-984-02 Special information tone detector Datasheet

M-984-02
Special Information Tone Detector
Features
Description
• Detects single-frequency tones used for error
indication and call progress in telephone systems
• Provides detection windows for:
400/425 Hz (Call Progress)
950 Hz (Special and error indication)
1400 Hz (Special and error indication)
1800 Hz (Special and error indication)
• Separate tri-state outputs for each tone window
• Inexpensive 3.58 MHz crystal time base
• Auxiliary 3.58 MHz clock output
• 14-pin DIP package and 16-pin SOIC package
• Single supply 3 to 5 volt (low power CMOS)
• Wide dynamic range (30 dBm)
The M-984-02 Special Information Tone Detector is a
monolithic integrated circuit designed to provide reliable detection of many common telephone network
status signals. In particular, it detects the signals
known as Special Information Tones (SITs) or error
tones as defined by the CCITT, and single tones often
used as dial tone, audible ringing, and other general
progress indications. The M-984-02 uses CMOS
switched capacitor filters and a crystal time base to
achieve the high stability and accuracy specified. Each
tone detection window has an associated output pin,
which can be placed in a high impedance state for use
with time-share microcomputer bus applications.
Applications
In comparison with the earlier M-984, the M-984-02
has wider acceptance bands for SIT tones to facilitate
reception of tape-loop tones, lower power consumption at 5V operation, 3V operation, superior temperature performance, lower cost, and is available in DIP,
SOIC, and SOIC tape and reel versions.
•
•
•
•
•
•
Automatic dialers
Modems
Telecom test equipment
Telephone traffic measurement,
Service evaluation
Billing equipment
Pin Diagram
Ordering Information
Part #
M-984-02P
M-984-02S
M-984-02T
Description
14-pin plastic DIP
16-pin plastic, SOIC
16-pin SOIC, Tape and Reel
Block Diagram
DS-M984-02-R3
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1
M-984-02
Absolute Maximum Ratings
DC Supply Voltage
Input Voltage on SIGIN
Input Voltage on Any Pin
(except SIGIN)
Storage Temperature Range
Operating Temperature Range
Lead Soldering Temperature
7V
VSS - 6.5V to VDD +0.3V
VSS - 0.3 to VDD + 0.3V
-40°C to +150°C
-40°C to +85°C
260°C for 5 seconds
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability.
Note:
Exceeding these ratings may permanently damage the device.
Specifications
Operating Conditions
Power
VREF
Signal Detection
Signal Rejection
Outputs
Inputs
Parameter
Conditions
Min
Max
Units
VDD
Power supply noise
Current drain (IDD)
VREF
Impedance
Frequency Range
Level: VDD = 5.0V
Level: VDD = 3.0V
Duration
0.1 - 5 kHz
VREF open
fc = 400 Hz
fc = 950, 1400, 1800 Hz
ISINK = -1.0 mA
ISOURCE = 1.0 mA
VO = VDD, VSS
VDD = 5V
VDD = 2.7V
VDD = 5V
VDD = 2.7V
VDD = 5V
VDD = 2.7V
f = 500 Hz
XOUT open
XOUT open
XOUT open
CL = 20 pF, ISINK = -1.0 mA
CL = 20 pF, ISOURCE = 1.0 mA
CL = 20 pF
CL = 50 pF
RL = 100 KΩ
2.7
48% of VDD
3.25
Note 1
-30 (24.5 mV)
-33 (17.4 mV)
85
50
16
Note 1
VDD-0.5
VDD -2.0
VDD - 0.5
12.5
4
2
12.5
12.5
4
-6.5
80
VDD - 0.2
40
20
VDD - 0.5
40
-
5.5
20
15
52% of VDD
8.25
Note 1
0 (775 mV)
-3 (173.5 mV)
15
Note 1
-40 (7.8 mV)
-43 (5.5 mV)
50
0.5
1
0.5
50
20
6
100
25
10
VDD
28
0.2
60
10
0.5
60
250
250
V
mV p-p
mA
V
kΩ
dBm
dBm
ms
ms
ms
dB
dBm
dBm
ms
V
V
µA
V
V
V
µA
µA
µA
µA
µA
µA
V
kΩ
kHz
V
V
%
pF
MΩ
V
V
%
ns
ns
Bridge Time
Signal to Noise Ratio
Frequency Range
Level: VDD = 5.0V
Level: VDD = 3.0V
Duration
Except X358
VOL
VOH
Dn pins only
IOZ
EN pin
VIL
VIH
Pull-up and Pulldown currents
MODE = VSS
/XRANGE +VSS
MODE2 = VDD
PD = VDD
Voltage range
Input impedance
Input Spectrum
External clock
VIL
connected to
VIH
XIN pin
Duty cycle
XIN, XOUT with
Capacitance
crystal ocs. active Internal res.
X358 pin
VOL
VOH
Duty cycle
tEN (High Z to Low Z)
tDE (Low Z to High Z)
SIGIN pin
Clock
Tri-state Operation
Unless otherwise noted, specifications hold over VDD - VSS = 2.8V to 5.5V power supply, and TOL -40°C to +85°C.
Notes:
1. See the Detector Frequency Windows table on page 4 for detection/ rejection frequencies.
2
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Rev. 3
M-984-02
Pin Functions
PIN
FUNCTION
XIN
XOUT
Crystal Connection — 3.58 MHz crystal across these pins will produce the timebase needed for proper operation of the
M-984-02. An external clock signal may be fed to XIN providing the clock signal has a duty cycle of 50 ±10% and comes within
0.2 volts of the supply rails. XOUT remains unconnected when an external clock is used.
X358
A buffered output pin. A 3.58 MHz clock signal is available for use in other circuits as a timebase. Leave open when unused.
ENVLP
The ENVLP pin is a common detection indicator for the four detect pins. Simply put, the ENVLP is a logical “OR” of the active
detect circuits for each of the four windows, though there is a delay provided to permit ENVLP to latch the first active detect pin.
ENVLP is not tri-state controlled.
The power supply pins, VDD being the most positive. Commonly, VDD is at 3-5 volts, white VSS is at ground.
VSS
VDD
SIGIN
Analog signal input. (Internally capacitively coupled.)
VREF
VREF is a bias voltage generated in the chip for use in external analog circuits, such as active filters and AC-coupled buffers.
Leave open when unused.
OE
The tri-state control pin. OE places the DET pins in the active mode when at logic “1”. When at logic “0,” OE causes the DET
outputs to appear as high impedance. Should be tied to logic “1” when the M-984-02 is not used in a time-shared bus
application.
D1800
D1400
D950
D400
Rev. 3
The detect outputs associated with each window. Tri-state control is available through use of the OE pin.
Timing is shown in the Timing Diagram on page 4.
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3
M-984-02
Typical Application
Detector Frequency Windows
Detector
D400
D950
D1400
D1800
Low Reject
363
835
1275
1656
Low Accept
392
885
1328
1722
High Accept
459
1016
1472
1854
High Reject
493
1070
1527
1924
Timing Diagram
Tri-State Timing
4
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Rev. 3
M-984-02
Mechanical Dimensions
Tolerances
Inches
A
A1
b
b2
C
D
E
E1
e
ec
L
Min
.015
.014
.045
.008
.735
.300
.240
Max
.210
.022
.070
.014
.775
.325
.280
.100 BSC
0°
.115
15°
.150
Metric (mm)
Min
Max
5.33
.38
.36
.56
1.1
1.8
.20
.36
18.7
19.7
7.6
8.3
6.1
7.1
2.54 BSC
0°
15°
2.9
4.1
Tolerances
Inches
A
A1
b
D
E
e
H
L
Min
.093
.004
.013
.398
.291
Max
.104
.012
.020
.413
.299
.050 BSC
.394
.016
.419
.050
Metric (mm)
Min
Max
2.35
2.65
.10
.30
.33
.51
10.10
10.50
7.4
7.6
1.27 BSC
10.00
10.65
.40
1.27
Dimensions
mm
(inches)
Rev. 3
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5
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Clare, Inc. makes no representations or warranties with respect to
the accuracy or completeness of the contents of this publication
and reserves the right to make changes to specifications and
product descriptions at any time without notice. Neither circuit
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set forth in Clare’s Standard Terms and Conditions of Sale, Clare,
Inc. assumes no liability whatsoever, and disclaims any express or
implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed,
intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction
of Clare’s product may result in direct physical harm, injury, or
death to a person or severe property or environmental damage.
Clare, Inc. reserves the right to discontinue or make changes to its
products at any time without notice.
Specification: DS-M-984-02-R3
©Copyright 2001, Clare, Inc.
All rights reserved. Printed in USA.
7/17/01
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