SAMSUNG 256MBDDRSDRAM

256Mb DDR SDRAM
Preliminary
DDR SDRAM Specification
Version 0.3
- 1 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Revision History
Version 0 (May, 2000)
- First version for internal review of 256Mb B-die.
Version 0.1(July,2000)
- Added DC target spec values
- Deleted tDAL in AC parameter X
Version 0.2(October,2000)
- Updated DC current spec
Version 0.3(November,2000)
- Changed spec to preliminery from target
- 2 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Contents
Revision History
2
General Information
7
1. Key Features
8
8
8
1.1 Features
1.2 Operating Frequencies
2. Package Pinout & Dimension
2.1 Package Pintout
2.2 Input/Output Function Description
2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
9
9
10
11
12
12
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
3.2.1 Power-Up Sequence
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.3 Precharge
3.2.4 No Operation(NOP) & Device Deselect
3.2.5 Row Active
3.2.6 Read Bank
13
13
14
14
16
17
17
18
18
18
3.2.7 Write Bank
3.3 Essential Functionality for DDR SDRAM
3.3.1 Burst Read Operation
3.3.2 Burst Write Operation
3.3.3 Read Interrupted by a Read
3.3.4 Read Interrupted by a Write & Burst Stop
3.3.5 Read Interrupted by a Precharge
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23
3.3.6 Write Interrupted by a Write
- 3 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.7 Write Interrupted by a Read & DM
3.3.8 Write Interrupted by a Precharge & DM
3.3.9 Burst Stop
3.3.10 DM masking
3.3.11 Read With Auto Precharge
3.3.12 Write With Auto Precharge
3.3.13 Auto Refresh & Self Refresh
3.3.14 Power Down
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29
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32
4. Command Truth Table
5. Functional Truth Table
33
6. Absolute Maximum Rating
37
7. DC Operating Conditions & Specifications
7.1 DC Operating Conditions
7.2 DDR SSDRAM spec Items and Test Conditions
7.3 DDR SDRAM IDD spec Table
37
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38
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
8.2 AC Timming Parameters & Specification
41
41
42
44
9. AC Operating Test Conditions
10. Input/Output Capacitance
44
11. IBIS: I/V Characteristics for Input and Output Buffers
45
45
47
11.1 Normal strength driver
11.2 Half strength driver
12. QFC function
QFC definition
QFC timming on Read Operation
QFC timming on Write operation with tDQSSmax
QFC timming on Write operation with tDQSSmin
QFC timming example for interrupted writes operation
Timing Diagram
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
List of tables
Table 1 : Operating frequency and DLL jitter
Table 2. : Column address configurtion
Table 3 : Input/Output function description
Table 4 : Burst address ordering for burst length
Table 5 : Bank selection for precharge by bank address bits
Table 6 : Operating description when new command asserted while
read with auto precharge is issued
Table 7 : Operating description when new command asserted while
write with auto precharge is issued
Table 8 : Command truth table
Table 9-1 : Functional truth table
Table 9-2 : Functional truth table (contiued)
Table 9-3 : Functional truth table (contiued)
Table 9-4 : Functional truth table (contiued)
Table 10 : Absolute maximum raings
Table 11 : DC operating condtion
Table 12 : DDR SDRAM spec Items and Test Conditions
Table 13 : DDR SDRAM IDD spec Table
Table 14 : AC operating condition
Table 15 : AC timing parameters and specifications
Table 16 : AC operating test conditions
Table 17 : Input/Output capacitance
Table 18 : Pull down and pull up current values for normal strength driver
Table 19 : Pull down and pull up current values for half strength driver
- 5 -
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10
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17
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
List of figures
Figure 1 : 256Mb Package Pinout
Figure 2 : Package dimension
Figure 3 :State digram
Figure 4 : Power up and initialization sequence
Figure 5 : Mode register set
Figure 6 : Mode register set sequence
Figure 7 : Extend mode register set
Figure 8 : Bank activation command cycle timing
Figure 9 : Burst read operation timing
Figure 10 : Burst write operation timing
Figure 11 : Read interrupted by a read timing
Figure 12 : Read interrupted by a write and burst stop timing
Figure 13 : Read interrupted by a precharge timing
Figure 14 : Write interrupted by a write timing
Figure 15 : Write interrupted by a read and DM timing
Figure 16 : Write interrupted by a precharge and DM timing
Figure 17 : Burst stop timing
Figure 18 : DM masking timing
Figure 19 : Read with auto precharge timing
Figure 20 : Write with auto precharge timing
Figure 21 : Auto refresh timing
Figure 22 : Self refresh timing
Figure 23 : Power down entry and exit timing
Figure 24 : Output Load Circuit (SSTL_2)
Figure 25 : I / V characteristics for input/output buffers:
pull-up(above) and pull-down(below) for normal strength driver
Figure 26 : I / V characteristics for input/output buffers:
pull-up(above) and pull-down(below) for half strength driver
Figure 27 : QFC timing on read operation
Figure 28 : QFC timing on write operation with tDQSSmax
Figure 29 : QFC timing on write operation with tDQSSmin
Figure 30 : QFC timing example for interrupted writes operation
- 6 -
6
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12
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14
15
16
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
General Information
Organization
64Mx4
32Mx8
16Mx16
133Mhz w/ CL=2
133Mhz w/ CL=2.5
100Mhz w/ CL=2
K4H560438B-TCA2
K4H560438B-TCB0
K4H560438B-TCA0
K4H560438B-TLA2
K4H560438B-TLB0
K4H560438B-TLA0
K4H560838B-TCA2
K4H560838B-TCB0
K4H560838B-TCA0
K4H560838B-TLA2
K4H560838B-TLB0
K4H560838B-TLA0
K4H561638B-TCA2
K4H561638B-TCB0
K4H561638B-TCA0
K4H561638B-TLA2
K4H561638B-TLB0
K4H561638B-TLA0
1
2
3
4
5
6
7
8
9
10
11
K 4 H XX XX X X X - X X XX
Memory
Speed
DRAM
Temperature & Power
Small Classification
Package
Density and Refresh
Version
Organization
Bank
Interface (VDD & VDDQ)
1. SAMSUNG Memory : K
2. DRAM : 4
3. Small Classification
H : DDR SDRAM
8. Version
M
A
B
C
D
E
4. Density & Refresh
64 : 64M 4K/64ms
28 : 128M 4K/64ms
56 : 256M 8K/64ms
51 : 512M 8K/64ms
1G : 1G 16K/32ms
: 1st Generation
: 2nd Generation
: 3rd Generation
: 4th Generation
: 5th Generation
: 6th Generation
9. Package
T : TSOP2 (400mil x 875mil)
10. Temperature & Power
C : (Commercial, Normal)
L : (Commercial, Low)
5. Organization
04 : x4
08 : x8
16 : x16
32 : x32
11. Speed
A0 : 10ns@CL2
A2 : 7.5ns@CL2
B0 : 7.5ns@CL2.5
6. Bank
3 : 4 Bank
7. Interface (VDD & VDDQ)
8: SSTL-2(2.5V, 2.5V)
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
1. Key Features
1.1 Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
1.2 Operating Frequencies
- A2(DDR266A)
- B0(DDR266B)
- A0(DDR200)
133MHz
100MHz
100MHz
Speed @CL2.5
-
133MHz
-
DLL jitter
±0.75ns
±0.75ns
±0.8ns
Speed @CL2
*CL : Cas Latency
Table 1. Operating frequency and DLL jitter
- 8 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
2. Package Pinout & Dimension
2.1 Package Pinout
16Mb x 16
32Mb x 8
64Mb x 4
VDD
VDD
VDD
1
66
VSS
VSS
VSS
DQ 0
DQ 0
NC
2
65
NC
DQ 7
DQ15
VDDQ
VDDQ
VDDQ
3
64
VSSQ
VSSQ
VSSQ
DQ 1
NC
NC
4
63
NC
NC
DQ14
DQ 2
DQ 1
DQ0
5
62
DQ3
DQ 6
DQ13
VSSQ
VSSQ
VSSQ
6
61
VDDQ
VDDQ
VDDQ
DQ 3
NC
NC
7
60
NC
NC
DQ12
DQ 4
DQ 2
NC
8
59
NC
DQ 5
DQ11
VDDQ
VDDQ
VDDQ
9
58
VSSQ
VSSQ
VSSQ
DQ 5
NC
NC
10
57
NC
NC
DQ10
DQ 6
DQ 3
DQ1
11
56
DQ2
DQ 4
DQ9
VSSQ
VSSQ
VSSQ
12
55
VDDQ
VDDQ
VDDQ
DQ 7
NC
NC
13
54
NC
NC
DQ8
NC
NC
NC
14
53
NC
NC
NC
VDDQ
VDDQ
VDDQ
15
52
VSSQ
VSSQ
VSSQ
LDQS
NC
NC
16
51
DQS
DQS
UDQS
NC
NC
NC
17
50
NC
NC
NC
VDD
VDD
VDD
18
49
VREF
VREF
VREF
QFC/NC QFC/NC
19
48
VSS
VSS
VSS
47
DM
DM
UDM
46
CK
CK
CK
QFC/NC
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
Bank Address
BA0-BA1
Row Address
A0-A12
Auto Precharge
A10
LDM
NC
NC
20
WE
WE
WE
21
CAS
CAS
CAS
22
45
CK
CK
CK
RAS
RAS
RAS
23
44
CKE
CKE
CKE
CS
CS
CS
24
43
NC
NC
NC
NC
NC
NC
25
42
A12
A12
A12
BA0
BA0
BA0
26
41
A11
A11
A11
BA1
BA1
BA1
27
40
A9
A9
A9
AP/A 10
AP/A 10
AP/A10
28
39
A8
A8
A8
A0
A0
A0
29
38
A7
A7
A7
A1
A1
A1
30
37
A6
A6
A6
A2
A2
A2
31
36
A5
A5
A5
A3
A3
A3
32
35
A4
A4
A4
VDD
VDD
VDD
33
34
VSS
VSS
VSS
MS-024FC
FIgure 1. 256Mb package Pinout
Organization
Column Address
64Mx4
A0-A9, A11
32Mx8
A0-A9
16Mx16
A0-A8
DM is internally loaded to match DQ and DQS identically.
Table 2. Column address configuration
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
2.2 Input/Output Function Description
SYMBOL
TYPE
DESCRIPTION
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to
both edges of CK. Internal clock signals are derived from CK/CK.
CKE
Input
Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs,
which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled
during power-down and self refresh modes, providing low standby power. CKE will recognize
an LVCMOS LOW level prior to VREF being stable on power-up.
CS
Input
Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
RAS, CAS, WE
Input
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
LDM,(U)DM
Input
Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on
DQ8-DQ15.
BA0, BA1
Input
Bank Addres Inputs : BA0 and BA1 define to which bank ACTIVE, READ, WRITE or PRECHARGE command is being applied.
A [n : 0]
Input
Address Inputs : Provide the row address for ACTIVE commands, the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
DQ
I/O
Data Input/Output : Data bus
LDQS,(U)DQS
I/O
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15.
QFC
Output
FET Control : Optional. Output during every Read and Write access. Can be used to control
isolation switches on modules.
NC
-
No Connect : No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply : +2.5V ± 0.2V.
VSSQ
Supply
DQ Ground.
VDD
Supply
Power Supply : +2.5V ± 0.2V (device specific).
VSS
Supply
Ground.
VREF
Input
SSTL_2 reference voltage.
Table 3. Input/Output Function Description
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
2.3 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
0.30±0.08
(10×)
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
(10.76)
0.10 MAX
[
0.075 MAX ]
(R
0.2
5
0.65TYP
0.65±0.08
0.05 MIN
(0.71)
(R
0.
15
)
(0.50)
)
(4×
)
1.20MAX
(10×)
)
1.00±0.10
0.210±0.05
0.665±0.05
22.22±0.10
(R
0.1
5
0.125 +0.075
-0.035
(R
0.
25
)
(0.80)
#33
(1.50)
(10×)
0.45~0.75
(1.50)
(10×)
#1
11.76±0.20
(0.80)
#34
10.16±0.10
#66
(0.50)
Units : Millimeters
0.25TYP
0×~8×
Figure 2. Package dimension
- 11 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3. Functional Description
3.1 Simplified State Diagram
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
IDLE
AUTO
REFRESH
CKEL
CKEH
POWER
DOWN
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
BURST STOP
WRITE
READ
WRITEA
READA
READ
WRITEA
WRITE
WRITEA
READ
READA
READA
PRE
WRITEA
READA
PRE
POWER
APPLIED
POWER
ON
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
WRITEA : Write with autoprecharge
READA : Read with autoprecharge
Figure 3. State diagram
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.2 Basic Functionality
3.2.1 Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state(all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock(CK, CK), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low"
to all of the rest address pins, A1~A11 and BA1)
*1 6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to
lock the DLL.
(To issue DLL reset command, provide "High" to A8 and "Low" to BA0)
*2 7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up.
Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
Power up & Initialization Sequence
3
4
5
6
7
8
9
precharge
ALL Banks
tRP
2 Clock min.
EMRS
2 Clock min.
MRS
DLL Reset
precharge
ALL Banks
11
12
13
1st Auto
Refresh
14
15
16
17
tRFC
tRFC
tRP
∼
Command
10
∼
∼ ∼ ∼
2
2nd Auto
Refresh
min.200 Cycle
18
19
2 Clock min.
Mode
Register Set
Any
Command
∼
1
∼
∼ ∼
∼ ∼
0
CK
CK
Figure 4. Power up and initialization sequence
- 13 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make
DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined,
therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode
register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A12 in
the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles
are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. The mode register is divided into various fields depending on functionality. The burst length uses
A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used
for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for
specific codes for various burst lengths, addressing modes and CAS latencies.
BA1
BA0
RFU
0
A12
A11
A10
A9
RFU
A8
A8
A7
DLL
TM
DLL Reset
A6
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
A7
mode
A3
Burst Type
0
No
0
Normal
0
Sequential
1
Yes
1
Test
1
Interleave
Address Bus
Mode Register
Burst Length
CAS Latency
BA0
An ~ A0
0
(Existing)MRS Cycle
1
Extended Funtions(EMRS)
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
A2
A1
A0
Reserve
0
0
Reserve
0
0
2
0
1
(3)
0
Reserve
0
1
1
0
1
1
A6
A5
A4
Latency
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
Latency
Sequential
Interleave
0
Reserve
Reserve
1
2
2
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
(1.5)
1
0
1
Reserve
Reserve
2.5
1
1
0
Reserve
Reserve
Reserve
1
1
1
Reserve
Reserve
Figure 5. Mode Register Set
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address(A2, A1, A0)
2
4
8
Sequential Mode
Interleave Mode
xx0
0, 1
0, 1
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Table 4. Burst address ordering for burst length
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and
upon returing to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon
exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Some vendors might also support
a weak driver strength option, intended for lighter load and/or point-to-point environments. I-V curves for the
normal drive strength and weak drive strength will be included in a future revision of this document.
Mode Register Set
0
1
2
3
4
5
6
7
8
CK
CK
*1
Mode
Register Set
Precharge
All Banks
Command
tCK
tRP*2
Any
Command
2 Clock min.
*1 : MRS can be issued only at all bank precharge state.
*2 : Minimum tRP is required to issue MRS command.
Figure 6. Mode Register Set sequence
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.2.2.2 Extended Mode Register Set(EMRS)
The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver
size. The default value of the extended mode register is not defined, therefore the extened mode register must
be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low
on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the
same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can
be changed using the same command and clock cycle requirements during operation as long as all banks are
in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1
RFU
BA0
BA0 A12
A11
A10
A9
1
A8
A7
A6
A5
A4
A3
A2
A1
A0
QFC D.I.C DLL
RFU : Must be set "0"
Address Bus
Extended Mode Register
Output Driver Impedence Control
A0
0
Normal
0
Enable
1
Weak
1
Disable
DLL Enable
An ~ A0
0
(Existing)MRS Cycle
1
Extended Funtions(EMRS)
QFC control
0
Disable(Default)
1
Enable
Figure 7. Extend Mode Register set
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.2.3 Precharge
The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge
command can be used to precharge each bank respectively or all banks simultaneously. The bank select
addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write
cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge,
an active command to the same bank can be initiated.
Bank Selection for Precharge by Bank address bits
A10/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
Table 5. Bank selection for precharge by Bank address bits
3.2.4 No Operation(NOP) & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore
all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS,
CAS and WE. For both Deselect and NOP the device should finish the current operation when this command is issued.
- 17 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.2.5 Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0,
BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed
the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged
before another Bank Activation command can be applied to the same bank. The minimum time interval
between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay
time(tRRD min).
Bank Activation Command Cycle (CAS Latency = 2)
0
1
Tn
2
Tn+1
Tn+2
CK
CK
Address
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
RAS-CAS delay(tRCD )
Command
Bank A
Activate
NOP
Bank A
Row. Addr.
RAS-RAS delay time( tRRD )
Write A
with Auto
Precharge
Bank B
Activate
NOP
ROW Cycle Time(t RC)
Bank A
Activate
: Don′t care
Figure 8. Bank activation command cycle timing
3.2.6 Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command
is initiated by activating RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as
described in the command truth table. The length of the burst and the CAS latency time will be determined by
the values programmed during the MRS command.
3.2.7 Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in
the command truth table. The length of the burst will be determined by the values programmed during the
MRS command.
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3 Essential Functionality for DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
3.3.1 Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read
command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the
clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for
the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8). The first
output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is
completed.
< Burst Length=4, CAS Latency= 2, 2.5 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
READ A
DQS
NOP
tRPST
tRPRE
CAS Latency=2
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
DQS
CAS Latency=2.5
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
Figure 9. Burst read operation timing
- 19 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.2 Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock(CK). The address inputs determine the starting column address. There is no write latency
relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ
pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the
clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent
falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any
additional data supplied to the DQ pins will be ignored.
< Burst Length=4 >
0
1
*1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
DQS
NOP
WRITEA
NOP
WRITEB
tDQSSmax
*1
tWPRES*1
DQ ′s
Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3
Figure 10. Burst write operation timing
1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown
(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus.
If a previous write was in progress, DQS could be High at this time, depending on tDQSS.
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.3 Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from
the interrupting Read command is satisfied. At this point the data from the interrupting Read command
appears. Read to Read interval is minimum 1 Clock.
< Burst Length=4, CAS Latency=2 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
READ A
READ B
NOP
DQS
CAS Latency=2
DQ ′s
Dout A0 Dout A 1 Dout B0 Dout B1 Dout B 2 Dout B 3
Figure 11. Read interrupted by a read timing
3.3.4 Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tristated one cycle before the beginning the write operation, Burst stop command must be applied at least 2
clock cycles for CL=2 and at least 3 clock cycles for CL=2.5 before the Write command.
< Burst Length=4, CAS Latency=2 >
0
1
2
3
4
5
6
7
8
CK
CK
Command
READ
Burst Stop
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1
Din 0
Din 1
Din 2
Din 3
Figure 12. Read interrupted by a write and burst stop timing.
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read
burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been
issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up
to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.5 Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required
for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS
latency.
< Burst Length=8, CAS Latency=2 >
0
1
2
3
4
5
6
7
NOP
NOP
NOP
NOP
8
CK
CK
1tCK
Command
READ
Precharge
NOP
NOP
NOP
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
Figure 13. Read interrupted by a precharge timing
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same
bank before the Read burst is complete. The following functionality determines when a Precharge command
may be given during a Read burst and when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL
is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS
Precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where
CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated. A new
Bank Activate command may be issued to the same bank after tRP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same
bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the
Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal
precharge occurs at the same time as the earliest possible external Precharge command would initiate a
precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of
clock cycles between a Precharge command and a new Bank Activate command to the same bank equals
tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of
clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands
can only be given on a rising clock edge).
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge
time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be
satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by
the earliest possible Precharge command which does not interrupt the burst.
- 22 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.6 Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst
is interrupted, the remaining addresses are overridden by the new address and data will be written into the
device until the programmed burst length is satisfied.
< Burst Length=4 >
CK
CK
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
1tCK
Command
NOP
WRITE A
WRITE b
DQS
DQ ′s
Din A0
Din A1
Din B0
Din B1
Din B2
Din B3
Figure 14. Write interrupted by a write timing
- 23 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.7 Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance
state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention.
When the read command is registered, any residual data from the burst write cycle must be masked by DM.
The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside.
Data that are presented on the DQ pins before the read command is initiated will actually be written to the
memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
< Burst Length=8, CAS Latency=2 >
0
1
2
3
4
5
6
7
8
NOP
NOP
CK
CK
Command
NOP
WRITE
NOP
NOP
NOP
tDQSSmax
DQS
CAS Latency=2
READ
NOP
tCDLR
tWPRES*5
DQ ′s
Din 0
Din 1
Din 2
Din 3
tDQSSmin
Din 4
Din 5
Din 6
Din 6
Din 7
Din 7
Dout 0 Dout 1 Dout 2 Do
tCDLR
DQS
tWPRES*5
CAS Latency=2
DQ ′s
Din 0
Din 1
Din 2
Din 3
Din 4
Din 5
Dout 0 Dout 1 Dout 2 Do
DM
Figure 15. Write interrupted by a read and DM timing
The following function established how a Read command may interrupt a Write burst and which input data is
not written into the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock
cycles. The case where the Write to Read delay is 1 clock cycle is disallowed
2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words
whcich immediately precede the interrupting Read operation and the input data word which immediately
follows the interrupting Read operation
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip
(i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them
during a read operation.
4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.
5. Refer to "3.3.2 Burst write operation"
- 24 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.8 Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank.
Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge
command. When precharge command is asserted, any residual data from the burst write cycle must be
masked by DM.
< Burst Length=8 >
0
CK
CK
Command
NOP
1
2
WRITE A
NOP
3
NOP
4
5
NOP
NOP
6
Precharge
7
WRITEB
8
NOP
tDQSSmax
DQS
tWR
tWPRES*5
DQ ′s
Dina0
Dina1
Dina2
Dina3
Dina 4
Dina 5
Dina6
Dina1
Dina 2
Dina3
Dina4
Dina5
Dina6
Dina7
Dina7
Dinb0
tDQSSmin
DQS
DQ ′s
tWPRES*5
Dina0
Dinb0
Dinb1
DM
Figure 16. Write interrupted by a precharge and DM timing
Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the
time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR
SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write
operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and
the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with
the address path by switching clock domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the
write recovery parameter must reference only the clock domain that is used to time the internal write operation,
i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for write recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask
input data during the time between the last valid write data and the rising clock edge on which the
Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM.
The minimum time for write recovery is defined by tWR.
- 25 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same
bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the Bank Activate command. During write with
autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to
Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min)
must still be satisfied such that a Write with autoprecharge command has the same timing as a Write
command followed by the earliest possible Precharge command which does not interrupt the burst.
5. Refer to "3.3.2 Burst write operation"
3.3.9 Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of
the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when
terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which
is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation.
< Burst Length=4, CAS Latency= 2, 2.5 >
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
CK
CK
Command
READ A
Burst Stop
NOP
NOP
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1
The burst ends after a delay equal to the CAS latency.
DQS
CAS Latency=2.5
DQ ′s
Dout 0 Dout 1
Figure 17. Burst stop timing
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:
1. The BST command may only be issued on the rising edge of the input clock, CK.
2. BST is only a valid command during Read bursts.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
- 26 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock
cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency
for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2,
2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are
optional).
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
3.3.10 DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read
cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the
corresponding data.(DM to data-mask latency is zero).
DM must be issued at the rising or falling edge of data strobe.
< Burst Length=8 >
CK
CK
Command
0
1
WRITE
NOP
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSS
DQS
DQ ′s
Din 0 Din 1 Din 2
Din 3 Din 4 Din 5 Din 6
Din7
DM
masked by DM=H
Figure 18. DM masking timing
- 27 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.11 Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge
operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the
start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation
has started the bank cannot be reactivated and the new command can not be asserted until the precharge
time(tRP) has been satisfied.
< Burst Length=4, CAS Latency= 2, 2.5>
0
1
2
3
4
5
6
7
8
NOP
NOP
NOP
NOP
NOP
NOP
CK
CK
BANK A
ACTIVE
Command
READ A
Auto Precharge
NOP
tRAS(min.)
DQS
CAS Latency=2
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
tRP
* Bank can be reactivated at the
completion of precharge
DQS
CAS Latency=2.5
DQ ′s
Dout 0 Dout 1 Dout 2 Dout 3
Begin Auto-Precharge
Figure 19. Read with auto precharge timing
When the Read with Auto precharge command is issued, new command can be asserted at 3,4 and 5
respectively as follows,
Asserted
command
For same Bank
For Different Bank
3
4
5
3
4
5
READ
READ +
No AP*1
READ+
No AP
Illegal
Legal
Legal
Legal
READ+AP
READ +
AP
READ +
AP
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
*1
: AP = Auto Precharge
Table 6. Operating description when new command asserted
while read with auto precharge is issued
- 28 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.12 Write with Auto Precharge
If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new
command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
< Burst Length=4 >
0
1
2
3
4
5
6
7
8
CK
CK
BANK A
ACTIVE
Command
NOP
WRITE A
Auto Precharge
NOP
NOP
NOP
Din 0
Din 1 Din 2 Din 3
NOP
NOP
NOP
DQS
DQ ′s
* Bank can be reactivated at
completion of tRP
tWR
tRP
Internal precharge start
Figure 20. Write with auto precharge timing
Burst length = 4
Asserted
command
For same Bank
For Different Bank
3
4
5
6
7
8
3
4
5
6
7
WRITE
WRITE+
No AP*1
WRITE+
No AP
WRITE+
No AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
WRITE+
AP
WRITE+
AP
WRITE+
AP
WRITE+
AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
READ
Illegal
READ+NO
AP+DM *2
READ+NO
AP+DM
READ+
NO AP
READ+
NO AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
READ+AP
Illegal
READ +
AP+DM
READ +
AP+DM
READ +
AP
READ +
AP
Illegal
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Precharge
Illegal
Illegal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
*1
: AP = Auto Precharge
*2
: DM : Refer to " 3.3.7 Write Interrupted by a Read & DM " in page 25.
Table 7. Operating description when new command asserted
while write with auto precharge is issued
- 29 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.13 Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the
internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the auto refresh command and the next activate command or subsequent auto refresh command
must be greater than or equal to the tRFC(min).
∼
Auto
Refresh
PRE
CMD
∼
∼
Command
∼
CK
CK
CKE = High
tRP
tRFC
Figure 21. Auto refresh timing
Self Refresh
∼
Active
∼
Read
∼
CKE
∼
∼
∼
∼
∼
Self
Refresh
∼
∼
Command
∼ ∼
CK
CK
∼
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising
edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in
self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally
disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE
high for longer than tXSR for locking of DLL.
tXSA*1
tXSR*2
Figure 22. Self refresh timing
1. Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after
any bank active command.
2. Exit self refresh to read command
- 30 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.14 Power down
The power down mode is entered when CKE is low and exited when CKE is high. Once the power down
mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce
power consumption. All banks should be in idle state prior to entering the precharge power down mode and
CKE should be set high at least 1tck+tIS prior to row active command . During power down mode, refresh
operations cannot be performed, therefore the device cannot be remained in power down mode longer than
the refresh period(Data retension time) of the device.
Precharge
power
down
Entry
∼
∼
Active
Active
power
down
Entry
Active
power
down
Exit
Read
∼
∼
∼
CKE
∼
∼
Precharge
∼
∼
Command
∼
CK
CK
Figure 23. Power down entry and exit timing
- 31 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
4. Command Truth Table
COMMAND
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
A11,
A9 ~ A0
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
L
H
H
H
H
X
X
X
Auto Refresh
Refresh
Entry
Self
Refresh
H
L
L
H
Bank Active & Row Addr.
H
X
L
L
H
H
V
Read &
Column Address
H
X
L
H
L
H
V
Write &
Column Address
Exit
H
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
H
X
L
H
L
L
H
X
L
H
H
L
H
X
L
L
H
L
H
X
X
X
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
L
DM
H
No operation (NOP) : Not defined
H
H
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
V
V
V
L
X
X
3
3
3
X
V
3
Row Address
L
Column
Address
H
L
Column
Address
H
X
V
L
X
H
X
X
X
L
H
H
H
4
4
4, 6
7
X
5
X
X
X
H
4
X
8
9
9
Table 8. Command truth table
1. OP Code : Operand Code. A 0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA 1 : Bank select addresses.
If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA 0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
- 32 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
5. Functional Truth Table
Current State
CS
RAS
CAS
PRECHARGE
STANDBY
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
Bank Active, Latch RA
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL*4
L
L
L
H
X
Refresh
AUTO-Refresh*5
ACTIVE
STANDBY
READ
WRITE
WE
Address
Command
Action
L
L
L
L
Op-Code, Mode-Add
MRS
Mode Register Set*5
L
H
H
L
X
Burst Stop
NOP
L
H
L
H
BA, CA, A10
READ/READA
Begin Read, Latch CA,
Determine Auto-Precharge
L
H
L
L
BA, CA, A10
WRITE/WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
PRE/PREA
Precharge/Precharge All
Refresh
ILLEGAL
L
L
H
L
BA, A10
L
L
L
H
X
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
Terminate Burst
L
H
L
H
BA, CA, A10
READ/READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L
H
L
L
BA, CA, A10
WRITE/WRITEA
ILLEGAL
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
Terminate Burst, Precharge
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A 10
READ/READA
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine Auto-Precharge*3
L
H
L
L
BA, CA, A 10
Terminate Burst, Latch CA,
WRITE/WRITEA Begin new Write, Determine
Auto-Precharge*3
L
L
H
H
BA, RA
Active
Bank Active/ILLEGAL*2
L
L
H
L
BA, A 10
PRE/PREA
Terminate Burst With DM=High,
Precharge
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
Op-Code, Mode-Add
Table 9-1. Functional truth table
- 33 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Current State
CS
RAS
CAS
WE
READ with
AUTO
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
*6
L
H
L
L
BA, CA, A10
WRITE/WRITEA
ILLEGAL
L
L
H
H
BA, RA
Active
*6
PRE/PREA
*6
Refresh
ILLEGAL
PRECHARGE*6
(READA)
WRITE with
AUTO
RECHARGE*7
(WRITEA)
PRECHARGING
(DURING tRP)
ROW
ACTIVATING
(FROM ROW
ACTIVE TO
tRCD)
WRITE
RECOVERING
(DURING tWR
OR tCDLR)
Address
L
L
H
L
BA, A10
L
L
L
H
X
Command
Action
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
*7
L
H
L
L
BA, CA, A10
WRITE/WRITEA
*7
L
L
H
H
BA, RA
Active
*7
L
L
H
L
BA, A10
PRE/PREA
*7
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
NOP*4(Idle after tRP)
L
L
L
H
X
Refresh
ILLEGAL
Op-Code, Mode-Add
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL*2
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL*2
L
H
L
H
BA, CA, A10
READ
ILLEGAL*2
L
H
L
L
BA, CA, A10
WRITE
WRITE
L
L
H
H
BA, RA
Active
ILLEGAL*2
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL*2
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
MRS
ILLEGAL
Op-Code, Mode-Add
Table 9-2. Functional truth table
- 34 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Current State
CS
RAS
CAS
WE
REFRESHING
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
MODE
REGISTER
SETTING
Address
Command
Action
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
L
H
H
L
X
Burst Stop
ILLEGAL
L
H
L
X
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
H
H
BA, RA
Active
ILLEGAL
L
L
H
L
BA, A10
PRE/PREA
ILLEGAL
L
L
L
H
X
Refresh
ILLEGAL
L
L
L
L
Op-Code, Mode-Add
MRS
ILLEGAL
Table 9-3. Functional truth table
- 35 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Current State
CKE
n-1
CKE
n
CS
SELF-
L
H
H
X
REFRESHING*8
L
H
L
H
L
H
L
H
L
H
L
L
H
L
L
L
POWER
DOWN
L
L
ALL BANKS
IDLE*9
ANY STATE
other than
listed above
RAS
CAS
WE
Add
Action
X
X
X
Exit Self-Refresh
H
H
X
Exit Self-Refresh
H
L
X
ILLEGAL
H
L
X
X
ILLEGAL
L
X
X
X
ILLEGAL
X
X
X
X
X
NOPeration(Maintain Self-Refresh)
H
X
X
X
X
X
Exit Power Down(Idle after tPDEX)
L
X
X
X
X
X
NOPeration(Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function True Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State=Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
ABBREVIATIONS :
H=High Level, L=Low level, X=Don′t Care
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
6. Refer to "Read with Auto Precharge" in page 85 for detailed information.
7. Refer to "Write with Auto Precharge" in page 86 for detailed information.
8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied
before issuing any command other than EXIT.
9. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
ILLEGAL = Device operation and/or data integrity are not guaranteed.
Table 9-4. Functional truth table
- 36 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
6. Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
Table 10. Absolute maximum ratings
7. DC Operating Conditions & Specifications
7.1 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Supply voltage(for device with a nominal VDD of 3.3V)
VDD
3.0
3.6
V
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
Note
I/O Supply voltage
VDDQ
2.3
2.7
V
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
VTT
VREF-0.04
VREF +0.04
V
2
Input logic high voltage
VIH (DC)
VREF+0.15
VDDQ+0.3
V
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN (DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID (DC)
0.3
VDDQ+0.6
V
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current (VOUT = 1.95V)
IOH
-16.8
mA
Output Low Current (VOUT = 0.35V)
IOL
16.8
mA
I/O Termination voltage(system)
Input leakage current
3
Notes 1. V REF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-topeak noise on V REF may not exceed 2% of the DC value
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF , and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
Table 11. DC operating condition
- 37 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
7.2 DDR SDRAM SPEC Items and Test Conditions
Conditions
Symbol
Typical
Worst
Operating current - One bank Active-Precharge;
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
IDD0
-
-
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
-
-
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD2P
-
-
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
-
-
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
IDD2Q
-
-
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD3P
-
-
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
IDD3N
-
-
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
IDD4R
-
-
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
IDD4W
-
-
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
IDD5
-
-
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
IDD6
-
-
Orerating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7
-
-
Typical case: VDD = 2.5V, T = 25’C
Worst case : VDD = 2.7V, T = 10’C
Table 12. DDR SDRAM spec Items and Test Conditions
- 38 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
7.3 DDR SDRAM IDD spec table
64Mx4
Symbol
K4H560438B-TCA2
(DDR266A)
K4H560438B-TCB0
(DDR266B)
K4H560438B-TCA0
(DDR200)
typical
typical
typical
worst
worst
Unit
IDD0
100
110
100
110
90
100
mA
IDD1
150
165
150
165
140
155
mA
IDD2P
25
30
25
30
23
25
mA
IDD2F
45
50
45
50
40
45
mA
IDD2Q
35
40
35
40
30
35
mA
IDD3P
40
45
40
45
33
35
mA
IDD3N
45
50
45
50
40
45
mA
IDD4R
180
200
180
200
145
160
mA
IDD4W
160
180
160
180
130
140
mA
IDD5
215
235
215
235
195
210
mA
IDD6
Normal
3
3
3
3
3
3
mA
Low power
1.5
1.5
1.5
1.5
1.5
1.5
mA
315
360
315
360
295
320
mA
IDD7
Notes
worst
Optional
32Mx8
Symbol
IDD6
K4H560838B-TCA2
(DDR266A)
K4H560838B-TCB0
(DDR266B)
K4H560838B-TCA0
(DDR200)
typical
typical
typical
worst
worst
Unit
IDD0
100
110
100
110
90
100
IDD1
155
175
155
175
145
160
mA
IDD2P
25
30
25
30
23
25
mA
mA
IDD2F
45
50
45
50
40
45
mA
IDD2Q
35
40
35
40
30
35
mA
IDD3P
40
45
40
45
33
35
mA
IDD3N
45
50
45
50
40
45
mA
IDD4R
190
215
190
215
155
175
mA
IDD4W
170
190
170
190
135
150
mA
IDD5
215
235
215
235
195
210
mA
3
3
3
3
3
3
mA
Normal
Low power
IDD7
1.5
1.5
1.5
1.5
1.5
1.5
mA
335
385
335
385
310
345
mA
- 39 -
Notes
worst
Optional
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
16Mx16
Symbol
IDD6
K4H561638B-TCA2
(DDR266A)
K4H561638B-TCB0
(DDR266B)
K4H561638B-TCA0
(DDR200)
typical
typical
typical
worst
worst
Unit
IDD0
100
110
100
110
90
100
IDD1
165
185
165
185
155
175
mA
IDD2P
25
30
25
30
23
25
mA
IDD2F
45
50
45
50
40
45
mA
mA
IDD2Q
35
40
35
40
30
35
mA
IDD3P
40
45
40
45
33
35
mA
IDD3N
50
55
50
55
40
45
mA
IDD4R
220
250
220
250
185
210
mA
IDD4W
190
215
190
215
160
180
mA
IDD5
215
235
215
235
195
210
mA
Normal
3
3
3
3
3
3
mA
Low power
1.5
1.5
1.5
1.5
1.5
1.5
mA
385
440
385
440
345
385
mA
IDD7
Notes
worst
Optional
Table 13. DDR SDRAM IDD spec Table
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- PC200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- PC266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- PC266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
- 40 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
IDD7 : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- PC200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- PC266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
- PC266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
0.62
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
Max
VREF + 0.31
Unit
Note
V
1
VREF - 0.31
V
2
VDDQ+0.6
V
3
0.5*VDDQ+0.2
V
4
Note 1. Vih(max) = 4.2V. The overshoot voltage duration is ≤ 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is ≤ 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Table 14. AC operating conditions
- 41 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
8.2 AC Timming Parameters & Specifications
Parameter
Symbol
K4H5604/08/1638B K4H5604/08/1638B K4H5604/08/1638B
-TCA2 (DDR266A) -TCB0 (DDR266B) -TCA0 (DDR200) Unit Note
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
65
65
70
Refresh row cycle time
tRFC
75
75
80
Row active time
tRAS
45
RAS to CAS delay
tRCD
20
20
20
ns
Row precharge time
tRP
20
20
20
ns
Row active to Row active delay
tRRD
15
15
15
ns
Write recovery time
tWR
2
2
2
tCK
Last data in to Read command
tCDLR
1
1
1
tCK
Col. address to Col. address delay
tCCD
Clock cycle time
tCK
CL=2.0
12K
1
7.5
CL=2.5
45
12K
1
48
ns
ns
12K
1
15
10
15
15
7.5
15
10
ns
tCK
15
ns
15
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Output data access time from CK/CK
tAC
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Data strobe edge to ouput data edge
tDQSQ
-
+0.5
-
+0.5
-
+0.6
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
Data out high impedence time from CK/CK
tHZQ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
DQS-in hold time
tWPREH
0.25
DQS-in high level width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS-in low level width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time
tIS
0.9
0.9
1.1
ns
Address and Control Input hold time
tIH
0.9
0.9
1.1
ns
Mode register set cycle time
tMRD
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.5
0.5
0.6
ns
DQ & DM hold time to DQS
tDH
0.5
0.5
0.6
ns
DQ & DM input pulse width
tDIPW
1.75
1.75
2
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
95
116
ns
- 42 -
0
0
0.25
ns
0.25
2
3
tCK
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Parameter
Preliminary
Symbol
K4H5604/08/1638B
-TCA2 (DDR266A)
Min
Max
K4H5604/08/1638B K4H5604/08/1638B
-TCB0 (DDR266B)
-TCA0 (DDR200)
Min
Max
Min
Unit
Note
7
Max
Exit self refresh to bank active command
tXSA
75
75
80
ns
Exit self refresh to read command
tXSR
200
200
200
Cycle
15.6
15.6
15.6
us
1
7.8
7.8
7.8
us
1
Refresh interval time
64Mb, 128Mb
256Mb
tREF
Output DQS valid window
tQH
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-1.0ns
-
ns
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
DQS write postamble time
tWPST
Auto precharge write recovery + Precharge time
tDAL
35
QFC setup to first DQS edge on reads
tQCS
0.9
QFC hold after last DQS edge on reads
tQCH
0.4
Write command to QFC delay on write
tQCSW
Write burst end to QFC delay on write
tQCHW
Write burst end to QFC delay on write interrupted
tQCHWI
by Precharge
0.25
0.25
0.25
35
1.1
0.9
0.6
0.4
4.0
tCK
35
1.1
0.9
0.6
0.4
4.0
4
ns
1.1
tCK
0.6
tCK
4.0
ns
1.25ns
0.5tCK
1.25ns
0.5tCK
1.25ns
0.5tCK
5
-
1.5tCK
-
1.5tCK
-
1.5tCK
6
.
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC high. And the value of
tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC
high.
6. the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC high.
7. A write command can be applied with tRCD satisfied after this command.
Table 15. AC timing parameters and specifications
- 43 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
9. AC Operating Test Conditions
(VDD=2.5/3.3V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V/ns
VREF+0.31/VREF-0.31
V
VREF
V
Vtt
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Note
See Load Circuit
Table 16. AC operating test conditions
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
CLOAD =30pF
VREF
=0.5*VDDQ
Figure 24. Output Load Circuit (SSTL_2)
10. Input/Output Capacitance
(VDD=2.5, VDDQ=2.5V, TA= 25°C , f=1MHz)
Parameter
Symbol
Min
Max
Delta Cap(max)
Unit
Input capacitance
(A0 ~ A 11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
2
3.0
0.5
pF
Input capacitance( CK, CK )
CIN2
2
3.0
0.25
pF
Data & DQS input/output capacitance
COUT
4.0
5.0
Input capacitance(DM)
CIN3
4.0
5.0
0.5
pF
pF
Table 17. Input/output capacitance
- 44 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
11. IBIS: I/V Characteristics for Input and Output Buffers
11.1 Normal strength driver
1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.
2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines the of the V-I curve of Figure a.
Maximum
160
140
Iout(mA)
120
Typical High
100
80
60
Typical Low
40
Minimum
20
0
0.0
0.5
1.0
1.5
2.0
2.5
Vout(V)
3. The nominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b.
4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figrue b.
0.0
0.5
1.0
1.5
2.0
2.5
0
Minumum
-20
Iout(mA)
-40
Typical Low
-60
-80
-100
-120
-140
-160
Typical High
-180
-200
-220
Maximum
Vout(V)
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source
voltage from 0 to VDDQ/2
6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages
from 0 to VDDQ/2
Figure 25. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
- 45 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Pulldown Current (mA)
Voltage
(V)
Typical
Typical
Low
High
0.1
6.0
6.8
0.2
12.2
0.3
18.1
0.4
pullup Current (mA)
Typical
Typical
Low
High
9.6
-6.1
-7.6
9.2
18.2
-12.2
13.8
26.0
-18.1
18.4
33.9
33.0
23.0
39.1
27.7
39.4
44.2
0.8
43.7
0.9
47.5
1.0
1.1
Minimum
Maximum
Minimum
Maximum
4.6
-4.6
-10.0
13.5
20.1
-14.5
-9.2
-20.0
-21.2
-13.8
24.1
26.6
-29.8
-24.0
-27.7
-18.4
-38.8
0.5
29.8
0.6
34.6
41.8
-29.8
-34.1
-23.0
-46.8
49.4
-34.3
-40.5
-27.7
0.7
-54.4
32.2
56.8
-38.1
-46.9
-32.2
-61.8
49.8
36.8
63.2
-41.1
-53.1
-36.0
-69.5
55.2
39.6
69.9
-41.8
-59.4
-38.2
-77.3
51.3
60.3
42.6
76.3
-46.0
-65.5
-38.7
-85.2
54.1
65.2
44.8
82.5
-47.8
-71.6
-39.0
-93.0
1.2
56.2
69.9
46.2
88.3
-49.2
-77.6
-39.2
-100.6
1.3
57.9
74.2
47.1
93.8
-50.0
-83.6
-39.4
-108.1
1.4
59.3
78.4
47.4
99.1
-50.5
-89.7
-39.6
-115.5
1.5
60.1
82.3
47.7
103.8
-50.7
-95.5
-39.9
-123.0
1.6
60.5
85.9
48.0
108.4
-51.0
-101.3
-40.1
-130.4
1.7
61.0
89.1
48.4
112.1
-51.1
-107.1
-40.2
-136.7
1.8
61.5
92.2
48.9
115.9
-51.3
-112.4
-40.3
-144.2
1.9
62.0
95.3
49.1
119.6
-51.5
-118.7
-40.4
-150.5
2.0
62.5
97.2
49.4
123.3
-51.6
-124.0
-40.5
-156.9
2.1
62.9
99.1
49.6
126.5
-51.8
-129.3
-40.6
-163.2
2.2
63.3
100.9
49.8
129.5
-52.0
-134.6
-40.7
-169.6
2.3
63.8
101.9
49.9
132.4
-52.2
-139.9
-40.8
-176.0
2.4
64.1
102.8
50.0
135.0
-52.3
-145.2
-40.9
-181.3
2.5
64.6
103.8
50.2
137.3
-52.5
-150.5
-41.0
-187.6
2.6
64.8
104.6
50.4
139.2
-52.7
-155.3
-41.1
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
Table 18. Pull down and pull up current values for normal strength driver
Temperature (Tambient)
Typical
Minimum
Maximum
25°C
70°C
0°C
Vdd/Vddq
Typical
Minimum
Maximum
2.5V
2.3V
2.7V
The above characteristics are specified under best, worst and normal process variation/conditions
- 46 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
11.2 Half strength driver
1. The nominal pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a.
2. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines the of the V-I curve of Figure a.
90
Maximum
80
70
Typical High
50
Iout(mA)
Iout(mA)
60
40
Typical Low
Minimum
30
20
10
0
0.0
1.0
2.0
Vout(V)
3. Thenominal pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b.
4. The Full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figrue b.
0.0
0.5
1.0
1.5
2.0
2.5
0
-10
Iout(mA)
-20
Minumum
Typical Low
-30
-40
-50
-60
Typical High
-70
-80
Maximum
-90
Vout(V)
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source
voltage from 0 to VDDQ/2
6. The Full variation in the ratio of the nominal pullup to pulldown current should be unity ±10%, for device drain to source voltages
from 0 to VDDQ/2
Figure 26. I/V characteristics for input/output buffers:Pull up(above) and pull down(below)
- 47 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Pulldown Current (mA)
Voltage
(V)
Typical
Typical
Low
High
0.1
3.4
pullup Current (mA)
Minimum
Maximum
3.8
2.6
5.0
Typical
Typical
Low
High
-3.5
Minimum
Maximum
-4.3
-2.6
-5.0
0.2
6.9
7.6
5.2
9.9
-6.9
-8.2
-5.2
-9.9
0.3
10.3
11.4
7.8
14.6
-10.3
-12.0
-7.8
-14.6
0.4
13.6
15.1
10.4
19.2
-13.6
-15.7
-10.4
-19.2
0.5
16.9
18.7
13.0
23.6
-16.9
-19.3
-13.0
-23.6
0.6
19.6
22.1
15.7
28.0
-19.4
-22.9
-15.7
-28.0
0.7
22.3
25.0
18.2
32.2
-21.5
-26.5
-18.2
-32.2
0.8
24.7
28.2
20.8
35.8
-23.3
-30.1
-20.4
-35.8
0.9
26.9
31.3
22.4
39.5
-24.8
-33.6
-21.6
-39.5
1.0
29.0
34.1
24.1
43.2
-26.0
-37.1
-21.9
-43.2
1.1
30.6
36.9
25.4
46.7
-27.1
-40.3
-22.1
-46.7
1.2
31.8
39.5
26.2
50.0
-27.8
-43.1
-22.2
-50.0
1.3
32.8
42.0
26.6
53.1
-28.3
-45.8
-22.3
-53.1
1.4
33.5
44.4
26.8
56.1
-28.6
-48.4
-22.4
-56.1
1.5
34.0
46.6
27.0
58.7
-28.7
-50.7
-22.6
-58.7
1.6
34.3
48.6
27.2
61.4
-28.9
-52.9
-22.7
-61.4
1.7
34.5
50.5
27.4
63.5
-28.9
-55.0
-22.7
-63.5
1.8
34.8
52.2
27.7
65.6
-29.0
-56.8
-22.8
-65.6
1.9
35.1
53.9
27.8
67.7
-29.2
-58.7
-22.9
-67.7
2.0
35.4
55.0
28.0
69.8
-29.2
-60.0
-22.9
-69.8
2.1
35.6
56.1
28.1
71.6
-29.3
-61.2
-23.0
-71.6
2.2
35.8
57.1
28.2
73.3
-29.5
-62.4
-23.0
-73.3
2.3
36.1
57.7
28.3
74.9
-29.5
-63.1
-23.1
-74.9
2.4
36.3
58.2
28.3
76.4
-29.6
-63.8
-23.2
-76.4
2.5
36.5
58.7
28.4
77.7
-29.7
-64.4
-23.2
-77.7
2.6
36.7
59.2
28.5
78.8
-29.8
-65.1
-23.3
-78.8
2.7
36.8
59.6
28.6
79.7
-29.9
-65.8
-23.3
-79.7
Table 19. Pull down and pull up current values for half strength driver
Temperature (Tambient)
Typical
Minimum
Maximum
25°C
70°C
0°C
Vdd/Vddq
Typical
Minimum
Maximum
2.5V
2.3V
2.7V
The above characteristics are specified under best, worst and normal process variation/conditions
- 48 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
12. QFC function
QFC definition
when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later
there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is also
driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe
transition is received. Whenever the device is in standby, the signal is HI-Z. DQS is intended to enable an
external data switch. QFC can be enabled or disabled through EMRS control.
QFC timing on Read operation
QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of
DQS postamble
CL = 2, BL = 2
0
1
2
3
4
5
6
7
8
CK
CK
Command
Read
DQS
DQ’S
QFC
Dout 0 Dout 1
Hi-Z
tQCS
tQCH
Figure 27. QFC timing on read operation
- 49 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
QFC timing on Write operation
QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon
as possible after the last DQS-in low going edge.
0
1
2
3
4
5
6
7
8
BL = 2
CK
CK
Command
Write
DQS@tDQSSmax
DQ’S@tDQSSmax
Dout 0 Dout 1
Hi-Z
QFC
*2
tQCHW max.
*1tQCHW min.
tQCSW
Figure 28. : QFC timing on write operation with tDQSSmax
CK
CK
0
1
2
3
4
5
6
7
8
BL = 2
Command
Write
DQS@tDQSSmin
DQ’S@tDQSSmin
QFC
Dout 0 Dout 1
Hi-Z
tQCSW
*1
tQCHW min.
*2
tQCHW max.
Figure 29. : QFC timing on write operation with tDQSSmin
1. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC tri-state.
2. The value of tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC tri-state.
- 50 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
QFC timing example for interrupted Writes operation
CK
CK
0
1
2
3
4
5
6
7
8
BL = 8
Command
Write
Precharge
DQS
DQ’S
QFC
Dout 0 Dout 1 Dout 2 Dout 3
Hi-Z
tQCHWI max
tQCSW
Figure 30. : QFC timing example for Interrupted writes operation
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REV. 0.3 November 2. 2000