Cypress CY7C1441AV25-133BZI 36-mbit (1m x 36/2m x 18/512k x 72) flow-through sram Datasheet

CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
Functional Description[1]
Features
• Supports 133-MHz bus operations
• 1M x 36/2M x 18/512K x 72 common I/O
• 3.3V core power supply
• 2.5V or 3.3V I/O power supply
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• CY7C1441AV33, CY7C1443AV33 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1447AV33 available in lead-free and non-lead-free
209-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 are
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bit
on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BWx, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst
sequence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated with the Processor Address Strobe
(ADSP) or the cache Controller Address Strobe (ADSC)
inputs. Address advancement is controlled by the Address
Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
8.5
ns
Maximum Operating Current
310
290
mA
Maximum CMOS Standby Current
120
120
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05357 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 23, 2006
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
1
Logic Block Diagram – CY7C1441AV33 (1M x 36)
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADV
CLK
ADSC
ADSP
DQD, DQPD
DQD, DQPD
BWD
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQC, DQPC
DQC, DQPC
BWC
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQB, DQPB
BWB
DQB, DQPB
BYTE
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQPC
DQPD
WRITE REGISTER
DQA, DQPA
BWA
BWE
DQA, DQPA
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
ZZ
SLEEP
CONTROL
2
Logic Block Diagram – CY7C1443AV33 (2Mx 18)
A0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BWB
DQB,DQPB
WRITE REGISTER
BWA
DQA,DQPA
WRITE REGISTER
DQB,DQPB
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQPA
DQPB
DQA,DQPA
WRITE DRIVER
BWE
GW
CE1
CE2
CE3
ENABLE
REGISTER
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05357 Rev. *F
Page 2 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Logic Block Diagram – CY7C1447AV33 (512K x 72)
ADDRESS
REGISTER
A0, A1,A
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BWH
DQH, DQPH
WRITE DRIVER
DQH, DQPH
WRITE DRIVER
BWG
DQF, DQPF
WRITE DRIVER
DQG, DQPG
WRITE DRIVER
BWF
DQF, DQPF
WRITE DRIVER
DQF, DQPF
WRITE DRIVER
BWE
DQE, DQPE
WRITE DRIVER
DQ
E, DQP
BYTE
“a”E
WRITE DRIVER
BWD
DQD, DQPD
WRITE DRIVER
DQD, DQPD
WRITE DRIVER
BWC
DQC, DQPC
WRITE DRIVER
DQC, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQB, DQPB
WRITE DRIVER
DQB, DQPB
WRITE DRIVER
OUTPUT
BUFFERS
E
DQA, DQPA
WRITE DRIVER
DQA, DQPA
WRITE DRIVER
ENABLE
REGISTER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQPA
DQPB
DQPC
DQPD
DQPE
DQPF
DQPG
DQPH
SLEEP
CONTROL
Document #: 38-05357 Rev. *F
Page 3 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Pin Configurations
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1443AV33
(2M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05357 Rev. *F
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
CY7C1441AV33
(1Mx 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
A
VSS
VDD
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-pin TQFP Pinout
Page 4 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1441AV33 (1M x 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
1
A
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
DQC
NC
DQD
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
R
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
9
10
11
CY7C1443AV33 (2M x 18)
1
2
3
4
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWB
NC/144M
A
CE2
NC
NC
NC
NC
DQB
VDDQ
VDDQ
VSS
VDD
NC
DQB
VDDQ
NC
DQB
NC
NC
DQB
DQB
NC
NC
DQB
R
6
7
8
NC
CE3
BWE
ADSC
ADV
A
BWA
CLK
GW
OE
ADSP
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
NC
DQPA
DQA
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
VDDQ
VDD
VSS
VSS
VSS
VDD
DQA
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document #: 38-05357 Rev. *F
5
A
NC/576M
Page 5 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1447AV33 (512K × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQG
DQG
A
CE2
ADSP
ADSC
ADV
CE3
A
DQB
DQB
B
DQG
DQG
BWSC
BWSG
NC288M
A
BWSB
BWSF
DQB
DQB
C
DQG
DQG
BWSH
BWSD NC/144M CE1
NC/576M
BWSE
BWSA
DQB
DQB
D
DQG
DQG
VSS
NC
NC/1G
OE
NC
VSS
DQB
DQB
E
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
F
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
G
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
H
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
J
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
DQPH VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQD
DQD
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
V
DQD
DQD
W
DQD
DQD
Document #: 38-05357 Rev. *F
VSS
BW
GW
DQPA
DQPE
A
A
A
A
A
A
DQE
DQE
A
A
A
A1
A
A
A
DQE
DQE
TMS
TDI
A
A0
A
TCK
DQE
DQE
NC/72M
TDO
Page 6 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Pin Definitions
Name
I/O
Description
A0, A1, A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,
and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB
BWC, BWD,
BWE, BWF,
BWG, BWH
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless
of the values on BWX and BWE).
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is
ignored if CE1 is HIGH. CE1 is sampled only when a new external address is
loaded.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled
only when a new external address is loaded.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. CE3 is
assumed active throughout this document for BGA. CE3 is sampled only when
a new external address is loaded.
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the first clock of a read cycle when emerging from a deselected state.
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK,
active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A[1:0] are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK,
active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A[1:0] are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
ZZ
InputAsynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
DQs
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Document #: 38-05357 Rev. *F
Page 7 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Pin Definitions (continued)
Name
I/O
Description
DQPX
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical
to DQs. During write sequences, DQPx is controlled by BW[A:H] correspondingly.
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation. Mode Pin has an internal
pull-up.
VDD
VDDQ
Power Supply
Power supply inputs to the core of the device.
I/O Power Supply
Power supply for the I/O circuitry.
Ground
Ground for the core of the device.
VSS
VSSQ
I/O Ground
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages.
TDI
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin can be left floating or connected to
VDD through a pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin can be disconnected or connected
to VDD. This pin is not available on TQFP packages.
TCK
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized,
this pin must be connected to VSS. This pin is not available on TQFP
packages.
NC
-
No Connects. Not internally connected to the die. 72M, 144M and 288M are
address expansion pins are not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M
NC/1G
-
No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.
Document #: 38-05357 Rev. *F
Ground for the I/O circuitry.
Page 8 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t CDV) is 6.5 ns (133-MHz device).
The
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
supports secondary cache in systems utilizing either a linear
or interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated
with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active (see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise, the appropriate data will be latched and
written into the device. Byte writes are allowed. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
Document #: 38-05357 Rev. *F
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQS will be written
into the specified address location. Byte writes are allowed. All
I/Os are tri-stated when a write is detected, even a byte write.
Since this is a common I/O device, the asynchronous OE input
signal must be deasserted and the I/Os must be tri-stated prior
to the presentation of data to DQs. As a safety precaution, the
data lines are tri-stated once a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
provides an on-chip two-bit wraparound burst counter inside
the SRAM. The burst counter is fed by A[1:0], and can follow
either a linear or interleaved burst order. The burst order is
determined by the state of the MODE input. A LOW on MODE
will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst
sequence.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Page 9 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Test Conditions
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Min.
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Max.
Unit
100
2tCYC
mA
ns
ns
ns
ns
2tCYC
2tCYC
0
Truth Table[2, 3, 4, 5, 6]
Cycle Description
Deselected Cycle, Power-down
ADDRESS
Used
CE1 CE2 CE3 ZZ ADSP ADSC
None
H
X
X
L
X
L
ADV WRITE OE CLK
DQ
X
X
X
L-H
Tri-State
Deselected Cycle, Power-down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselected Cycle, Power-down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselected Cycle, Power-down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselected Cycle, Power-down
None
X
X
X
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode, Power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
External
External
External
External
External
Next
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
H
X
X
X
L
L
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
L
L
L
H
H
H
X
X
X
X
X
L
L
L
X
X
L
H
H
H
H
H
L
H
X
L
H
L
H
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05357 Rev. *F
Page 10 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Partial Truth Table for Read/Write[2, 7]
Function (CY7C1441AV33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A (DQA, DQPA)
H
L
H
H
H
L
Write Byte B(DQB, DQPB)
H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
L
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
L
H
L
H
L
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC,
DQPB, DQPA)
H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
H
H
H
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD,
DQPC, DQPA)
H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD,
DQPB, DQPA)
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write[2]
GW
BWE
BWB
BWA
Read
Function (CY7C1443AV33)
H
H
X
X
Read
H
L
H
H
Write Byte A - (DQA and DQPA)
H
L
H
L
Write Byte B - (DQB and DQPB)
H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Truth Table for Read/Write[2, 8]
GW
BWE
BWX
Read
Function (CY7C1447AV33)
H
H
X
Read
H
L
All BW = H
Write Byte x – (DQx and DQPx)
H
L
L
Write All Bytes
H
L
All BW = L
Write All Bytes
L
X
X
Notes:
7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
8. BWx represents any byte write signal BW[A..H].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can
be enabled at the same time for any given write.
Document #: 38-05357 Rev. *F
Page 11 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Data-In (TDI)
The
CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
TAP Controller Block Diagram
0
TAP Controller State Diagram
1
Bypass Register
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
Selection
Circuitry
TDO
Identification Register
CAPTURE-IR
x . . . . . 2 1 0
Boundary Scan Register
SHIFT-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
0
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-IR
1
TCK
TMS
0
PAUSE-DR
TAP CONTROLLER
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
TDI
0
1
CAPTURE-DR
0
0
1
Selection
Circuitry
0
UPDATE-IR
1
0
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05357 Rev. *F
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Page 12 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
IDCODE
EXTEST
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
EXTEST OUTPUT BUS TRI-STATE
BYPASS
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
Document #: 38-05357 Rev. *F
Page 13 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes:
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05357 Rev. *F
Page 14 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ............................................... .VSS to 3.3V
Input pulse levels................................................. VSS to 2.5V
Input rise and fall times ................................................... 1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels......................................... 1.25V
Output reference levels...................................................1.5V
Output reference levels ................................................ 1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11]
Parameter
Description
Description
Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage IOH = –4.0 mA
VDDQ = 3.3V
2.4
V
IOH = –1.0 mA
VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
VOL1
Output LOW Voltage
VOL2
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
V
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VDDQ = 2.5V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
VDDQ = 3.3V
GND < VIN < VDDQ
Note:
11. All voltages referenced to VSS (GND).
Document #: 38-05357 Rev. *F
Page 15 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Identification Register Definitions
CY7C1441AV33 CY7C1443AV33 CY7C1447AV33
(1M x 36)
(2M x 18)
(512K x 72)
Instruction Field
Revision Number (31:29)
Description
000
000
000
Device Depth (28:24)
01011
01011
01011
Architecture/Memory
Type(23:18)[12]
000001
000001
000001
Defines memory type and architecture
Defines width and density
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
Describes the version number.
Reserved for Internal Use
100111
010111
110111
00000110100
00000110100
00000110100
1
1
1
ID Register Presence Indicator (0)
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x18)
3
3
3
Instruction
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order (165-ball FBGA package)
89
89
-
Boundary Scan Order (209-ball FBGA package)
-
-
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05357 Rev. *F
Page 16 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
165-ball FBGA Boundary Scan Order[13,14]
CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18)
Bit #
Ball ID
Bit #
Ball ID
1
26
E11
N6
2
27
D11
N7
3
N10
28
G10
4
P11
29
F10
5
P8
30
E10
6
R8
31
D10
7
R9
32
C11
8
P9
33
A11
9
P10
34
B11
10
R10
35
A10
11
R11
36
B10
12
H11
37
A9
13
N11
38
B9
14
M11
39
C10
15
L11
40
A8
16
K11
41
B8
17
J11
42
A7
18
M10
43
B7
19
L10
44
B6
20
K10
45
A6
21
J10
46
B5
22
H9
47
A5
23
H10
48
A4
24
G11
49
B4
25
F11
50
B3
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H3
J1
K1
L1
M1
J2
K2
L2
M2
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
Internal
Notes:
13. Balls which are NC (No Connect) are preset LOW.
14. Bit# 89 is preset HIGH.
Document #: 38-05357 Rev. *F
Page 17 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
209-ball FBGA Boundary Scan Order [13,15]
CY7C1447AV33 (512K x 72)
Bit #
Ball ID
Bit #
Ball ID
Bit #
1
W6
36
F6
71
Ball ID
Bit #
Ball ID
K3
72
H6
C6
106
2
V6
U6
37
K8
3
38
K9
107
K4
73
B6
108
K6
4
W7
39
5
V7
40
K10
74
A6
109
K2
J11
75
A5
110
L2
6
U7
41
J10
76
B5
111
L1
7
T7
42
H11
77
C5
112
M2
8
V8
43
H10
78
D5
113
M1
9
U8
44
G11
79
D4
114
N2
10
T8
45
G10
80
C4
115
N1
11
V9
46
F11
81
A4
116
P2
12
U9
47
F10
82
B4
117
P1
13
P6
48
E10
83
C3
118
R2
14
W11
49
E11
84
B3
119
R1
15
W10
50
D11
85
A3
120
T2
16
V11
51
D10
86
A2
121
T1
17
V10
52
C11
87
A1
122
U2
18
U11
53
C10
88
B2
123
U1
19
U10
54
B11
89
B1
124
V2
20
T11
55
B10
90
C2
125
V1
21
T10
56
A11
91
C1
126
W2
22
R11
57
A10
92
D2
127
W1
23
R10
58
C9
93
D1
128
T6
24
P11
59
B9
94
E1
129
U3
25
P10
60
A9
95
E2
130
V3
26
N11
61
D7
96
F2
131
T4
27
N10
62
C8
97
F1
132
T5
28
M11
63
B8
98
G1
133
U4
29
M10
64
A8
99
G2
134
V4
30
L11
65
D8
100
H2
135
5W
31
L10
66
C7
101
H1
136
5V
32
K11
67
B7
102
J2
137
5U
33
M6
68
A7
103
J1
138
Internal
34
L6
69
D6
104
K1
35
J6
70
G6
105
N6
Note:
15. Bit# 138 is preset HIGH.
Document #: 38-05357 Rev. *F
Page 18 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial
Industrial
Ambient
Temperature
VDD
VDDQ
0°C to +70°C
3.3V –5%/+10%
2.5V –5%
to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range[16, 17]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[16]
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
for 3.3V I/O
3.135
VDD
V
for 2.5V I/O
2.375
2.625
2.4
V
for 2.5V I/O, IOH = –1.0 mA
2.0
V
for 3.3V I/O, IOL = 8.0 mA
0.4
for 2.5V I/O, IOL = 1.0 mA
Voltage[16]
VIL
Input LOW
IX
Input Leakage Current
except ZZ and MODE
V
0.4
V
for 3.3V I/O
2.0
VDD + 0.3V
V
for 2.5V I/O
1.7
VDD + 0.3V
V
for 3.3V I/O
–0.3
0.8
V
for 2.5V I/O
–0.3
0.7
V
–5
5
µA
5
µA
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
µA
–30
Input = VDD
Input Current of ZZ
V
for 3.3V I/O, IOH = –4.0 mA
µA
–5
Input = VSS
30
Input = VDD
µA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
310
mA
10-ns cycle, 100 MHz
290
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
All Speeds
180
mA
ISB2
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = 0, inputs static
All speeds
120
mA
ISB3
Automatic CE
Max. VDD, Device Deselected,
Power-down
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
Current—CMOS Inputs f = fMAX, inputs switching
All Speeds
180
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
All Speeds
135
mA
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
–5
Notes:
16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD
Document #: 38-05357 Rev. *F
Page 19 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Capacitance[18]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 2.5V
100 TQFP
Max.
165 FBGA 209 FBGA
Max.
Max.
Unit
6.5
7
5
pF
3
7
5
pF
5.5
6
7
pF
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
Thermal Resistance[18]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
90%
10%
90%
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
10%
R = 1538Ω
VT = 1.25V
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05357 Rev. *F
Page 20 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Switching Characteristics Over the Operating Range[23, 24]
–133
Parameter
tPOWER
Description
[19]
VDD (Typical) to the first Access
Min.
–100
Max.
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
3.0
ns
tCL
Clock LOW
2.5
3.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[20, 21, 22]
6.5
2.5
2.5
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z[20, 21, 22]
3.8
tOEV
OE LOW to Output Valid
3.0
tOELZ
tOEHZ
OE LOW to Output
Low-Z[20, 21, 22]
OE HIGH to Output
High-Z[20, 21, 22]
8.5
2.5
ns
2.5
0
0
ns
4.5
ns
3.8
ns
0
3.0
ns
ns
4.0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.5
1.5
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
1.5
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.5
1.5
ns
tWES
GW, BWE, BWX Set-up Before CLK Rise
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-up
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.5
0.5
ns
Hold Times
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes:
19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation
can be initiated.
20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
23. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05357 Rev. *F
Page 21 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Timing Diagrams
Read Cycle Timing[25]
tCYC
CLK
t
tADS
t CL
CH
tADH
ADSP
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
t
WES
t
WEH
GW, BWE,BW
X
Deselect Cycle
tCES t CEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OELZ
tCDV
t CHZ
tDOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05357 Rev. *F
Page 22 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Timing Diagrams (continued)
Write Cycle Timing[25, 26]
t CYC
CLK
t
tADS
t
CH
CL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
t
t
WES WEH
GW
tCES
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
OEHZ
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document #: 38-05357 Rev. *F
Page 23 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Timing Diagrams (continued)
Read/Write Cycle Timing[25, 27, 28]
tCYC
CLK
t
CH
tADS
tADH
tAS
tAH
t
CL
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
t
t
WES WEH
BWE, BWX
tCES
tCEH
CE
ADV
OE
tDS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
tOELZ
D(A3)
tCDV
Q(A2)
Back-to-Back READs
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
27. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
28. GW is HIGH.
Document #: 38-05357 Rev. *F
Page 24 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Timing Diagrams (continued)
ZZ Mode Timing[29, 30]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
29. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05357 Rev. *F
Page 25 of 31
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CY7C1441AV33
CY7C1443AV33
CY7C1447AV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
CY7C1441AV25-133AXC
Package
Diagram
Operating
Range
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1443AV33-133AXC
CY7C1441AV25-133BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-133BZC
CY7C1441AV25-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1443AV33-133BZXC
CY7C1447AV33-133BGC
CY7C1447AV33-133BGXC
CY7C1441AV25-133AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1443AV33-133AXI
CY7C1441AV25-133BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-133BZI
CY7C1441AV25-133BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1443AV33-133BZXI
CY7C1447AV33-133BGI
CY7C1447AV33-133BGXI
100
CY7C1441AV25-100AXC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1443AV33-100AXC
CY7C1441AV25-100BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-100BZC
CY7C1441AV25-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1443AV33-100BZXC
CY7C1447AV33-100BGC
CY7C1447AV33-100BGXC
CY7C1441AV25-100AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1443AV33-100AXI
CY7C1441AV25-100BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-100BZI
CY7C1441AV25-100BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1443AV33-100BZXI
CY7C1447AV33-100BGI
CY7C1447AV33-100BGXI
Document #: 38-05357 Rev. *F
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Page 26 of 31
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CY7C1441AV33
CY7C1443AV33
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Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05357 Rev. *F
A
Page 27 of 31
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CY7C1443AV33
CY7C1447AV33
Package Diagrams (continued)
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
B
15.00±0.10
0.15(4X)
51-85165-*A
SEATING PLANE
Document #: 38-05357 Rev. *F
1.40 MAX.
0.36
C
Page 28 of 31
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CY7C1443AV33
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Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
51-85167-**
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05357 Rev. *F
Page 29 of 31
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1441AV33
CY7C1443AV33
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Document History Page
Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through
SRAM
Document Number: 38-05357
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
124459
03/06/03
CJM
New Data Sheet
*A
254910
See ECN
SYT
Part number changed from previous revision. New and old part number differ
by the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Footnote #13 (32-Bit Vendor I.D Code changed)
Added Boundary scan information
Added IDD, IX and ISB values in the DC Electrical Characteristics
Added tPOWER specifications in Switching Characteristics table
Removed 119 PBGA Package
Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A
(14 x 22 x 1.76 mm)
*B
300131
See ECN
SYT
Removed 150 and 117 MHz Speed Bins
Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W respectively for
TQFP Package on Pg # 21
Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA
Packages.
Added comment of ‘Lead-free BG and BZ packages availability’ below the
Ordering Information
*C
320813
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA
Changed the test condition from VDD = Min. to VDD = Max for VOL in the
Electrical Characteristics table.
Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values.
Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 fBGA and
209 fBGA packages on the Thermal Resistance table.
Changed CIN,CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package.
Removed “Lead-free BG and BZ packages availability” comment below the
Ordering Information
*D
331551
See ECN
SYT
Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA
Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced TBD to 100 mA for IDDZZ
Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
Package.
Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively
Updated the Ordering Information by shading and unshading MPNs as per
availability
*E
417547
See ECN
RXU
Converted from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”.
Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respectively
and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30 µA
respectively on page# 19.
Modified test condition in note# 8 from VIH < VDD to VIH < VDD.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information.
Document #: 38-05357 Rev. *F
Page 30 of 31
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CY7C1443AV33
CY7C1447AV33
Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through
SRAM
Document Number: 38-05357
REV.
*F
Orig. of
ECN NO. Issue Date Change
473650
See ECN
Document #: 38-05357 Rev. *F
VKN
Description of Change
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
Page 31 of 31
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