Cypress CYK128K16MCCB 2-mbit (128k x 16) pseudo static ram Datasheet

CYK128K16MCCB
2-Mbit (128K x 16) Pseudo Static RAM
Features
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when the
chip is deselected (CE HIGH), or when the outputs are
disabled (OE HIGH), or when both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
• Wide voltage range: 2.70V–3.30V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 1mA @ f = 1 MHz
Writing to the device is accomplished by asserting Chip
Enable (CE LOW) and Write Enable (WE) input LOW. If Byte
Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A17). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written
into the location specified on the address pins (A0 through
A16).
— Typical active current: 14 mA @ f = fmax (For 55-ns)
— Typical active current: 8 mA @ f = fmax (For 70-ns)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
Reading from the device is accomplished by asserting Chip
Enable (CE LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. Refer to the truth table for a complete description of read
and write modes.
Functional Description[1]
The CYK128K16MCCB is a high-performance CMOS Pseudo
Static RAM organized as 128K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
128K × 16
RAM Array
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
A11
A12
A13
A14
A15
A16
BHE
WE
CE
OE
BLE
Power- Down
Circuit
BHE
BLE
CE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05584 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 27, 2005
CYK128K16MCCB
Pin Configuration[2, 3, 4]
48-ball VFBGA
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
NC
A7
I/O3
Vcc
D
VCC
I/O12
DNU
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Product Portfolio
Power Dissipation
Operating ICC (mA)
VCC Range (V)
Product
CYK128K16MCCB
Min.
Typ.[5]
2.70
3.0
f = 1MHz
Max.
Speed
(ns)
Typ.[5]
3.30
55
1
70
f = fmax
Standby ISB2(µA)
Max.
Typ.[5]
Max.
Typ.[5]
Max.
5
14
22
9
40
8
15
Notes:
2. Ball D3, H1, G2 and ball H6 for the FBGA package can be used to upgrade to a 4-Mbit, 8-Mbit, 16-Mbit and a 32-Mbit density, respectively.
3. NC “no connect”—not connected internally to the die.
4. DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05584 Rev. *C
Page 2 of 9
CYK128K16MCCB
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage to Ground Potential ................. –0.4V to 4.6V
Device
DC Voltage Applied to Outputs
in High-Z State[6, 7, 8] ........................................ –0.4V to 3.7V
Ambient
Temperature
Range
CYK128K16MCCB Industrial
–25°C to +85°C
VCC
2.70V to
3.30V
DC Input Voltage[6, 7, 8] .................................... –0.4V to 3.7V
Electrical Characteristics (Over the Operating Range)
CYK128K16MCCB-55 CYK128K16MCCB-70
Parameter
Description
Min. Typ.[5] Max.
Test Conditions
VCC
Supply Voltage
VOH
Output HIGH Voltage IOH = –0.1 mA
VCC = 2.70V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 2.70V
VIH
Input HIGH Voltage
VCC= 2.7V to 3.3V
VIL
Input LOW Voltage
2.7
3.0
Min. Typ.[5]
3.3
2.7
VCC –
0.4
3.0
Max. Unit
3.3
V
V
VCC –
0.4
0.4
0.4
V
0.8 *
VCC
VCC
+ 0.4V
0.8 *
VCC
VCC
+ 0.4V
V
–0.4
0.4
–0.4
0.4
V
IIX
Input Leakage Current GND < VIN < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
–1
+1
–1
+1
µA
ICC
VCC Operating Supply f = fMAX = 1/tRC
Current
f = 1 MHz
GND < VOUT < VCC, Output Disabled
VCC = VCCmax
IOUT = 0 mA
CMOS levels
14
22
8
15
mA
1
5
1
5
mA
ISB1
Automatic CE
CE > VCC − 0.2V
VCC = 3.3V
Power-Down Current VIN > VCC – 0.2V, VIN <
0.2V) f = fMAX (Address
—CMOS Inputs
and Data Only), f = 0
(OE, WE, BHE and BLE),
VCC = 3.30V
40
250
40
250
µA
ISB2
VCC = 3.3V
Automatic CE
CE > VCC – 0.2V
Power-Down Current VIN > VCC – 0.2V or VIN <
0.2V, f = 0, VCC = 3.30V
—CMOS Inputs
9
40
9
40
µA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
8
pF
8
pF
Thermal Resistance[9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
BGA
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per EIA
/ JESD51.
55
°C/W
17
°C/W
Notes:
6. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
7. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
8. Overshoot and undershoot specifications are characterized and are not 100% tested.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05584 Rev. *C
Page 3 of 9
CYK128K16MCCB
AC Test Loads and Waveforms
R1
VCC
VCC
OUTPUT
GND
R2
30 pF
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
3.0V VCC
Unit
R1
22000
Ω
R2
22000
Ω
RTH
11000
Ω
VTH
1.50
V
Switching Characteristics Over the Operating Range [10]
55 ns[14]
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
55[14]
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
55
OE LOW to LOW
Z[11, 13]
tHZOE
OE HIGH to High
Z[11, 13]
tLZCE
CE LOW to Low Z[11, 13]
tLZOE
70
5
tHZCE
CE HIGH to High
tDBE
BLE/BHE LOW to Data Valid
Z[11, 13]
70
10
5
25
ns
ns
5
2
Z[11, 13]
ns
ns
25
5
ns
ns
25
25
ns
55
70
ns
tLZBE
BLE/BHE LOW to Low
tHZBE
BLE/BHE HIGH to HIGH Z[11, 13]
10
25
ns
Address Skew
0
10
ns
tSK[14]
Write Cycle
5
5
ns
[12]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels
of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
Document #: 38-05584 Rev. *C
Page 4 of 9
CYK128K16MCCB
Switching Characteristics Over the Operating Range (continued)[10]
55 ns[14]
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
tBW
BLE/BHE LOW to Write End
50
60
ns
tSD
Data Set-Up to Write End
25
45
ns
tHD
Data Hold from Write End
0
0
ns
[11, 13]
WE LOW to High-Z
tHZWE
WE HIGH to Low-Z
tLZWE
25
[11, 13]
5
25
5
ns
ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[15, 16, 17]
tRC
ADDRESS
tSK
DATA OUT
tOHA
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled)[16, 17]
ADDRESS
CE
tRC
tSK
tHZCE
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes:
15. Device is continuously selected. OE, CE = VIL.
16. WE is HIGH for Read Cycle.
17. For the 55-ns Cycle, the addresses must not toggle once the read is started on the device. For the 70-ns Cycle, the addresses must be stable within 10 ns after
the start of the read cycle.
Document #: 38-05584 Rev. *C
Page 5 of 9
CYK128K16MCCB
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 18, 19, 20]
t WC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
DON’T CARE
tHZOE
Write Cycle 2 (CE Controlled)[12, 13, 18, 19, 20]
t WC
ADDRESS
tSCE
CE
tSA
tHA
tAW
tPWE
WE
tBW
BHE/BLE
OE
t HZOE
DATA I/O
DON’T CARE
tSD
tHD
VALID DATA
Notes:
18. Data I/O is high impedance if OE > VIH.
19. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state.
20. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05584 Rev. *C
Page 6 of 9
CYK128K16MCCB
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[19, 20]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tHD
tSD
DON’T CARE
DATAI/O
VALID DATA
tLZWE
tHZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[19, 20]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DON’T CARE
DATA I/O
tHD
VALID DATA
Truth Table [21]
CE
WE
OE
BHE
BLE
H
X
X
X
X
X
X
X
H
H
L
H
L
L
L
L
H
L
H
L
Inputs/Outputs
Mode
Power
High Z
Deselect/Power-Down
Standby (ISB)
High Z
Deselect/Power-Down
Standby (ISB)
Data Out (I/O0–I/O15)
Read
Active (ICC)
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read
Active (ICC)
Note:
21. H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Document #: 38-05584 Rev. *C
Page 7 of 9
CYK128K16MCCB
Truth Table (continued)[21]
CE
WE
OE
BHE
BLE
L
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Inputs/Outputs
Mode
Power
Read
Active (ICC)
L
H
H
L
H
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
High Z
Output Disabled
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
L
X
L
L
Data In (I/O0–I/O7); High Z (I/O8–I/O15)
Write
Active (ICC)
H
High Z (I/O0–I/O7); Data In (I/O8–I/O15)
Write
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
55
CYK128K16MCCBU-55BVI
BV48A
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm)
Industrial
70
CYK128K16MCCBU-70BVI
BV48A
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm)
Industrial
55
CYK128K16MCBU-55BVXI
BV48A
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free)
Industrial
70
CYK128K16MCBU-70BVXI
BV48A
48-ball Very Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free)
Industrial
Package Diagram
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*B
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and
company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05584 Rev. *C
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYK128K16MCCB
Document History Page
Document Title: CYK128K16MCCB 2-Mbit (128K x 16) Pseudo Static RAM
Document Number: 38-05584
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
229571
See ECN
REF
New data sheet
*A
224474
See ECN
SYT
Changed ball E3 on the package pinout from NC to DNU
*B
263150
See ECN
PCI
Changed from preliminary to final
*C
314013
See ECN
RKF
Added Pb-Free parts to the Ordering information
Document #: 38-05584 Rev. *C
Page 9 of 9
Similar pages