AT89C51RB2 / RC2 & T89C51IC2 QualPack Qualification Package AT89C51RB2 / RC2 & T89C51IC2 FLASH C51 Microcontrollers AT89C51RB2 / RC2 & T89C51IC2 June 2002 Rev. 1 – 2002 June 1 AT89C51RB2 / RC2 & T89C51IC2 QualPack 1 Table of contents 1 TABLE OF CONTENTS ....................................................................................................................................................2 2 GENERAL INFORMATION.............................................................................................................................................3 3 TECHNOLOGY INFORMATION...................................................................................................................................4 3.1 3.2 3.3 4 WAFER PROCESS TECHNOLOGY ....................................................................................................................................4 PRODUCT DESIGN ..........................................................................................................................................................5 DEVICE CROSS SECTION .................................................................................................................................................6 QUALIFICATION ..............................................................................................................................................................7 4.1 QUALIFICATION METHODOLOGY....................................................................................................................................7 4.2 QUALIFICATION TEST METHODS.....................................................................................................................................8 4.3 WAFER LEVEL RELIABILITY ..........................................................................................................................................9 4.3.1 Electromigration.......................................................................................................................................................9 4.3.2 Hot carriers injection .............................................................................................................................................11 4.3.3 Time Dependent Dielectric Breakdown..................................................................................................................12 4.3.4 FLASH characteristics ...........................................................................................................................................14 4.3.4.1 4.3.4.2 4.3.4.3 4.3.4.4 Cell endurance .................................................................................................................................................................14 Cell retention ...................................................................................................................................................................15 Cell Read Disturb ............................................................................................................................................................16 Wafer probe Data retention measurement........................................................................................................................17 4.4 DEVICE RELIABILITY....................................................................................................................................................18 4.4.1 AT89C51RC2 tests..................................................................................................................................................18 4.4.2 AT89C51RC2 reliability calculation ......................................................................................................................19 4.5 PACKAGING RELIABILITY .............................................................................................................................................20 4.6 QUALIFICATION STATUS ..............................................................................................................................................20 5 ENVIRONMENTAL INFORMATION ..........................................................................................................................21 6 OTHER DATA ..................................................................................................................................................................22 6.1 6.2 6.3 ISO9001 AND QS9000 CERTIFICATES .........................................................................................................................22 DATA BOOK REFERENCE .............................................................................................................................................23 REVISION HISTORY ......................................................................................................................................................23 Rev. 1 – 2002 June 2 AT89C51RB2 / RC2 & T89C51IC2 QualPack 2 General Information Product Name: Function: AT89C51RC2 / RB2 8-bit Microcontrollers with 32KB / 16KB FLASH Product Name: Function: T89C51IC2 8-bit Microcontroller with 32KB FLASH Two Wires Interface (TWI), 32KHz Oscillator Wafer Process: Logic CMOS 0.35um with embedded FLASH Available Package Types PLCC 44, VQFP 44 1.4mm, PDIL40 (not available for T89C51IC2) Other Forms: Die, Wafer Locations: Process Development, Product Development Wafer Plant QC Responsibility Probe Test Assembly Final Test Lot Release Shipment Control Quality Assurance Reliability Testing Failure Analysis Atmel Colorado Springs, USA Atmel Nantes, France Atmel Colorado Springs, USA Atmel Nantes, France Atmel Colorado Springs, USA Dependant upon Package Dependant upon Package Atmel Nantes, France Global Logistic Center, Philippines Atmel Nantes, France Atmel Nantes, France Atmel Nantes, France Quality Management Atmel Nantes, France Signed: Pascal LECUYER Rev. 1 – 2002 June 3 AT89C51RB2 / RC2 & T89C51IC2 QualPack 3 Technology Information 3.1 Wafer Process Technology Process Type (Name): Logic 0.35um with embedded FLASH (AT56800) Base Material: Wafer Thickness (final) Wafer Diameter Epitaxied Silicon 475um 150mm Number Of Masks 27 Gate Oxide (Logic transistors) Material Thickness Silicon Dioxide 68 A Gate Oxide (EPROM cell) Material Thickness Silicon Dioxide 390 A Polysilicon Number of Layers Thickness Poly 1 Thickness Poly 2 2 1400A Amorphous 3200A Metal Number of Layers Material: Layer 1 Thickness Layer 2 Thickness Layer 3 Thickness 3 AlCu 5000A 5000A 8000A Passivation Material Thickness Oxide HDP/ Oxynitride 21000A Rev. 1 – 2002 June 4 AT89C51RB2 / RC2 & T89C51IC2 QualPack 3.2 Product Design 2 Die Size Pad Size Openning / Pitch 14.13 mm 79um * 91um / 126um Logic Effective Channel Length 0.35µm Gate Poly Width (min.) Gate Poly Spacing (min.) 0.35µm 0.42µm Metal 1 Metal 1 Metal 2 Metal 2 Metal 3 Metal 3 Width Spacing Width Spacing Width Spacing 0.42µm 0.49µm 0.56µm 0.49µm 0.56µm 0.49µm Contact Size Contact Spacing 0.35µm 0.42µm Via 1 Size Via 2 Size 0.42µm 0.42µm Rev. 1 – 2002 June 5 AT89C51RB2 / RC2 & T89C51IC2 QualPack 3.3 Device cross section AT56Kxx cross section Rev. 1 – 2002 June 6 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4 Qualification 4.1 Qualification methodology All product qualifications are split into three distinct steps as shown below. Before a product is released for use, successful qualification testing are required at wafer, device and package level. - Wafer Level Reliability consists in testing individually basic process modules regarding their well known potential limitations (Electromigration, Hot Carriers Injection, Oxide Breakdown, NVM Data Retention). Each test is performed using wafer process specific structures. - Device reliability is covering either dice design and processing aspects. The tests are performed on device under qualification, but generic data may also be considered for reliability calculation. - For each package type proposed in the Datasheet, it is verified that qualification data are available. If not qualification tests are carried out for the new package types. In addition, one package type is selected to verify packaging reliability of the device under qualification. Product Qualification Wafer Level Device Packaging (Design / Process) Reliability Rev. 1 – 2002 June Reliability Reliability 7 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.2 Qualification test methods General Requirements for Plastic packaged CMOS Ics. Standard Test Description Acceptance MIL-STD 883 Method 1005 Electrical Life Test (Early Failure Rate) 48 hours 140°C 0/300 - 48h MIL-STD 883 Method 1005 Electrical Life Test (Latent Failure Rate) 1000 hours 140°C Dynamic or Static 0/100 - 500h MIL-STD 883 Method 3015.7 Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses 0/3 per level JEDEC 78 Latch up 50mW power injection, 50% overvoltage @125°C 0/5 per stress AEC Q100 Method 005 NVM Endurance Program Erase Cycles 25°C 0/50 - 100kc AEC Q100 Method 005 NVM Data Retention High Temperature Storage 165°C 0/50 - 500h MIL-STD 883 Method 1010 Temperature Cycling 1000 cycles -65°C/150°C air/air 0/50 - 500c Atmel PAQA0184 HAST after Preconditioning 144 hours 130°C/85%RH 0/50 - 72h EIA JESD22-A101 85/85 Humidity Test 1000 hours 85°C/85%RH 0/50 - 500h EIA JESD22-A110 HAST 336 hours 130°C/85%RH/5.5V 0/50 - 168h EIA JEDEC 20-STD Preconditioning Soldering Stress 220°C/235°c/3 times 0/11 per class MIL-STD 883 Method 2003 Solderability 0/3 MIL-STD 883 Method 2015 Marking Permanency 0/5 Rev. 1 – 2002 June 8 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.3 Wafer Level Reliability 4.3.1 Electromigration Purpose: To evaluate the AT56800, AT35500, and AT37000 processes for Metal 1, Metal 3 & Via Electromigration Reliability. Test Parameters: Metal 1 & Metal 3: Sample Size = 15 Temp = 250C with Joule heating . J = 3.5E06 A/cm2. Via: Sample Size = 15 Temp = 200C with Joule heating. J = 2.5E06 A/cm2. Black’s Equation Parameters: Failure Criteria - 10% increase in resistance. Data taken every 1% change. n=2 Ea = 0.6eV Lifetime Predictions: Metal 1 : Split 1 - Tf.1% exp = ~ 28 hrs Tf.01% op = ~ 28 hrs x 39706 accel = 127 years. (Sigma = 2.7118 hours, Acceltemp = 130, Accelcurrent = 306) Metal 3 : Split 3 - Tf.1% exp = ~ 140 hrs Tf.01% op = ~ 140 hrs x 39706 accel = 634 years. (Sigma = 1.8782 hours, Acceltemp = 130, Accelcurrent = 306) VIA : Split 4 - Tf.1% exp = ~ 22 hrs Tf.1% op = ~ 22 hrs x 7144 accel = 18 years. (Sigma = 2.59 hours, Acceltemp = 31.75, Accelcurrent = 225) (9/15 fails) Conclusion: All splits pass the minimum 10 years lifetime. Rev. 1 – 2002 June 9 AT89C51RB2 / RC2 & T89C51IC2 QualPack Test results : AT56800 metal 1 results AT56800 metal 3 results AT56800 VIA results Electromigration summary table: Level M1 M3 Via Rev. 1 – 2002 June 10 Sample Size 15 15 15 Fails @ 10% 9 7 9 Tf.1% Lifetime (yrs) 140 1088 19 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.3.2 Hot carriers injection Test conditions The test is performed by forcing a high drain bias on the test device (Vds>Vddmax) to accelerate the carriers to the maximum. At the same time the gate bias (Vgs) is chosen in order to maximize the injection of carriers into the gate oxide and also the substrate. WLR_B n-channel W/L 0.35um/25um the stress is performed on a number of transistors, each at a different stress condition Vds,stress and Vgs,stress. For each transistor, the time to reach the failure criteria (dIdsat/Idsat=10%) is obtained. NMOS is more sensitive to hot carriers compared to PMOS. Consequently NMOS is the only structure tested. Measurement AT568T7 lot 1J0433 has been measured using the WLR_B hot electron structure with standard drain. NMOS W/L = 25/0.35um. Results HCI 56.8k 1J0433 AT568T7 FAB 5 N-Channel W/L 0.35/25.0um 10% Change in Idsat 1 y = 5E+16x30,692 Tau Lifetime in years 0,1 R2 = 0,9719 0,01 0,001 0,0001 0,2 0,22 0,24 0,26 0,28 0,3 1/Vdd Conclusion The extrapolated life time in the worst case conditions (@Vds=Vdd max & Vgs set to maximize substrate current) is much greater than 0.2 years in DC mode (qualification requirement) which is equivalent to more than 10 years in AC mode. Rev. 1 – 2002 June 11 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.3.3 Time Dependent Dielectric Breakdown Purpose: To evaluate the AT56800 thin gate oxide TDDB performance as follows: a) To determine the activation energy of gate oxide failures on STI active edge capacitors b) To determine the field acceleration factor for intrinsic gate oxide failures c) To determine the sigma the lognormal standard deviation of the time to breakdown distribution of the intrinsic gate oxide Test Parameters: Lot Min thickness: Max thickness: Capacitor size: 9G3470 (wafers 4, 5, 18) 72.9A 74.7A 2 6.267um The stress conditions used are shown below: Temperature/Field 9.5MV/cm 225C N=5 200C N=5 175C N=5 10.0MV/cm N=5 N=5 N=5 10.5MV/cm N=5 N=5 N=6 Accumulated total stress time: 132 hours / 46 capacitors Calculation Parameters: Failure Criteria: Temp/Voltage use: Oxide thickness: 0.01% failures 105°c / 3.3v 63A (target –10%) Lifetime Prediction: The equation used to describe the breakdown of gate oxides is: Tbd(i) = exp(SIGMA*Z(i) + GAMMA*Eox +Ea/kT + T0) Where th Tbd(i) is the time to breakdown of the i capacitor, SIGMA is the lognormal standard deviation of the breakdown distribution, th Z(i) is the Z-score of the i capacitor (essentially the difference between its breakdown time and the mean measured in standard deviations), GAMMA is the Field acceleration constant, Eox is the oxide field, Ea is the activation energy of this failure mechanism, K is Boltzmann’s constant, T is the Kelvin Temperature, and T0 is a fitting constant. Rev. 1 – 2002 June 12 AT89C51RB2 / RC2 & T89C51IC2 QualPack The best fit coefficients in the regression analysis are: T0= 14.25034317 LN-sec Ea= 1.060043152 eV GAMMA= -3.2454227 LN-sec-cm/MV SIGMA= 0.414655753 LN-sec with an adjusted r-squared of 97.99%. The intrinsic lifetime at use conditions calculated from this regression is 56174 years. Conclusion: Using the coefficients determined above, the time to reach any cumulative percent failure level can be estimated given the stress conditions. Using 105C and 3.3 volts on 63 Angstrom N-Channel gate2 oxide, we may expect 0.01% of capacitors having 6,267 square microns area with 6,174 microns of active edge to fail in about 613 years, exceeding the technology requirement of ten years. Test results : AT56.8K Active Edge TDDB 225C 2,00000E+00 1,00000E+00 0,00000E+00 -1,00000E+00 -2,00000E+00 AT56.8K Active Edge TDDB 200C 2,00000E+00 1,00000E+00 0,00000E+00 -1,00000E+00 -2,00000E+00 1,00 1,00 1,00 1,00 1,00 1,00 E+00 E+01 E+02 E+03 E+04 E+05 1,00 1,00 1,00 1,00 1,00 1,00 E+00 E+01 E+02 E+03 E+04 E+05 Tbd (sec) Tbd (sec) AT56.8K Active Edge TDDB 175C 2,00000E+00 1,00000E+00 0,00000E+00 -1,00000E+00 -2,00000E+00 1,00 1,00 1,00 1,00 1,00 1,00 E+00 E+01 E+02 E+03 E+04 E+05 Tbd (sec) Rev. 1 – 2002 June 13 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.3.4 FLASH characteristics 4.3.4.1 Cell endurance Purpose: To evaluate the ability of memory cell to withstand high number of program/erase cycles without change of electrical characteristics. Test Parameters: Measurements have been done on lot 0r5414 (MP044 reticle). Test done on 2 cells in a byte : st - cell near byte select transistor, called bit0 (1 column) th - cell near Vss contact, called bit 7 (8 column). Cycling is done for various programming voltages : - write : 13.5V on BL / 15.6V on select - clear : 13.5V on sense / 15.6V on select @5ms 14.5V on BL / 16.6V on select @5ms 14.5V on sense / 16.6V on select 15.5V on BL / 17.6V on select 15.5V on sense / 17.6V on select 16.5V on BL / 17.6V on select 16.5V on sense / 17.6V on select MP044 0R5414 #01 Vsel=Vbl+2.1 Bit 7 (near Vss) MP044 0R5414 #01 Vsel=Vbl+2.1 Bit 0 (near byte sel) 0 0 -0.5 -0.5 13.5V 14.5V 15.5V 16.5V -1.5 Vt_wrt (V) Vt_wrt (V) 13.5V -1 14.5V -1 15.5V 16.5V -1.5 -2 -2 -2.5 -2.5 1 10 100 1000 10000 1 100000 10 100 MP044 0R5414 #01 Vsel=Vsen+2.1 Bit 0 (near byte sel) 10000 100000 MP044 0R5414 #01 Vsel=Vsen+2.1 Bit 7 (near Vss) 7 7 6.5 6.5 6 6 5.5 13.5V 5 14.5V 15.5V 4.5 16.5V 4 3.5 Vt_clr (V) Vt_clr (V) 1000 # cycles # cycles 5.5 13.5V 5 14.5V 15.5V 4.5 16.5V 4 3.5 3 3 2.5 2.5 2 2 1 10 100 1000 # cycles Rev. 1 – 2002 June 14 10000 100000 1 10 100 1000 # cycles 10000 100000 AT89C51RB2 / RC2 & T89C51IC2 QualPack Conclusions: Vt_wrt shift of 200mV after 10k cycles I_read decrease of 2.5uA after 10kcycles (- 7 to 9 %) No big difference between bit0 and bit 7 in terms of Vt or current variations Using the coefficients - 4.3.4.2 Cell retention Purpose: To extrapolate cell life duration at 125°c from bake measurements at high temperature. Test parameters: Lot: 9T0930 Temperature: 250°c and 200°c Duration: 92 hours Lifetime Prediction: The equation used to describe memory cell retention is: DVt (V) = A * (t[h])^m * exp (-1.05eV/kT[K]) Results : 56.8k cell - 9t0930 (#24/25) 0 1 10 100 y = 0,2138Ln(x) - 2,3118 -2 -3 T (C) ln [DVt (V)] -1 200C y = 0,2211Ln(x) - 4,8026 250C -4 290,0 270,0 250,0 230,0 210,0 190,0 170,0 150,0 1 -5 10 100 1000 10000 100000 time (h) Bake time (h) Test measurements Extrapolated Life Time Conclusions : Extrapolation to 125C - 10years = Vt loss is less than 0.8mV Rev. 1 – 2002 June 15 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.3.4.3 Cell Read Disturb Purpose: To measure read disturb influence on 56k8 memory cell. Test parameters: Lot: 0t0348 Programming: 14V on WL and sensegate @5ms Temperature: 25°c and 140°c The cell is stressed with BL voltage much higher than standard read conditions (around 6V) to accelerate disturb phenomenon : electrons from the Floating gate can move through the tunnel oxide. This charge loss is measured after stress by a Vt measurement. Test results: 0t0348 #01 56.8k (568A6) BL rea d disturb @25C 0t0348 #01 56.8k (568A6) BL read disturb @140C 2.5 2.5 2 2 Vbl=6. 5V Vbl=7V Vbl=7. 5V 1 Vbl=6V Delta Vt (V) Delta Vt (V) Vbl=6V 1.5 1.5 Vbl=6.5V Vbl=7V Vbl=7.5V 1 Vbl=8V 0.5 Vbl=8V 0.5 0 0 0.1 1 10 100 Time (s) 1000 10000 0.1 1 10 100 Time (s) 1000 10000 Conclusion: Extrapolation to 10 years lifetime give a maximum BL voltage of around 4V in read operation, which is much higher than nominal BL read voltage (~1V). So there is no sensitivity to read disturb either at room temperature or high temperature. Rev. 1 – 2002 June 16 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.3.4.4 Wafer probe Data retention measurement Data retention has been verified after bake for 168 hours at 250°C on 3 wafers of a standard production lot. The results are summarized in the table below: Lot 1G4448 1G4448 1G4448 Total Wafer % Retention loss 6 8 12 0% 0% 0% 0% Failure rate extrapolation at 55°C 3.91fit 4.19fit 3..96fit 1.34fit Time to failure >> 10 years >> 10 years >> 10 years >> 10 years Conclusion: Data Retention measurements at wafer probe stand out high data retention capability of AT56800 products, exceeding the technology requirement of ten years. Rev. 1 – 2002 June 17 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.4 Device reliability 4.4.1 AT89C51RB2 / RC2 & T89C51IC2 tests AT89C51RC2 test results are summarized in the table below: Lot Device Type Test Description A00498A T89C51RC2 PLCC 44 EFR Dynamic Life Test LFR Life Test A00637B T89C51RC2 PLCC 44 EFR Dynamic Life Test LFR Life Test FLASH Data Retention FLASH Endurance A00366 T89C51IC2 PLCC 44 ESD-HBM Model LATCH-UP Over-Voltage Power Injection Rev. 1 – 2002 June 18 Step Result 12h 48h 0/270 0/266 168h 500h 1000h 12h 48h 0/100 0/100 0/100 0/350 0/350 168h 500h 1000h 500h 1000h 0/100 0/100 0/100 0/50 0/50 10kc 0/33 2000V 3000V 4000V 0/3 0/3 3/3 5.5v 50mW 0/5 0/5 Comment Class 2 of MIL STD 883 Functional Test done at 90°c Classified latch-up free in commercial and industrial range AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.4.2 AT89C51RB2 / RC2 & T89C51IC2 reliability calculation In the next table, it is proposed a AT89C51RC2 reliability prediction calculated at 55°c for 60% confidence level from generic test data collected during the 12 last months process monitor. Lots Device Type Test Description Step Result Comment A00151S A00712 A00588A T89C51CC01 TQFP 44 EFR Dynamic Life Test 48h 1/809 1 Icc drift caused by a contact particle 1000h 0/264 A00498A A00637B T89C51RC2 PLCC 44 48h 1/616 1000h 0/200 48h 0/300 LFR Life Test 1000h 0/200 LFR Life Test EFR Dynamic Life Test LFR Life Test A00330K A00365J T83C51IC2 PLCC 44 EFR Dynamic Life Test 1 Ipd drift caused by interlayer oxide thinning A00470K T89C51CC02 SOW 28 LFR Life Test 168h 0/100 Global All products EFR Dynamic Life Test 48h 2/1725 1159 ppm - 0/764 8 fit LFR Life Test Rev. 1 – 2002 June an 19 AT89C51RB2 / RC2 & T89C51IC2 QualPack 4.5 AT89C51RB2 / RC2 & T89C51IC2 Packaging reliability In this section are presented the packaging qualification measurements carried out for AT89C51RC2 in PLCC 44. Lots Device Type Test Description A00498A T89C51RC2 PLCC44 85/85 Humidity 168h 500h 1000h 0/50 0/50 0/50 Thermal Cycles 200c 500c 1000c 0/50 0/50 0/50 HAST & Thermal shocks post Preconditioning L1 72h 144h 0/50 0/50 Preconditioning Level 1 SAM Visual Elect. 0/22 0/50 0/50 85/85 Humidity 168h 500h 1000h 0/50 0/50 0/50 Thermal Cycles 100c 500c 1000c 0/50 0/50 0/50 HAST & Thermal Shocks post Preconditioning L1 72h 144h 0/50 0/50 Preconditioning Level 1 SAM Visual Elect. 0/22 0/50 0/50 A00637B 4.6 T89C51RC2 PLCC 44 Step Result Comment AT89C51RB2 / RC2 & T89C51IC2 Qualification status Atmel digital 0.35um wafer process is qualified since 1999, October. Derived from this technology, the AT89C51RC2 has demonstrated high reliability all over the various testing reported in this document. Full qualification has been pronounced on 2002, January. Rev. 1 – 2002 June 20 AT89C51RB2 / RC2 & T89C51IC2 QualPack 5 Environmental Information Atmel Nantes Environmental Policy aims are : - Reducing the use of harmful chemicals in its processes - Reducing the content of harmful materials in its products - Using re-usable materials wherever possible - Reducing the energy content of its products As part of that plan, Ozone Depleting Chemicals are being replaced either by Atmel Nantes or its sub-contractors. Atmel Nantes site is ISO14001 certified since May 2000. Rev. 1 – 2002 June 21 AT89C51RB2 / RC2 & T89C51IC2 QualPack 6 Other Data 6.1 ISO9001 and QS9000 Certificates Rev. 1 – 2002 June 22 AT89C51RB2 / RC2 & T89C51IC2 QualPack 6.2 Data Book Reference The data sheet is available upon request to sales representative or upon direct access on Atmel web site: http://www.atmel.com/ Address References All inquiries relating to this document should be addressed to the following: Atmel Nantes BP70602 44306 Nantes Cedex 3 France Telephone (33) 2 40 18 18 18 Telefax (33) 2 40 18 19 00 Or direct contact Pascal LECUYER Telephone (33) 2 40 18 17 73 Telefax (33) 2 40 18 19 00 6.3 Revision History Issue 0 1 Modification Notice Initial Product Qualification (T89C51RB2/RC2/IC2) Die Size update (AT89C51RB2/RC2 & T89C51IC2) Application Date 2002 January 2002 June Remarks: The information given in this document is believed to be accurate and reliable. However, no responsibility is assumed by Atmel for its use. No specific guarantee or warranty is implied or given by this data unless agreed in writing elsewhere. Atmel reserves the right to update or modify this information without notification, at any time, in the interest of providing the latest information. Parts of this publication may be reproduced without special permission on the condition that our author and source are quoted and that two copies of such extracts are placed at our disposal after publication. Before use of such reproduced material the user should check that the information is current. Written permission must be obtained from the publisher for complete reprints or translations Rev. 1 – 2002 June 23