DATASHEET ISL9440, ISL9440A, ISL9441 Triple, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller The ISL9440, ISL9440A and ISL9441 are quad-output synchronous buck controllers that integrate 3 PWM controllers and 1 low drop-out linear regulator controller, which are full featured and designed to provide multi-rail power for use in products such as cable and satellite set-top boxes, VoIP gateways, cable modems, and other home connectivity products as well as a variety of industrial and general purpose applications. Each output is adjustable down to 0.8V. The PWMs are synchronized at 180° out of phase thus reducing the RMS input current and ripple voltage. The ISL9440, ISL9440A and ISL9441 offer internal soft-start, independent enable inputs for ease of supply rail sequencing, and integrated UV/OV/OC/OT protections in a space conscious 5mmx5mm QFN package. The ISL9440 and ISL9440A offers an early warning function to output a logic signal to warn the system to back up data when the input voltage falls below a certain level. The ISL9440, ISL9440A and ISL9441 are utilize internal loop compensation to keep minimum peripheral components for compact design and a low total solution cost. These devices are implemented with current mode control with feed forward to cover various applications even with fixed internal compensations. The table below shows the difference in terms of the ISL9440, ISL9440A and ISL9441 features. PART NUMBER EARLY WARNING SWITCHING FREQUENCY (kHz) ISL9440 YES 300 ISL9440A YES 600 ISL9441 NO 300 FN6383 Rev 2.00 February 9, 2015 Features • Three integrated synchronous buck PWM controllers - Internal bootstrap diodes - Internal compensation - Internal soft-start • Independent control for each regulator and programmable output voltages; independent enable/shutdown • Fixed Switching Frequency: 300kHz (ISL9440, ISL9441); 600kHz (ISL9440A) • Adaptive shoot through protection on all synchronous buck controllers • Independently programmable voltage outputs • Out-of-phase switching to reduce input capacitance (0°/180°/0°) • No external current sense resistor - Uses lower MOSFET’s rDS(ON) • Current mode controller with voltage feed forward • Complete protection - Overcurrent, overvoltage, undervoltage lockout, over-temperature • Cycle-by-cycle current limiting • Wide input voltage range - Input rail powers VIN Pin: 5.6V to 24V - Input rail powers VCC_5V Pin (VIN tied to VCC_5V, for 5V input applications): 4.5V to 5.6V • Early warning (ISL9440, ISL9440A) on input voltage failure • Integrated reset function (ISL9440, ISL9440A) • Pb-free (RoHS compliant) Applications • Satellite and cable set-top boxes • Cable modems • VoX gateway devices • NAS/SAN devices Related Literature • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages” FN6383 Rev 2.00 February 9, 2015 Page 1 of 20 ISL9440, ISL9440A, ISL9441 Pinout PHASE1 BOOT1 UGATE1 LGATE1 LGATE2 UGATE2 BOOT2 PHASE2 ISL9440, ISL9440A, ISL9441 (32 LD 5X5 QFN) TOP VIEW 32 31 30 29 28 27 26 25 VCC_5V 3 22 LGATE3 VIN 4 21 UGATE3 EN1 5 20 BOOT3 FB1 6 19 PHASE3 OCSET1 7 18 ISEN3 RST 8 17 EN3 9 10 11 12 13 14 15 16 FB3 PGND OCSET3 23 EN2 2 FB2 PGOOD OCSET2 ISEN2 SGND 24 LDOFB 1 G4 ISEN1 Ordering Information PART NUMBER (Note 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL9440IRZ* ISL9440IRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B ISL9440AIRZ* 9440AIRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B ISL9441IRZ* ISL9441IRZ -40 to +85 32 Ld 5x5 QFN L32.5x5B NOTES: 1. *Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9440, ISL9440A, ISL9441. For more information on MSL, please see tech brief TB363 FN6383 Rev 2.00 February 9, 2015 Page 2 of 20 BOOT1 PGOOD RST VCC_5V VIN PGND EN1 EN2 EN3 BOOT2 VCC_5V VCC_5V UGATE1 UGATE2 PHASE1 PHASE2 ADAPTIVE DEAD-TIME VCC_5V ADAPTIVE DEAD-TIME V/I SAMPLE TIMING VCC_5V V/I SAMPLE TIMING LGATE1 LGATE2 POR ENABLE PGND PGND BIAS SUPPLIES BOOT3 0.8V REF + G4 VCC_5V REFERENCE VE 0.8V REF UGATE3 FAULT LATCH - gm*VE PHASE3 FB4 SOFT-START ADAPTIVE DEAD-TIME EARLY WARNING (see note 6) V/I SAMPLE TIMING VCC_5V LGATE3 0.8V REF 18.5pF 1400k FB1 180k PGOOD OCP PGND 16k + ERROR AMP 1 0.8V REF - PWM1 OC1 OC2 OC3 UV UV/OV PWM3 FB3 + FB1 FB2 FB3 FB4 VIN ISEN3 OCSET3 OC3 DUTY CYCLE RAMP GENERATOR PWM CHANNEL PHASE CONTROL ISEN1 CURRENT SAMPLE + CHANNEL 3 PWM2 CURRENT SAMPLE FB2 OCSET1 + 1.75V REFERENCE ISEN2 - Page 3 of 20 + OC2 OC1 SAME STATE FOR 2 CLOCK CYCLES REQUIRED TO LATCH OVERCURRENT FAULT OCSET2 CHANNEL 2 VIN SGND VCC_5V CHANNEL 1 0.8V REF ISL9440, ISL9440A, ISL9441 FN6383 Rev 2.00 February 9, 2015 Block Diagram ISL9440, ISL9440A, ISL9441 Typical Application - ISL9440, ISL9441 +12V + C1 56µF C2 4.7µF C16 1µF VIN VCC_5V 3 4 C3 10µF BOOT1 C7 0.1µF VOUT1 +2.5V, 6A + C9 330µF + C14 330µF 26 UGATE1 30 27 PHASE1 32 25 L1 R3 3.3µH 8.45k ISEN1 1 24 13 FB1 VOUT3 +5V VOUT4 Q4 IRF7404 2.2µH VOUT2 + C15 + C10 330µF 330µF R5 4.02k Q2 IRF7907 FB2 +1.5V, 6A R6 4.53k ISL9440/ISL9441 G4 20 19 LDOFB C61 1µF BOOT3 9 +3.3V, 500mA C12 + 68µF L2 ISEN2 R4 +12V 21 R10 15k PHASE2 6 C11 0.01µF R12 100 C8 0.1µF UGATE2 28 LGATE2 29 IRF7907 R2 4.75k C6 10µF BOOT2 8.45k LGATE1 Q1 R1 10.2k 31 10 18 C81 0.1µF UGATE3 PHASE3 L3 ISEN3 R41 15µH 2.8k R11 4.75k 22 LGATE3 R71 301k OCSET1 R72 301k R73 261k OCSET2 16 7 Q3 IRF7907 FB3 VOUT3 + C13 330µF R51 24.3k +5V, 2A R52 100 C52 2.2nF V VCC_5V 12 R91 10k OCSET3 15 8 RST R61 4.53k RST V VCC_5V R9 10k 2 5 14 17 23 PGOOD PGOOD 11 EN1 EN2 EN3 PGND SGND FN6383 Rev 2.00 February 9, 2015 Page 4 of 20 ISL9440, ISL9440A, ISL9441 Typical Application - ISL9440A +12V + C1 56µF C2 4.7µF C16 1µF VIN VCC_5V 4 C3 10µF BOOT1 C7 0.1µF L1 VOUT1 +2.5V, 6A + C9 330µF + C14 330µF 26 UGATE1 30 27 PHASE1 32 25 ISEN1 1 24 8.45k 29 13 FB1 VOUT3 +5V VOUT4 Q4 IRF7404 1.2µH VOUT2 + C15 + C10 330µF 330µF R5 4.02k Q2 IRF7907 FB2 +1.5V, 6A R6 4.53k ISL9440A G4 20 19 LDOFB C61 1µF BOOT3 9 +3.3V, 500mA R10 15k L2 ISEN2 R4 +12V 21 C12 + 68µF PHASE2 6 C11 0.01µF R12 100 C8 0.1µF UGATE2 28 LGATE2 IRF7907 R2 4.75k C6 10µF BOOT2 8.45k LGATE1 Q1 R1 10.2k 31 R3 1.8µH 3 10 18 C81 0.1µF UGATE3 PHASE3 L3 ISEN3 R41 8.2µH 2.8k R11 4.75k 22 LGATE3 R71 301k OCSET1 R72 301k R73 261k OCSET2 16 7 Q3 IRF7907 FB3 VOUT3 +5V, 2A + C13 330µF R51 24.3k V VCC_5V 12 R91 10k OCSET3 15 8 RST R61 4.53k RST V VCC_5V R9 10k 2 5 14 17 23 PGOOD PGOOD 11 EN1 EN2 EN3 PGND SGND FN6383 Rev 2.00 February 9, 2015 Page 5 of 20 ISL9440, ISL9440A, ISL9441 Absolute Maximum Ratings Thermal Information VCC_5V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V VCC_5V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V BOOT/UGATE to PHASE . . . . . . . . . . . . . -0.3V to VCC_5V + 0.3V PHASE1,2,3 and ISEN1, 2,3, to GND . . . . . . . . . . . . . . . . . . . . .-5V (<100ns, 10µJ)/-0.3V (DC) to +28V EN1,EN2, EN3, FB1, FB2, FB3, to GND . . -0.3V to VCC_5V + 0.3V LDOFB, OCSET1, OCSET2, OCSET3, LGATE1, LGATE2, LGATE3, to GND. . . -0.3V to VCC_5V + 0.3V PGOOD, RST, G4 to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250V Thermal Resistance (Typical) JA(oC/W) JC(oC/W) 32 Ld QFN Package (Note 4). . . . . . . . 31 3 Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Operating Temperature . . . . . . . . . . . . . . .-40°C to +85°C Maximum Storage Temperature. . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profilesee link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, TA = -40°C to +85°C (Note 8), Typical values are at TA = +25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 5.6 12.0 24.0 V 4.5 5.0 5.6 V 4.5 5.0 5.6 V 5.0 5.5 V VIN SUPPLY Input Voltage Range Input Voltage Range VIN = VCC_5V (Note 9) VCC_5V SUPPLY (Note 5) Operation Voltage Internal LDO Output Voltage VIN > 5.6V, IL = 60mA 4.5 Maximum Supply Current of Internal LDO VIN = 12V 60 mA VIN SUPPLY CURRENT Shutdown Current (Note 6) EN = EN2 = EN3 = 0, VIN =12V Operating Current (Note 7) 50 100 µA 3 5 mA REFERENCE SECTION Internal Reference Voltage Across specified temperature range Reference Voltage Accuracy Across specified temperature range 0.8 -1 V +1 % PWM CONTROLLER ERROR AMPLIFIERS DC Gain (Note 8) 88 dB Gain-BW Product (Note 8) 15 MHz Slew Rate (Note 8) 2.0 V/µs PWM REGULATOR Switching Frequency (ISL9440, ISL9441) 260 300 340 kHz Maximum Duty Cycle (ISL9440, ISL9441) 93 % Minimum Duty Cycle (ISL9440, ISL9441) 3 % Switching Frequency (ISL9440A) Maximum Duty Cycle (ISL9440A) FN6383 Rev 2.00 February 9, 2015 522 600 86 678 kHz % Page 6 of 20 ISL9440, ISL9440A, ISL9441 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, TA = -40°C to +85°C (Note 8), Typical values are at TA = +25°C, unless otherwise specified. (Continued) PARAMETER TEST CONDITIONS MIN Minimum Duty Cycle (ISL9440A) TYP 6 FB Bias Current (Note 8) Peak-to-Peak Saw-tooth Amplitude (Note 8) MAX UNITS % 50 nA VIN = 12V 1.6 V VIN = 5.5V 0.667 V 1 V Ramp Offset Soft-start Period 1.1 1.7 2.3 ms PWM GATE DRIVER CHANNEL 1, 2 (UGATE1, 2; LGATE 1, 2) (Note 8) Source Current 800 mA Sink Current 2000 mA Upper Drive Pull-Up VCC_5V = 5.0V 4 8 Upper Drive Pull-Down VCC_5V = 5.0V 1.6 3 Lower Drive Pull-Up VCC_5V = 5.0V 4 8 Lower Drive Pull-Down VCC_5V = 5.0V 0.9 2 Rise Time COUT = 1000pF 18 ns Fall Time COUT = 1000pF 18 ns 400 mA PWM GATE DRIVER CHANNEL 3 (UGATE3; LGATE 3) (Note 8) Sink/Source Current Upper Drive Pull-Up VCC_5V = 5.0V 8.0 12 Upper Drive Pull-Down VCC_5V = 5.0V 3.2 6.0 Lower Drive Pull-Up VCC_5V = 5.0V 8 12 Lower Drive Pull-Down VCC_5V = 5.0V 1.8 3.5 Rise Time COUT = 1000pF 18 ns Fall Time COUT = 1000pF 18 ns LOW DROP OUT CONTROLLER Drive Sink Current LDOFB = 0.76V 50 Amplifier Trans-conductance LDOFB Input Leakage Current (Note 8) mA 2 LDOFB = 0.8V A/V 50 nA 0.8 V ENABLE1, ENABLE2, ENABLE3 THRESHOLD Enable Pin Logic Input Low Enable Pin Logic Input High 2.0 V POWER GOOD MONITORS PGOOD Upper Threshold, PWM 1, 2 and 3 105.5 111 115.5 % PGOOD Lower Threshold, PWM 1, 2 and 3 87 91 96 % PGOOD for Linear Controller 70 75 80 % 0.4 V 1 µA PGOOD Low Level Voltage I_SINK = 4mA PGOOD Leakage Current PGOOD = 5V 0.025 PGOOD Rise Time RPULLUP = 10k to 3.3V 0.05 FN6383 Rev 2.00 February 9, 2015 µs Page 7 of 20 ISL9440, ISL9440A, ISL9441 Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. VIN = 5.6V to 24V, or VCC_5V = 5V ±10%, C_VCC_5V = 4.7µF, TA = -40°C to +85°C (Note 8), Typical values are at TA = +25°C, unless otherwise specified. (Continued) PARAMETER PGOOD Fall Time TEST CONDITIONS MIN RPULLUP = 10k to 3.3V TYP MAX 0.05 UNITS µs EARLY WARNING FUNCTIONS Undervoltage Lockout Rising (VCC_5V Pin) 4.25 4.45 4.50 V Undervoltage Lockout Falling (VCC_5V Pin) 3.95 4.20 4.40 V 5.75 5.90 V Early Warning Voltage Rising (VIN Pin; ISL9440, ISL9440A only) Early Warning Voltage Falling (VIN Pin; ISL9440, ISL9440A only) 5.30 5.55 V RST RST Voltage Low I_SINK = 4mA 0.4 V RST Leakage Current RST = 5V 0.025 1 µA RST Rise Time RPULLUP = 10k to 3.3V 0.05 µs RST Fall Time RPULLUP = 10k to 3.3V 0.05 µs PGOOD/RST TIMING RISING VIN/VOUT Rising Threshold to PGOOD High Rising 100 200 300 1.0 PGOOD Rising to RST Rising ms µs PGOOD/RST TIMING FALLING VIN/VOUT Falling Threshold to PGOOD Falling 40 70 100 µs PGOOD Falling to RST Falling 4.5 5.5 6.5 µs OVER VOLTAGE PROTECTION OV Trip Point 118 % 32 µA 15 µA OVER CURRENT PROTECTION Overcurrent Threshold (OCSET_) (Note 5) ROCSET = 55k Full Scale Input Current (ISEN_) (Note 5) Overcurrent Set Voltage (OCSET_) 1.70 1.75 1.80 V OVER-TEMPERATURE Over-Temperature Shutdown 150 °C Over-Temperature Hysteresis 20 °C NOTES: 5. In normal operation, where the device is supplied with voltage on the VIN pin, the VCC_5V pin provides a 5V output capable of 60mA (min). When the VCC_5V pin is used as a 5V supply input, the internal LDO regulator is disabled and the VIN input pin must be connected to the VCC_5V pin. (Refer to the Pin Descriptions section for more details.) 6. This is the total shutdown current with VIN = 5.6 and 24V. 7. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current. 8. Limits established by characterization and are not production tested. 9. Check Note 5 for VCC_5V and VIN configurations at 5V ±10% input applications. ISL9440, ISL9440A’s PGOOD signal will fall LOW when VIN pin voltage drops below 5.55V (TYP), which results from the early warning detection on VIN pin voltage. ISL9441 doesn’t have an early warning function, so when VIN pin voltage is below 5.55V, PGOOD will not be pulled LOW; ISL9441’s PGOOD only shows the output voltage regulation status. FN6383 Rev 2.00 February 9, 2015 Page 8 of 20 ISL9440, ISL9440A, ISL9441 Pin Descriptions BOOT3, BOOT2, BOOT1 (Pin 20, 26, 31) These pins are bootstrap pins to provide bias for high side driver. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. UGATE3, UGATE2, UGATE1 (Pin 21, 27, 30) These pins provide the gate drive for the upper MOSFETs. PHASE3, PHASE2, PHASE1 (Pin 19, 25, 32) VIN (Pin 4) Use this pin to power the device with an external supply voltage with a range of 5.6V to 24V. For 5V ±10% operation, connect this pin to VCC_5V. For ISL9440 and ISL9440A, the voltage on this pin is monitored for early warning function. If the voltage on this pin drop below 5.55V, the PGOOD will be pulled low. RST will be low after PGOOD toggles to low for 5.5µs (TYP). Refer to Figure 1 for detailed time sequence. These pins are connected to the junction of the upper MOSFET’s source, output filter inductor, and lower MOSFET’s drain. ISL9441 doesn’t have early warning functions, which means the VIN pin voltage is not monitored. LGATE3, LGATE2, LGATE1 (Pin 22, 28, 29) This pin is the output of the internal 5V linear regulator. This output supplies the bias for the IC, the low side gate drivers, and the external boot circuitry for the high side gate drivers. The IC may be powered directly from a single 5V (±10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VCC_5V pin must be always decoupled to power ground with a minimum of 4.7F ceramic capacitor, placed very close to the pin. These pins provide the gate drive for the lower MOSFETs. PGND (Pin 23) This pin provides the power ground connection for the lower gate drivers for all PWM1, PWM2 and PWM3. This pin should be connected to the sources of the lower MOSFETs and the (-) terminals of the external input capacitors. FB3, FB2, FB1, LDOFB (Pin 16, 13, 6, 10) These pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. They set the output voltage of the converter. In addition, the PGOOD circuit uses these inputs to monitor the output voltage status. ISEN3, ISEN2, ISEN1 (Pin 18, 24, 1) These pins are used to monitor the voltage drop across the lower MOSFET for current loop feedback and overcurrent protection. PGOOD (Pin 2) This is an open drain logic output used to indicate the status of the output voltages AND input voltage (voltage on VIN pin; early warning for ISL9440 and ISL9440A). This pin is pulled low when either of the three PWM outputs is not within 10% of the respective nominal voltage, or if the linear controller output is less than 75% of it’s nominal value, or VIN pin voltage drops below 5.55V. ISL9440 and ISL9440A’s PGOOD pin also indicates the VIN pin status for early warning function. If the voltage on VIN pin drops below 5.55V, this pin will be pulled low. VCC_5V (Pin 3) EN3, EN2, EN1 (Pin 17, 14, 5) These pins provide an enable/disable function for their respective PWM output. The output is enabled when this pin is floating or pulled HIGH, and disabled when the pin is pulled LOW. G4 (Pin 9) This pin is the open drain output of the linear regulator controller. OCSET3, OCSET2, OCSET1 (Pin 15, 12, 7) A resistor from this pin to ground sets the overcurrent threshold for the respective PWM. RST (Pin 8) Reset pulse output. This pin outputs a logic LOW signal after PGOOD toggles to low for 5.5µs (TYP). It can be used to reset system. Refer to Figure 1 for detailed time sequence of ISL9440 and ISL9440A with early warning function. ISL9441 doesn’t have early warning functions, which means the VIN pin voltage is not monitored. But RST still output LOW signal following PGOOD LOW. SGND (Pin 11) This is the small-signal ground, common to all 4 controllers, and are suggested to be routed separately from the high current ground (PGND). In case of one whole solid ground and no noisy current going through around chip, SGND and PGND can be tied to the same ground copper plane. All voltage levels are measured with respect to this pin. A small ceramic capacitor should be connected right next to this pin for noise decoupling. FN6383 Rev 2.00 February 9, 2015 Page 9 of 20 ISL9440, ISL9440A, ISL9441 8 VIN = 5.5V FALLING/ VOUT 1-4 OUT OF REGULATION 7 VOLTAGE (V) 6 VIN/VOUT VVININ==5.5V 5.5VRISING/ RISING/ VVOUT 1-4 IN REGULATION OUT 1-4 IN REGULATION 5 TYP = 200ms PGOOD 4 RST 3 2 MAX = 100µs 2.4V MAX = 2µs 1 0 0.4V 0 5 10 15 20 25 MAX = 6.5µs TIME (NOT TO SCALE) FIGURE 1. PGOOD AND RST TIMING Typical Performance Curves (Oscilloscope Plots are Taken Using the ISL9440EVAL1Z Evaluation Board, VIN = 12V Unless Otherwise Noted.) 2.55 95 2.53 90 2.52 85 EFFICIENCY (%) OUTPUT VOLTAGE (V) 2.54 2.51 2.50 2.49 2.48 2.47 80 75 70 65 2.46 2.45 0.0 1.0 2.0 3.0 4.0 5.0 6.0 60 0.0 7.0 1.0 2.0 LOAD CURRENT (A) 3.0 4.0 5.0 6.0 7.0 LOAD CURRENT (A) FIGURE 2. PWM1 LOAD REGULATION FIGURE 3. PWM1 EFFICIENCY vs LOAD (VO = 2.5V), VIN = 12V, 1 DUAL SO-8 MOSFET (IRF7907) FOR UPPER AND LOWER MOSFETS 1.55 90 85 1.53 1.52 EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.54 1.51 1.50 1.49 1.48 1.47 80 75 70 65 1.46 1.45 0.0 1.0 2.0 3.0 4.0 5.0 6.0 LOAD CURRENT (A) FIGURE 4. PWM2 LOAD REGULATION FN6383 Rev 2.00 February 9, 2015 7.0 60 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 LOAD CURRENT (A) FIGURE 5. PWM2 EFFICIENCY vs LOAD (VO = 1.5V), VIN = 12V, 1 DUAL SO-8 MOSFET (IRF7907) FOR UPPER AND LOWER MOSFETS Page 10 of 20 ISL9440, ISL9440A, ISL9441 Typical Performance Curves (Continued) 5.10 100 5.10 95 5.09 90 5.09 EFFICIENCY (%) OUTPUT VOLTAGE (V) (Oscilloscope Plots are Taken Using the ISL9440EVAL1Z Evaluation Board, VIN = 12V Unless Otherwise Noted.) 5.08 5.08 5.07 5.07 85 80 75 70 5.06 65 5.06 5.05 0.0 1.0 2.0 3.0 60 0. 0 4.0 1.0 2.0 3.0 4. 0 LOAD CURRENT (A) LOAD CURRENT (A) FIGURE 6. PWM3 LOAD REGULATION FIGURE 7. PWM3 EFFICIENCY vs LOAD (VO = 5V), VIN = 12V, 1 DUAL SO-8 MOSFET (IRF7907) FOR UPPER AND LOWER MOSFETS VOUT1 50mV/DIV, AC COUPLED VOUT3 1V/DIV VOUT2 50mV/DIV, AC COUPLED VOUT4 (LDO) 1V/DIV VOUT3 50mV/DIV, AC COUPLED VOUT1 1V/DIV VOUT2 1V/DIV VOUT4 50mV/DIV, AC COUPLED 5µs/DIV 0.2ms/DIV FIGURE 8. PWM SOFT-START WAVEFORMS FIGURE 9. OUTPUT RIPPLE UNDER MAXIMUM LOAD (IO1 = IO1 = 6A, IO3 = 2A, IO4 = 0.5A) VIN, 1V/DIV, CH1 VIN, 1V/DIV, CH1 RST, 5V/DIV, CH3 CH1 CH3 RST, 5V/DIV, CH3 CH3 PGOOD, 5V/DIV, CH4 PGOOD, 5V/DIV, CH4 CH4 CH1 CH4 100µs/DIV FIGURE 10. VIN FALLING TO PGOOD FALLING DELAY TIME FN6383 Rev 2.00 February 9, 2015 10µs/DIV FIGURE 11. PGOOD FALLING TO RST FALLING Page 11 of 20 ISL9440, ISL9440A, ISL9441 Typical Performance Curves (Continued) (Oscilloscope Plots are Taken Using the ISL9440EVAL1Z Evaluation Board, VIN = 12V Unless Otherwise Noted.) VOUT1, 100mV/DIV, 0A to 6A, 1.6A/µs VIN, 1V/DIV, CH1 VOUT2, 100mV/DIV, 0A to 6A, 1.6A/µs RST, 1V/DIV, CH3 CH3 VOUT3, 100mV/DIV, 0A to 2A, 1A/µs PGOOD, 5V/DIV, CH4 VOUT4 (LDO), 100mV/DIV, 0A to 0.5A, 1A/µs CH4 CH1 500ns/DIV FIGURE 12. PGOOD RISING TO RST RISING 500µs/DIV FIGURE 13. OUTPUT RIPPLE UNDER TRANSIENT LOAD PWM1, 5V/DIV Vo1, 1V/DIV PWM2, 5V/DIV Vo2, 1V/DIV Vo3, 1V/DIV 5ms/DIV FIGURE 14. THREE CHANNEL HARD-SHORT OCP AT THE SAME TIME FN6383 Rev 2.00 February 9, 2015 PWM3, 5V/DIV 1µs/DIV FIGURE 15. PHASE NODE PWM WAVEFORMS, VIN = 24V Page 12 of 20 ISL9440, ISL9440A, ISL9441 Functional Description General Description The ISL9440, ISL9440A and ISL9441 are integrate control circuits for three synchronous buck converters and one linear controller. The three synchronous bucks operate out of phase to substantially reduce the input ripple and thus reduce the input filter requirements. The chip has 3 control lines (EN1, EN2 and EN3), which provide independent control for each of the synchronous buck outputs. The buck PWM controllers employ free-running frequency of 300kHz (ISL9440 and ISL9441) and 600kHz (ISL9440A). The current mode control scheme with an input voltage feed-forward ramp input to the modulator provides an excellent rejection of input voltage variations and provides simplified loop compensations. The linear controller can drive either a PNP or PFET to provide ultra low-dropout regulation with programmable voltages. Internal 5V Linear Regulator (VCC_5V) All ISL9440, ISL9440A and ISL9441 functions are internally powered from an on-chip, low dropout 5V regulator. The maximum regulator input voltage is 24V. Bypass the regulator’s output (VCC_5V) with a 4.7µF capacitor to ground. The dropout voltage for this LDO is typically 600mV, so when VIN is greater than 5.6V, VCC_5V is typically 5V. The ISL9440, ISL9440A and ISL9441 also employ an undervoltage lockout circuit that disables both regulators when VCC_5V falls below 4.4V. The internal LDO can source over 60mA to supply the IC, power the low side gate drivers and charge the external boot capacitor. When driving large FETs especially at 300kHz (ISL9440, ISL9441)/600kHz (ISL9440A) frequency, little or no regulator current may be available for external loads. For example, a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA). Also, at higher input voltages with larger FETs, the power dissipation across the internal 5V will increase. Excessive dissipation across this regulator must be avoided to prevent junction temperature rise. Larger FETs can be used with 5V ±10% input applications. The thermal overload protection circuit will be triggered, if the VCC_5V output is short-circuit. Connect VCC_5V to VIN for 5V ±10% input applications. Digital Enable Signals The typical applications for the ISL9440, ISL9440A and ISL9441 are using digital sequencing controllers for the power rails. Using a digital enable rather than an analog soft-start provides a well controlled method for sequencing up and down on the power rails. Soft-Start Operation The ISL9440, ISL9440A and ISL9441 have a fixed soft-start time, 1.7ms (TYP). PGOOD will not toggle to high until FN6383 Rev 2.00 February 9, 2015 soft-start is done and all the four outputs are up and in regulations. Output Voltage Programming The ISL9440, ISL9440A and ISL9441 use a precision internal reference voltage to set the output voltage. Based on this internal reference, the output voltage can thus be set from 0.8V up to a level determined by the input voltage, the maximum duty cycle, and the conversion efficiency of the circuit. A resistive divider from the output to ground sets the output voltage of either PWM channel. The center point of the divider shall be connected to FBx pin. The output voltage value is determined by Equation 1. R1 + R2 V OUTx = 0.8V ---------------------- R2 (EQ. 1) where R1 is the top resistor of the feedback divider network and R2 is the resistor connected from FBx to ground. Out-of-Phase Operation To reduce input ripple current, Channel 1 and Channel 2 operate 180° out-of-phase, Channel 3 keeps 0 phase degree with Channel 1. Channel 1 and Channel 2 typically output higher load compared to Channel 3 because of their stronger drivers. This reduces the input capacitor ripple current requirements, reduces power supply-induced noise, and improves EMI. This effectively helps to lower component cost, save board space and reduce EMI. Triple PWMs typically operate in-phase and turn on both upper FETs at the same time. The input capacitor must then support the instantaneous current requirements of the three switching regulators simultaneously, resulting in increased ripple voltage and current. The higher RMS ripple current lowers the efficiency due to the power loss associated with the ESR of the input capacitor. This typically requires more low-ESR capacitors in parallel to minimize the input voltage ripple and ESR-related losses, or to meet the required ripple current rating. With synchronized out-of-phase operation, the high-side MOSFETs turn on 180° out-of-phase. The instantaneous input current peaks of both regulators no longer overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the required input capacitor ripple current rating, allowing fewer or less expensive capacitors, and reducing the shielding requirements for EMI. The typical operating curves show the synchronized 180° out-of-phase operation. Input Voltage Range The ISL9440, ISL9440A and ISL9441 are designed to operate from input supplies ranging from 4.5V to 24V. For 5V ±10% input applications, ISL9441 is suggested. The reason is that VIN and VCC_5V Pin should be tied together for this input application. The early warning function will pull PGOOD and RST low for ISL9440 and ISL9440A. ISL9441 has not been implemented with early warning function. Page 13 of 20 ISL9440, ISL9440A, ISL9441 The input voltage range can be effectively limited by the available maximum duty cycle (DMAX = 93% for ISL9440 and ISL9441, DMAX = 86% for ISL9440A). V OUT + V d1 V IN min = -------------------------------- + V d2 – V d1 0.93 (EQ. 2) BOOT where, Vd1 = Sum of the parasitic voltage drops in the inductor discharge path, including the lower FET, inductor and PC board. Vd2 = Sum of the voltage drops in the charging path, including the upper FET, inductor and PC board resistances. UGATE PHASE ISL9440, ISL9440A, ISL9441 The maximum input voltage and minimum output voltage is limited by the minimum on-time (tON(min)). V OUT V IN max ---------------------------------------------------t ON min 300kHz VIN VCC_5V (EQ. 3) where, tON(min) = 30ns Gate Control Logic The gate control logic translates generated PWM signals into gate drive signals providing amplification, level shifting and shootthrough protection. The gate drivers have some circuitry that helps optimize the IC performance over a wide range of operational conditions. As MOSFET switching times can vary dramatically from type to type and with input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower MOSFETs. Shootthrough control logic provides a 20ns dead-time to ensure that both the upper and lower MOSFETs will not turn on simultaneously and cause a shoot-through condition. Gate Drivers The low-side gate driver is supplied from VCC_5V and provides a peak sink current of 2A/2A/200mA and source current of 800mA/800mA/400mA for Channels 1/2/3 respectively. The high-side gate driver is also capable of delivering the same current as those in low-side gate driver. Gate-drive voltages for the upper N-Channel MOSFET are generated by the flying capacitor boot circuit. A boot capacitor connected from the BOOT pin to the PHASE node provides power to the high side MOSFET driver. To limit the peak current in the IC, an external resistor may be placed between the UGATE pin and the gate of the external MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance. FIGURE 16. At start-up, the low-side MOSFET turns on and forces PHASE to ground in order to charge the BOOT capacitor to 5V. After the low-side MOSFET turns off, the high-side MOSFET is turned on by closing an internal switch between BOOT and UGATE. This provides the necessary gate-to-source voltage to turn on the upper MOSFET, an action that boosts the 5V gate drive signal above VIN. The current required to drive the upper MOSFET is drawn from the internal 5V regulator. Adaptive Dead Time The ISL9440, ISL9440A and ISL9441 incorporate an adaptive dead time algorithm on the synchronous buck PWM controllers that optimizes operation with varying MOSFET conditions. This algorithm provides an approximately 20ns of dead time between switching the upper and lower MOSFET’s. This dead time is adaptive and allows operation with different MOSFET’s without having to externally adjust the dead time using a resistor or capacitor. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive dead time circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. Internal Bootstrap Diode The ISL9440, ISL9440A and ISL9441 have integrated bootstrap diodes to help reduce total cost and reduce layout complexity. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above the maximum battery voltage plus 5V. The bootstrap capacitor can be chosen from Equation 4. Q GATE C BOOT -----------------------V BOOT (EQ. 4) Where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. FN6383 Rev 2.00 February 9, 2015 Page 14 of 20 ISL9440, ISL9440A, ISL9441 As an example, suppose an upper MOSFET has a gate charge (QGATE) of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125µF is required. The next larger standard value capacitance is 0.22µF. A good quality ceramic capacitor is recommended. Overvoltage Protection The converter output is monitored and protected against overload, short circuit and undervoltage conditions. A sustained overload on the output sets the PGOOD low and initiates hiccup mode. All switching controllers within the ISL9440, ISL9440A and ISL9441 have fixed overvoltage set points. The overvoltage set point is set at 118% of the output voltage set by the feedback resistors. In the case of an overvoltage event, the IC will attempt to bring the output voltage back into regulation by keeping the upper MOSFET turned off and modulating the lower MOSFET for 2 consecutive PWM cycles. If the overvoltage condition has not been corrected in 2 cycles, the ISL9440, ISL9440A and ISL9441 will turn on the lower MOSFET until the overvoltage has been cleared, or the power path is interrupted by opening a fuse. Undervoltage Lockout Over-Temperature Protection The ISL9440, ISL9440A and ISL9441 include UVLO protection that will keep the devices in a reset condition until a proper operating voltage is applied and that will also shut down the ISL9440, ISL9440A and ISL9441 if the operating voltage drops below a pre-defined value. All controllers are disabled when UVLO is asserted. When UVLO is asserted, PGOOD will be valid and de-asserted. The IC incorporates an over-temperature protection circuit that shuts the IC down when a die temperature of +150°C is reached. Normal operation resumes when the die temperatures drops below +130°C through the initiation of a full soft-start cycle. Protection Circuits Overcurrent Protection All the PWM controllers use the lower MOSFET’s on-resistance, rDS(ON) , to monitor the current in the converter. The sensed voltage drop is compared with a threshold set by a resistor connected from the OCSETx pin to ground. 7 R CS R OCSET = ------------------------------------------ I OC r DS ON (EQ. 5) where, IOC is the desired overcurrent protection threshold, and RCS is a value of the current sense resistor connected to the ISENx pin. If an overcurrent is detected for 2 consecutive clock cycles then the IC enters a hiccup mode by turning off the gate drivers and entering into soft-start. The IC will cycle 4 times through soft-start before trying to restart. The IC will continue to cycle through soft-start until the overcurrent condition is removed. Hiccup mode is active during soft-start so care must be taken to ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. Because of the nature of this current sensing technique, and to accommodate a wide range of rDS(ON) variations, the value of the overcurrent threshold should represent an overload current about 150% to 180% of the maximum operating current. If more accurate current protection is desired, place a current sense resistor in series with the lower MOSFET source. Feedback Loop Compensation To reduce the number of external components and to simplify the process of determining compensation components, all PWM controllers have internally compensated error amplifiers. To make internal compensation possible several design measures were taken. First, the ramp signal applied to the PWM comparator is proportional to the input voltage provided via the VIN pin. This keeps the modulator gain constant with variation in the input voltage. Second, the load current proportional signal is derived from the voltage drop across the lower MOSFET during the PWM time interval and is subtracted from the amplified error signal on the comparator input. This creates an internal current control loop. The resistor connected to the ISEN pin sets the gain in the current feedback loop. The following expression estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the MOSFET’s rDS(ON). I MAX r DS ON R CS ----------------------------------------------15A (EQ. 6) Choosing RCS to provide 15µA of current to the current sample and hold circuitry is recommended but values down to 2µA and up to 100µA can be used. The higher sampling current will help to stabilize the loop. Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency determined by the load. 1 F PO = --------------------------------2 R O C O (EQ. 7) where RO is load resistance and CO is load capacitance. For this type of modulator, a Type 2 compensation circuit is usually sufficient. FN6383 Rev 2.00 February 9, 2015 Page 15 of 20 ISL9440, ISL9440A, ISL9441 Figure 17 shows a Type 2 amplifier and its response along with the responses of the current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies in between the zero and the pole. 1 F Z = ------------------------------- = 6kHz 2 R 2 C 1 (EQ. 8) 1 F P = ------------------------------- = 600kHz 2 R 1 C 2 (EQ. 9) C2 R2 C1 CONVERTER EA TYPE 2 EA GM = 17.5dB GEA = 18dB FZ FP FC FIGURE 17. FEEDBACK LOOP COMPENSATION The zero frequency, the amplifier high-frequency gain, and the modulator gain are chosen to satisfy most typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase ‘boost’. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within the 1.2kHz to 30kHz range gives some additional phase ‘boost’. Some phase boost can also be achieved by connecting capacitor CZ in parallel with the upper resistor R1 of the divider that sets the output voltage value. Please refer to “Output Inductor Selection” on page 18 and “Input Capacitor Selection” on page 18 for further details. Linear Regulator The linear regulator controller is a trans-conductance amplifier with a nominal gain of 2A/V. The N-channel MOSFET output device can sink a minimum of 50mA. The reference voltage is 0.8V. With zero volts differential at it’s input, the controller sinks 21mA of current. An external PNP transistor or PFET pass element can be used. The dominant pole for the loop can be FN6383 Rev 2.00 February 9, 2015 60 ERROR AMPLIFIER SINK CURRENT (mA) FPO Under no-load conditions, leakage currents from the pass transistors supply the output capacitors, even when the transistor is off. Generally this is not a problem since the feedback resistor drains the excess charge. However, charge may build up on the output capacitor making VLDO rise above its set point. Care must be taken to insure that the feedback resistor’s current exceeds the pass transistors leakage current over the entire temperature range. The linear regulator output can be supplied by the output of one of the PWMs. When using a PFET, the output of the linear regulator will track the PWM supply after the PWM output rises to a voltage greater than the threshold of the PFET pass device. The voltage differential between the PWM and the linear output will be the load current times the rDS(ON). R1 MODULATOR placed at the base of the PNP (or gate of the PFET), as a capacitor from emitter to base (source to gate of a PFET). Better load transient response is achieved however, if the dominant pole is placed at the output, with a capacitor to ground at the output of the regulator. 50 40 30 20 10 0 0.79 0.8 0.82 0.83 0.81 FEEDBACK VOLTAGE (V) 0.84 0.85 FIGURE 18. LINEAR CONTROLLER GAIN Base-Drive Noise Reduction The high-impedance base driver is susceptible to system noise, especially when the linear regulator is lightly loaded. Capacitively coupled switching noise or inductively coupled EMI onto the base drive causes fluctuations in the base current, which appear as noise on the linear regulator’s output. Keep the base drive traces away from the step-down converter, and as short as possible, to minimize noise coupling. A resistor in series with the gate drivers reduces the switching noise generated by PWM. Additionally, a bypass capacitor may be placed across the base-to-emitter resistor. This bypass capacitor, in addition to the transistor’s input capacitor, could bring in a second pole that will de-stabilize the linear regulator. Therefore, the stability requirements determine the maximum base-to-emitter capacitance. Layout Guidelines Careful attention to layout requirements is necessary for successful implementation of an ISL9440, ISL9440A and Page 16 of 20 ISL9440, ISL9440A, ISL9441 ISL9441 based DC/DC converter. The ISL9440, ISL9440A and ISL9441 switch at a very high frequency and therefore the switching times are very short. At these switching frequencies, even the shortest trace has significant impedance. Also, the peak gate drive current rises significantly in extremely short time. Transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, generate EMI, increase device overvoltage stress and ringing. Careful component selection and proper PC board layout minimizes the magnitude of these voltage spikes. There are three sets of critical components in a DC/DC converter using the ISL9440, ISL9440A and ISL9441: The controller, the switching power components and the small signal components. The switching power components are the most critical from a layout point of view because they switch a large amount of energy so they tend to generate a large amount of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. A multi-layer printed circuit board is recommended. Layout Considerations 1. The Input capacitors, Upper FET, Lower FET, Inductor and Output capacitor should be placed first. Isolate these power components on the topside of the board with their ground terminals adjacent to one another. Place the input high frequency decoupling ceramic capacitor very close to the MOSFETs. 2. Use separate ground planes for power ground and small signal ground. Connect the SGND and PGND together close to the IC. Do not connect them together anywhere else. 3. The loop formed by Input capacitor, the top FET and the bottom FET must be kept as small as possible. 4. Ensure the current paths from the input capacitor to the MOSFET, to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. 5. Place The PWM controller IC close to lower FET. The LGATE connection should be short and wide. The IC can be best placed over a quiet ground area. Avoid switching ground loop current in this area. 6. Place VCC_5V bypass capacitor very close to VCC_5V pin of the IC and connect its ground to the PGND plane. 7. Place the gate drive components BOOT diode and BOOT capacitors together near controller IC PHASE node. Since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. Route all high speed switching nodes away from the control circuitry. 11. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. All small signal grounding paths including feedback resistors, current limit setting resistors and ENx pull-down resistors should be connected to this SGND plane. 12. Ensure the feedback connection to the output capacitor is short and direct. Component Selection Guidelines MOSFET Considerations The logic level MOSFETs are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. Two N-Channel MOSFETs are used in each of the synchronous-rectified buck converters for the 3 PWM outputs. These MOSFETs should be selected based upon rDS(ON), gate supply requirements, and thermal management considerations. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty cycle (see the following equations). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations assume linear voltagecurrent transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. 2 I O r DS ON V OUT I O V IN t SW F SW P UPPER = --------------------------------------------------------------- + -----------------------------------------------------------V IN 2 (EQ. 10) 2 I O r DS ON V IN – V OUT P LOWER = ------------------------------------------------------------------------------V IN (EQ. 11) A large gate-charge increases the switching time, tSW, which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. 8. The output capacitors should be placed as close to the load as possible. Use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. Use copper filled polygons or wide but short trace to connect the junction of upper FET, Lower FET and output inductor. Also keep the PHASE node connection to the IC short. Do not unnecessarily oversize the copper islands for FN6383 Rev 2.00 February 9, 2015 Page 17 of 20 ISL9440, ISL9440A, ISL9441 Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. Selection of output capacitors is also dependent on the output inductor, so some inductor analysis is required to select the output capacitors. One of the parameters limiting the converter’s response to a load transient is the time required for the inductor current to slew to it’s new level. The ISL9440, ISL9440A and ISL9441 will provide either 0% or maximum duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the load current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. Also, if the load transient rise time is slower than the inductor response time, as in a hard drive or CD drive, it reduces the requirement on the output capacitor. The maximum capacitor value required to provide the full, rising step, transient load current during the response time of the inductor is: 2 L O I TRAN C OUT = ----------------------------------------------------------2 V IN – V O DV OUT (EQ. 12) where, COUT is the output capacitor(s) required, LO is the output inductor, ITRAN is the transient load current step, VIN is the input voltage, VO is output voltage, and DVOUT is the drop in output voltage allowed during the load transient. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Equivalent Series Resistance) and voltage rating requirements as well as actual capacitance requirements. The output voltage ripple is due to the inductor ripple current and the ESR of the output capacitors as defined by: V RIPPLE = I L ESR (EQ. 13) where, IL is calculated in the “Output Inductor Selection” on page 18. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load circuitry for specific decoupling requirements. Use only specialized low-ESR capacitors intended for switchingregulator applications at 300kHz (ISL9440/ISL9441)/600kHz (ISL9440A) for the bulk capacitors. In most cases, multiple FN6383 Rev 2.00 February 9, 2015 small-case electrolytic capacitors perform better than a single large-case capacitor. The stability requirement on the selection of the output capacitor is that the ‘ESR zero’ (f Z) be between 1.2kHz and 30kHz. This range is set by an internal, single compensation zero at 6kHz. The ESR zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. Therefore: 1 C OUT = ------------------------------------2 ESR f Z (EQ. 14) In conclusion, the output capacitors must meet three criteria: 1. They must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. The ESR must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. The ESR zero should be placed, in a rather large range, to provide additional phase margin. The recommended output capacitor value for the ISL9440, ISL9440A and ISL9441 is between 150F to 680F, to meet stability criteria with external compensation. Use of aluminum electrolytic (POSCAP) or tantalum type capacitors is recommended. Use of low ESR ceramic capacitors is possible but would take more rigorous loop analysis to ensure stability. Output Inductor Selection The PWM converters require output inductors. The output inductor is selected to meet the output voltage ripple requirements. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current and output capacitor(s) ESR. The ripple voltage expression is given in the capacitor selection section and the ripple current is approximated by Equation 15: V IN – V OUT V OUT I L = --------------------------------------------------------- f S L V IN (EQ. 15) For the ISL9440, ISL9440A and ISL9441, inductor values between 1.2µH to 10µH are recommended when using the Typical Application Schematic. Other values can be used but a thorough stability study should be done. A smaller volume cap in combination with big inductor will be more prone to stability issues. One way to get more phase margin is to add a small cap (typically 1nF to 10nF) in parallel with the upper resistor of the voltage sense resistor divider. For example, in ISL9440, ISL9440A Application Schematic, the 5V output has a 15µH inductor with which the system phase margin is less than 45°. An resistor and capacitor are added with the upper resistor of the divider to get more phase margin. Input Capacitor Selection The important parameters for the bulk input capacitor(s) are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS Page 18 of 20 ISL9440, ISL9440A, ISL9441 I RMS = 2 2 I RMS1 + I RMS2 (EQ. 16) where, I RMSx = 2 DC – DC I O (EQ. 17) 5.0 4.5 4.0 INPUT RMS CURRENT current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. The AC RMS Input current varies with the load. The total RMS current supplied by the input capacitance is: IN PHASE 3.5 3.0 2.5 OUT OF PHASE 2.0 1.5 DC is duty cycle of the respective PWM. Depending on the specifics of the input power and its impedance, most (or all) of this current is supplied by the input capacitor(s). Figure 19 shows the advantage of having the PWM converters operating out of phase. If the converters were operating in phase, the combined RMS current would be the algebraic sum, which is a much larger value as shown. The combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is significantly less than the combined in-phase current. 5V 3.3V 1.0 0.5 0 0 1 2 3 3.3V AND 5V LOAD CURRENT 4 5 FIGURE 19. INPUT RMS CURRENT vs LOAD Use a mix of input bypass capacitors to control the voltage ripple across the MOSFETs. Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For board designs that allow through-hole components, the Sanyo OS-CON® series offer low ESR and good temperature performance. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX is surge current tested. © Copyright Intersil Americas LLC 2007-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6383 Rev 2.00 February 9, 2015 Page 19 of 20 ISL9440, ISL9440A, ISL9441 Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 5/10 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .30 ± 0 . 15 17 (4X) 8 0.15 9 16 TOP VIEW 0.10 M C A B + 0.07 32X 0.40 ± 0.10 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN6383 Rev 2.00 February 9, 2015 Page 20 of 20