64M DDR SDRAM K4D64163HF 64Mbit DDR SDRAM 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM Revision 1.1 August 2002 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF Revision History Revision 1.1 (August 6, 2002) • Typo corrected Revision 1.0 (June 17, 2002) • Defined DC spec Revision 0.1 (May 20, 2002) - Target Spec • Typo corrected Revision 0.0 (April 30, 2002) - Target Spec • Defined Target Specification - 2 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 3.3V + 5% power supply for device operation • 2 DQS’s ( 1DQS / Byte ) • 2.5V + 5% power supply for I/O interface • Data I/O transactions on both edges of Data strobe • SSTL_2 compatible inputs/outputs • DLL aligns DQ and DQS transitions with Clock transition • 4 banks operation • Edge aligned data & data strobe output • MRS cycle with address key programs • Center aligned data & data strobe input -. Read latency 3 (clock) • DM for write masking only -. Burst length (2, 4 and 8) • Auto & Self refresh -. Burst type (sequential & interleave) • 64ms refresh period (4K cycle) • All inputs except data & DM are sampled at the positive going edge of the system clock • 66pin TSOP-II • Maximum clock frequency up to 300MHz • Differential clock input • Maximum data rate up to 600Mbps/pin • No Wrtie-Interrupted by Read Function ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D64163HF-TC33 300MHz 600Mbps/pin K4D64163HF-TC36 275MHz 550Mbps/pin K4D64163HF-TC40 250MHz 500Mbps/pin K4D64163HF-TC50 200MHz 400Mbps/pin K4D64163HF-TC60 166MHz 333Mbps/pin Interface Package SSTL_2 66 pin TSOP-II GENERAL DESCRIPTION FOR 1M x 16Bit x 4 Bank DDR SDRAM The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 3 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF PIN CONFIGURATION (Top View) VDD 1 66 VSS DQ0 2 65 DQ15 VDDQ 3 64 VSSQ DQ1 4 63 DQ14 DQ2 5 62 DQ13 VSSQ 6 61 VDDQ DQ3 7 60 DQ12 DQ4 8 59 DQ11 VDDQ 9 58 VSSQ DQ5 10 57 DQ10 DQ6 11 56 DQ9 VSSQ 12 55 VDDQ DQ7 13 54 DQ8 NC 14 53 NC VDDQ 15 52 VSSQ LDQS 16 51 UDQS NC 17 50 NC VDD 18 49 VREF NC 19 48 VSS LDM 20 47 UDM WE 21 46 CK CAS 22 45 CK RAS 23 44 CKE CS 24 43 NC NC 25 42 NC BA0 26 41 A11 BA1 27 40 A9 AP/A10 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 VDD 33 34 VSS 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm Pin Pitch) PIN DESCRIPTION CK,CK Differential Clock Input BA0, BA1 Bank Select Address CKE Clock Enable A0 ~A11 Address Input CS Chip Select DQ0 ~ DQ15 Data Input/Output RAS Row Address Strobe VDD Power CAS Column Address Strobe VSS Ground WE Write Enable VDDQ Power for DQ’s LDQS,UDQS Data Strobe VSSQ Ground for DQ’s LDM,UDM Data Mask NC No Connection - 4 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. Input/Output Data Strobe : Output with read data, input with write data. Edgealigned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Input/Output Data inputs/Outputs are multiplexed on the same pins. BA0, BA1 Input Selects which bank is to be active. A0 ~ A 11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA 11, Column addresses : CA0 ~ CA7. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. No connection/ Reserved for future use This pin is recommended to be left "No connection" on the device CK, CK*1 LDQS,(U)DQS LDM,UDM DQ0 ~ DQ15 NC/RFU *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. - 5 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF BLOCK DIAGRAM (1Mbit x 16I/O x 4 Bank) 16 Intput Buffer I/O Control CK, CK Data Input Register Serial to parallel Bank Select LWE LDMi 1Mx16 16 Output Buffer 1Mx16 32 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 1Mx16 x16 DQi 1Mx16 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe Gen. Programming Register DLL LCKE LRAS LCBR Data Strobe LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 6 - LDM UDM Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ precharge ALL Banks EMRS MRS DLL Reset 1st Auto Refresh precharge ALL Banks ~ tRP tRFC tRFC 200 Clock min. Inputs must be stable for 200us - 7 - 2nd Auto Refresh ~ ~ 2 Clock min. 2 Clock min. Mode Register Set Any Command ~ 2 Clock min. ~ ~ tRP Command ~ CK,CK Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A 7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA 0 RFU 0 A11 A10 A9 RFU DLL A8 A8 A7 DLL TM A6 A5 A3 CAS Latency A2 BT A1 A0 Burst Length Address Bus Mode Register Burst Type Test Mode DLL Reset A4 A7 mode A3 Type 0 No 0 Normal 0 Sequential 1 Yes 1 Test 1 Interleave Burst Length CAS Latency BA0 An ~ A0 A6 A5 A4 Latency 0 MRS 0 0 0 Reserved 1 EMRS 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved * RFU(Reserved for future use) should stay "0" during MRS cycle. A2 A1 A0 0 0 0 Burst Type Sequential Interleave 0 Reserve Reserve 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS NOP Any Command NOP NOP tMRD=2 tCK tRP *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. - 8 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA 1 BA0 RFU 1 BA0 A11 A10 A9 A8 A7 RFU A6 A5 A4 D.I.C An ~ A0 A6 A1 0 MRS 0 1 1 EMRS 1 1 A3 A2 RFU A1 A0 D.I.C DLL Address Bus Extended Mode Register A0 DLL Enable Weak 0 Enable Matched 1 Disable Output Driver Impedence Control *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. - 9 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS=0V, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage VDD 3.135 3.3 3.465 V 1 Output Supply voltage VDDQ 2.375 2.50 2.625 V 1 Reference voltage VREF 0.49*V DDQ - 0.51*VDDQ V 2 Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V 3 Input logic high voltage VIH(DC) VREF+0.15 - VDDQ+0.30 V 4 Input logic low voltage VIL(DC) -0.30 - VREF -0.15 V 5 Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Note : 1. Under all conditions VDDQ must be less than or equal to V DD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. - 10 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) Version Parameter Symbol Test Condition Unit Note -33 -36 -40 -50 -60 210 200 190 170 160 Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) Precharge Standby Current in Non Power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 110 105 95 80 70 mA Active Standby Current power-down mode ICC3P CKE ≤ VIL(max), tCC= tCC(min) 110 105 95 80 70 mA Active Standby Current in in Non Power-down mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 160 150 140 120 100 mA Operating Current ( Burst Mode) ICC4 tRC ≥ tRFC(min) tRC ≥ tRFC(min) Page Burst, All Banks activated. 390 370 350 320 300 mA Refresh Current ICC5 tRC ≥ tRFC(min) 210 200 190 180 170 mA Self Refresh Current ICC6 CKE ≤ 0.2V mA 5 1 mA 2 2 mA Note : 1. Measured with outputs open. 2. Refresh period is 64ms. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*V DDQ-0.2 - 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF AC OPERATING TEST CONDITIONS (VDD=3.3V±5%, TA= 0 to 65°C) Parameter Value Unit Input reference voltage for CK(for single ended) 0.50*VDDQ V CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns VREF+0.35/V REF-0.35 V VREF V Vtt V Input Levels(VIH/V IL) Input timing measurement reference level Output timing measurement reference level Output load condition Note See Fig.1 Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω VREF =0.5*VDDQ CLOAD=30pF (Fig. 1) Output Load Circuit CAPACITANCE (VDD=3.3V, TA= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK ) CIN1 1.0 5.0 pF Input capacitance(A0~A11, BA0~BA1) CIN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ31) COUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) CIN4 1.0 6.5 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and V SS CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All V SSQ pins are connected in chip. - 12 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF C CHARACTERISTICS Symbol Parameter K cycle time CL=3 K high level width K low level width QS out access time from CK utput access time from CK ata strobe edge to Dout edge ead preamble ead postamble K to valid DQS-in QS-In setup time QS-in hold time QS write postamble QS-In high level width QS-In low level width ddress and Control input setup ddress and Control input hold Q and DM setup time to DQS Q and DM hold time to DQS tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH -33 Min Min -40 Max Min -50 Max Min -60 Max Min Max Unit Note 3.3 4.0 3.6 6 4.0 7 5.0 10 6.0 10 ns 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.75 0.75 ns -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.7 0.7 -0.75 0.75 ns - 0.4 - 0.4 - 0.4 - 0.45 - 0.5 ns 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.8 1.25 0.85 1.15 0.85 1.15 0.8 1.2 0.75 1.25 tCK 0 - 0 - 0 - 0 - 0 - ns 0.45 - 0.35 - 0.35 - 0.3 - 0.25 - tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 0.9 - 0.9 - 0.9 - 1.0 - 1.1 - ns 0.9 - 0.9 - 0.9 - 1.0 - 1.1 - ns 0.4 - 0.4 - 0.4 - 0.45 - 0.5 - ns 0.4 - 0.4 - 0.4 - 0.45 - 0.5 - ns - tCLmin or tCHmin - tCLmin or tCHmin - - tCLmin or tCHmin - ns 1 tHP-0.4 - tHP-0.4 - - tHP-0.5 - ns 1 tHP tCLmin or tCHmin ata output hold time from DQS tQH tHP-0.4 lock half period -36 Max tCLmin or tCHmin tHP0.45 1 ote 1 : The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst ase output vaild window even then the clock duty cycle applied to the device is better than 45/55% A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax - 13 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF AC CHARACTERISTICS (I) Parameter Symbol -33 -36 -40 -50 -60 Unit Note Min Max Min Max Min Max Min Max Min Max tRC tRFC tRAS tRCD tRP tRRD 17 - 16 - 14 - 12 - 10 - 20 - 18 - 16 - 14 - 12 - 11 100K 10 100K 9 100K 8 100K 7 100K 6 - 5 - 5 - 4 - 3 - 6 - 5 - 5 - 4 - 3 - 2 - 2 - 2 - 2 - 2 - tCK tCK tCK tCK tCK tCK Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge tWR 3 - 3 - 3 - 2 - 2 - tCK 1 tWR_A 3 - 3 - 3 - 3 - 3 - tCK 1 Last data in to Read command tCDLR tCCD tMRD 2 - 2 - 2 - 2 - 2 - - 1 - 1 - 1 - 1 - 3 - 2 - 2 - 2 - 2 - tCK tCK tCK 1 1 tDAL 9 - 8 - 8 - 7 - 6 - tCK tXSR 200 - 200 - 200 - 200 - 200 - tCK Power down exit time tPDEX 2tCK +tIS - 2tCK +tIS - 1tCK +tIS - 1tCK +tIS - 1tCK +tIS - ns Refresh interval time tREF 15.6 15.6 - 15.6 - 15.6 - 15.6 - us Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read com- Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) (Unit : Number of Clock) K4D64163HF-TC33 Frequency Cas Latency 300MHz (3.0ns ) 3 275MHz ( 3.6ns ) 3 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 17 16 14 12 10 tRFC 20 18 16 14 12 tRAS 11 10 9 8 7 tRCD 6 5 5 4 3 tRP 6 5 5 4 3 tRRD 2 2 2 2 2 tDAL 9 8 8 7 6 Unit K4D64163HF-TC36 Frequency Cas Latency 275MHz (3.6ns ) 3 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 16 14 12 10 tRFC 18 16 14 12 tRAS 10 9 8 7 tRCD 5 5 4 3 tRP 5 5 4 3 tRRD 2 2 2 2 tDAL 8 8 7 6 Unit K4D64163HF-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 14 12 10 tRFC 16 14 12 tRAS 9 8 7 tRCD 5 4 3 tRP 5 4 3 tRRD 2 2 2 tDAL 8 7 6 Unit - 14 - tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF K4D64163HF-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 12 10 tRFC 14 12 tRAS 8 7 tRCD 4 3 tRP 4 3 tRRD 2 2 tDAL 7 6 Unit K4D64163HF-TC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3 tRC 10 tRFC 12 tRAS 7 tRCD 3 tRP 3 tRRD 2 tDAL 6 Unit tCK tCK tCK Simplified Timing @ BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BAa BAb BAa BAb Ra Rb Ra Rb Ca Cb 17 18 19 20 21 22 CK, CK BA[1:0] BAa A10/AP ADDR (A0~A11) BAa BAa Ra Ra Ca Ra WE DQS DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 DM COMMAND ACTIVEA WRITEA PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRP tRC Normal Write Burst (@ BL=4) tRRD Multi Bank Interleaving Write Burst (@ BL=4) - 15 - Rev. 1.1(Aug. 2002) 64M DDR SDRAM K4D64163HF PACKAGE DIMENSIONS (66pin TSOP-II) (10.76) (0.50) 0.125 +0.075 -0.035 0.30±0.08 (10×) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY - 16 - 0.075 MAX ] .2 5 0.10 MAX [ (R 0 0.65TYP 0.65±0.08 0.05 MIN (0.71) (R 0. 15 ) ) (R ( 4× ) (10×) 5) 1.20MAX 22.22±0.10 (R 0 .1 1.00±0.10 0.210±0.05 0.665±0.05 (1.50) 0. 25 ) (0.80) #33 (10×) 0.45~0.75 (1.50) (10×) #1 11.76±0.20 (0.80) #34 10.16±0.10 #66 (0.50) Units : Millimeters 0.25TYP 0×~8× Rev. 1.1(Aug. 2002)