TI1 BQ2026LPR 1.5k-bit serial eprom with sdq interface Datasheet

bq2026
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SLUS938 – DECEMBER 2011
1.5K-Bit Serial EPROM With SDQ Interface
Check for Samples: bq2026
FEATURES
DESCRIPTION
•
The bq2026 is a 1.5K-bit serial EPROM containing a
factory-programmed, unique 48-bit identification
number, 8-bit family code, and a 64-bit status
register.
1
2
•
•
•
•
•
•
1536 bits of One-Time Programmable (OTP)
EPROM For Storage Of User-Programmable
Configuration Data
Factory-Programmed Unique 64-Bit
Identification Number
Single-Wire Interface to Reduce Circuit Board
Routing
Synchronous Communication Reduces Host
Interrupt Overhead
6KV IEC 61000-4-2 ESD Compliance on Data
Pin
No Standby Power Required
Available in a 3-Pin SOT23 Package and TO-92
Package
The bq2026 SDQ™ interface requires only a single
connection and a ground return. The SDQ pin is also
the sole power source for the bq2026.
The small surface-mount package options saves
printed-circuit-board space, while the low cost makes
it ideal for applications such as battery pack
configuration parameters, record maintenance, asset
tracking, product-revision status, and access-code
security.
ORDERING INFORMATION(1)
TA (2)
APPLICATIONS
•
•
•
•
Security Encoding
Inventory Tracking
Product-Revision Maintenance
Battery-Pack Identification
–20°C to 70°C
PACKAGED DEVICES(3)
PART NUMBER
PACKAGE
STATUS
bq2026DBZR
SOT23-3
Production
bq2026LPR (4)
TO-92
Production
(1) For the most current package and ordering information, see
the Package Option Addendum at the end of this document, or
see the TI Web site at www.ti.com
(2) Device specified to communicate at –40°C to 85°C
(3) The device is available only in tape and reel with a base
quantity of 3000 units for the bq2026DBZR and 2000 units for the
bq2026LPR.
(4) ROHS Compliant
spacer
BLOCK DIAGRAM
DBZ PACKAGE
(TOP VIEW)
SDQ
SDQ
SDQ Communications
Controller and CRC
Generation Circuit
Internal
Bus
ID ROM
(64 bits)
VSS
VSS
EPROM
MEMORY
(1536 bits)
VSS
RAM
Buffer
(1 byte)
EPROM
STATUS
(64 bits)
VSS
LP PACKAGE
(BOTTOM VIEW)
1
VSS
2
SDQ
3
VSS
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDQ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
VALUE
DC voltage applied to VPU See Figure 1
MAX
–0.3
12.5
V
5
mA
Low-level output current, IOL
ESD IEC 61000-4-2 Air discharge
UNIT
MIN
6
kV
Operating free-air temperature range, TA
–20
70
°C
Storage temperature range, Tstg
–55
125
°C
(1)
SDQ to VSS, VSS to SDQ
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PARAMETER
ISDQ
Supply current
TEST CONDITION
MIN
TYP
MAX
VPU = 5.5 V
20
Logic 0, VPU = 5.5 V, IOL = 4 mA, SDQ pin
0.4
Logic 0, VPU = 2.65 V, IOL = 2 mA
0.4
UNIT
μA
VOL
Low-level output voltage
VOH
High-level output voltage
Logic 1
IOL
Low-level output current (sink)
VOL = 0.4 V, SDQ pin
VIL
Low-level input voltage
Logic 0
VIH
High-level input voltage
Logic 1
VPP
Programming voltage
Ilkg
Input leakage
1.4
µA
CI
Input capacitance
1.2
nF
VPU
V
5.5
4
0.8
2.2
mA
V
V
11.5
12
V
AC SWITCHING CHARACTERISTCS
TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PARAMETER
tc
Bit cycle time
tWSTRB
Write start cycle (1)
tWDSU
Write data setup
tWDH
Write data hold (1) (2)
trec
Recovery time
tRSTRB
Read start cycle (1)
tODD
Output data delay (1)
tODHO
Output data hold
tRST
Reset time (1)
tPPD
Presence pulse delay (1)
tPP
Presence pulse
tEPROG
EPROM programming time
tPSU
tPREC
(1)
(2)
2
TEST CONDITION
(1)
(1)
MIN
TYP
MAX
UNIT
60
120
μs
1
15
μs
tWSTRB
15
μs
60
tc
μs
μs
1
(1)
(1)
1
13
μs
tRSTRB
13
μs
17
60
μs
μs
480
(1)
15
64
μs
60
240
μs
480
μs
Program setup time
5
μs
Program recovery time
5
μs
5-kΩ series resistor between SDQ pin and VPU. (See Figure 1)
tWDH must be less than tc to account for recovery.
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AC SWITCHING CHARACTERISTCS (continued)
TA = –20°C to 70°C; VPU(min) = 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
tPRE
Program rising-edge time
5
μs
tPFE
Program falling-edge time
5
μs
tRSTREC
480
μs
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
bq2026DBZR
SDQ
1
I/O
VSS
2, 3
-
Data
Ground
Ground
bq2026LPR
VSS
1, 3
-
SDQ
2
I/O
Data
FUNCTIONAL DESCRIPTION
GENERAL OPERATION
The block diagram shows the relationships among the major control and memory sections of the bq2026. The
bq2026 has three main data components: a 64-bit factory-programmed ROM, including 8-bit family code, 48-bit
identification number and 8-bit CRC value, 1536-bit EPROM, and EPROM STATUS bytes. Power for read and
write operations is derived from the SDQ pin. An internal capacitor stores energy while the signal line is high and
releases energy during the low times of the SDQ pin, until the pin returns high to replenish the charge on the
capacitor.
EPROM
Table 1 is a memory map of the 1536-bit EPROM section of the bq2026, configured as six pages of 32 bytes
each. The 1-byte RAM buffer is an additional register used when programming the memory. Data are first written
to the RAM buffer and then verified by reading a 16-bit CRC from the bq2026 that confirms proper receipt of the
data. If the buffer contents are correct, a programming pluse is issued and a 1-byte segment of data is written
into the selected address in memory. This process ensures data integrity when programming the memory. The
details for reading and programming the 1536-bit EPROM portion of the bq2026 are in the Memory Function
Commands section of this data sheet.
Table 1. 1536-Bit EPROM Data Memory Map
ADDRESS (HEX)
PAGE
00A0-00BF
Page 5
0080-009F
Page 4
0060-007F
Page 3
0040-005F
Page 2
0020-003F
Page 1
0000-001F
Page 0
EPROM STATUS MEMORY
In addition to the programmable 1536-bits of memory are 8 bytes of status information, the first 7 bytes are
available to the user, contained in the EPROM STATUS memory. The STATUS memory is accessible with
separate commands. The STATUS bytes are EPROM and are read or programmed to indicate various
conditions to the software interrogating the bq2026. These general purpose bytes can be used by the customer
to store various information.
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Table 2. EPROM Status Bytes
ADDRESS (HEX)
PAGE
100h-107h
General Purpose OTP Status Memory
Error Checking
Error checking can be implemented by comparing the 16-bit CRC values transmitted by the bq2026. If the two
CRC values match, the transmission is error-free. Details are found in the CRC Generation section of this data
sheet.
Customizing the bq2026
The 64-bit ID identifies each bq2026. The 48-bit serial number is unique and programmed by Texas Instruments.
The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis.
Contact your Texas Instruments sales representative for more information.
Bus Termination
Because the drive output of the bq2026 is an open-drain, N-channel MOSFET, the host must provide a source
current or a 5-kΩ external pullup, as shown in the typical application circuit in Figure 1.
VPU
bq2026
SDQ
SDQI
1
Communications
Controller
CPU
SDQO
VSS
3
VSS
2
HOST
Figure 1. Typical Applications Circuit
Serial Communication
A host reads, programs, or checks the status of the bq2026 through the hierarchical command structure of the
SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or
status can be read or modified.
Initialization
ROM Command Sequence
Memory/Status Command Sequence
Figure 2. General Command Sequence
Initialization
Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESET
pulse, while the bq2026 responds with the PRESENCE pulse. The host resets the bq2026 by driving the DATA
bus low for at least 480 μs. For more details, see the RESET section under SDQ Signaling.
4
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ROM COMMANDS
READ ROM
The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code
and 48-bit identification number. The READ ROM sequence starts with the host generating the RESET pulse of
at least 480 μs. The bq2026 responds with a PRESENCE pulse. Next, the host continues by issuing the READ
ROM command, 33h, and then reads the ROM and CRC byte using the READ signaling (see the READ and
WRITE signals section) during the data frame.
Reset
and
Presence
Signals
1
1
Read ROM (33h)
0
0
1
1
Family Code and Identification
Number (7 BYTES)
0
0
CRC (1 BYTE)
Figure 3. READ ROM Sequence
MATCH ROM
The MATCH ROM command, 55h, is used by the host to select a specific SDQ device when the family code and
identification number is known. The host issues the MATCH ROM command followed by the family code, ROM
number, and the CRC byte. The device that matches the 64-bit ROM sequence is selected and available to
perform subsequent Memory/Status Function commands.
Reset
and
Presence
Signals
1
0
Match ROM (55h)
1
0
1
0
1
Family Code and Identification
Number (7 BYTES)
0
CRC (1 BYTE)
Figure 4. MATCH ROM Sequence
SKIP ROM
This SKIP ROM command, CCh, allows the host to access the memory/status functions without issuing the 64-bit
ROM code sequence. The SKIP ROM command is directly followed by a memory/status functions command.
Reset
and
Presence
Signals
Skip ROM (CCh)
0
1
0
1
0
1
0
1
Figure 5. SKIP ROM Sequence
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MEMORY/STATUS FUNCTION COMMANDS
Four memory/status function commands allow read and modification of the 1536-bit EPROM data memory or the
7-byte EPROM status memory. There is a READ MEMORY/Field CRC command, plus the WRITE MEMORY,
READ STATUS, and WRITE STATUS commands. The bq2026 responds to memory/status function commands
only after a part is selected by a ROM command.
READ MEMORY/Field CRC
To read the memory, the ROM command is followed by the READ MEMORY command, F0h, followed by the
address low byte and then the address high byte.
NOTE
As shown in Figure 6, individual bytes of address and data are transmitted LSB first.
The host then issues read time slots and receives data from the bq2026 starting at the initial address and
continuing until the end of the 1536-bit data field is reached or until a reset pulse is issued. If reading occurs
through the end of memory space, the host may issue sixteen additional read time slots and the bq2026
responds with a 16-bit CRC of all data bytes read from the initial starting byte through the last byte of memory.
After the CRC is received by the host, any subsequent read time slots appears as logical 1s until a reset pulse is
issued. Any reads ended by a reset pulse prior to reaching the end of memory does not have the 16-bit CRC
available.
Initialization and ROM
Command Sequence
READ MEMORY Command
F0h
Address Low
Byte
A0
Address High
Byte
A7 A8
Read EPROM Memory Until
End of EPROM Memory
Read and
Verify 16-bit
CRC
A15
Figure 6. READ MEMORY/Field CRC
6
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READ STATUS
The READ STATUS command is used to read data from the EPROM status data field. After issuing a ROM
command, the host issues the READ STATUS command, AAh, followed by the address low byte and then the
address high byte.
NOTE
An 16-bit CRC of the command byte and address bytes is computed by the bq2026 and
read back by the host to confirm that the correct command word and starting address
were received.
If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated.
If the CRC received by the host is correct, the host issues read time slots and receives data from the bq2026
starting at the supplied address and continuing until the end of the EPROM Status data field is reached. At that
point, the host receives a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes
from the initial starting byte through the final byte.
This feature is provided because the EPROM status information may change over time making it impossible to
program the data once and include an accompanying CRC that is always valid. Therefore, the READ status
command supplies a 16-bit CRC that is based on (and always is consistent with) the current data stored in the
EPROM status data field.
After the 16-bit CRC is read, the host receives logical 1s from the bq2026 until a reset pulse is issued. The
READ STATUS command sequence can be ended at any point by issuing a reset pulse.
Initialization and ROM
CommandSequence
READ MEMORY
Command
AAh
Address Low
Byte
A0
Address High
Byte
A7 A8
Read STATUS Memory Until
End of Page
A15
Read and
Verify 16-bit
CRC
of command,
address and
data
Figure 7. READ STATUS Command
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Read
Status
Flow
Write
Status
Flow
Master TX:
16-bit address, A
Master TX:
16-bit address, A
Master RX:
8-bit data at A
A = 0x0107?
A=A+1
NO
Master TX:
8-bit data, D
Master RX:
CRC of M/F cmd, A & D
YES
Master RX:
CRC of preloaded
A[15:0] & shifted D
Master TX:
Programming Pulse
Master RX:
CRC of all data transmitted
Master RX:
D
ROM
Function
Flow
A = 0x0107?
Master TX:
8-bit data, D
CRC =
A[15:0]
NO
A=A+1
YES
ROM
Function
Flow
Figure 8. Status Memory Read and Write Flowchart
8
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WRITE MEMORY
The WRITE MEMORY command is used to program the 1536-bit EPROM memory field. The 1536-bit memory
field is programmed in 1-byte segments. Data is first written into an 1-byte RAM buffer. The contents of the RAM
buffer is then ANDed with the contents of the EPROM memory field when the programming command is issued.
Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROM
command, the host issues the WRITE MEMORY command, 0Fh, followed by the low byte and then the high byte
of the starting address. The host then transmits 1 byte of data to the bq2026.
a 16-bit CRC is calculated and transmitted based on the command, address and data. If this CRC agrees with
the CRC calculated by the host, the host applies the programming voltage for at least 480 μs or tEPROG.
If at any time during the WRITE MEMORY process, the CRC read by the host is incorrect, a reset pulse must be
issued, and the entire sequence must be repeated.
The WRITE DATA MEMORY command sequence can be terminated at any point by issuing a reset pulse except
during the program pulse period tPROG.
NOTE
The bq2026 responds with the data from the selected EPROM address sent least
significant-bit first. This response should be checked to verify the programmed byte. If the
programmed byte is incorrect, then the host must reset the part and begin the write
sequence again.
For both of these cases, the decision to continue programming is made entirely by the host, because the bq2026
is not able to determine if the 16-bit CRC calculated by the host agrees with the 16-bit CRC calculated by the
bq2026.
Prior to programming, bits in the 1536-bit EPROM data field appear as logical 1s.
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Read
Memory
Flow
Write
Memory
Flow
Master TX:
16-bit address, A
Master TX:
16-bit address, A
Master RX:
8-bit data at A
A = 0x00BF?
A=A +1
NO
Master TX:
8-bit data, D
Master RX:
CRC of M/F cmd, A & D
Master RX:
CRC of preloaded
A[15:0] & shifted D
YES
Master RX:
CRC of all data transmitted
Master TX:
Programming Pulse
CRC = A[15:0]
Master RX: D
ROM
Function
Flow
Master TX:
8-bit data, D
A = 0x00BF?
A=A+1
NO
YES
ROM
Function
Flow
Figure 9. General Use OTP Memory Read and Write Flowchart
10
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WRITE STATUS
The Write Status command is used to program the EPROM Status data field after the bq2026 has been selected
by a ROM command
The flow chart in Figure 9 illustrates that the host issues the Write Status command, 55h, followed by the
address low byte and then the address high byte followed by the byte of data to be programmed.
NOTE
Individual bytes of address and data are transmitted LSB first. a 16-bit CRC of the
command byte, address bytes, and data byte is computed by the bq2026 and read back
by the host to confirm that the correct command word, starting address, and data byte
were received.
If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated.
If the CRC received by the host is correct, the programming voltage, VPP is applied to the SDQ pin for period
tPROG. Prior to programming, the first 7 bytes of the EPROM STATUS data field appear as logical 1s. For each bit
in the data byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the
EPROM STATUS data field is programmed to a logical 0 after the programming pulse has been applied at the
byte location.
After the programming pulse is applied and the data line returns to VPU, the host issues eight read time slots to
verify that the appropriate bits have been programmed. The bq2026 responds with the data from the selected
EPROM STATUS address sent least significant bit first. This response should be checked to verify the
programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write
sequence again. If the bq2026 EPROM data byte programming was successful, the bq2026 automatically
increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant
byte of the new two-byte address is also loaded into the 16-bit CRC generator as a starting value. The host
issues the next byte of data using eight write time slots.
As the bq2026 receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that
has been preloaded with the LSB of the current address and the result is a 16-bit CRC of the new data byte and
the new address. After supplying the data byte, the host reads this 16-bit CRC from the bq2026 with eight read
time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC
is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the
CRC is correct, the host issues a programming pulse and the selected byte in memory is programmed.
NOTE
The initial write of the WRITE STATUS command, generates a 16-bit CRC value that is
the result of shifting the command byte into the CRC generator, followed by the
two-address bytes, and finally the data byte. Subsequent writes within this WRITE
STATUS command due to the bq2026 automatically incrementing its address counter
generates a 16-bit CRC that is the result of loading (not shifting) the LSB of the new
(incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by
the host, because the bq2026 is not able to determine if the 16-bit CRC calculated by the host agrees with the
16-bit CRC calculated by the bq2026. If an incorrect CRC is ignored and a program pulse is applied by the host,
incorrect programming could occur within the bq2026. Also note that the bq2026 always increments its internal
address counter after the receipt of the eight read time slots used to confirm the programming of the selected
EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte
does not match the supplied data byte but the master continues with the WRITE STATUS command, incorrect
programming could occur within the bq2026. The WRITE STATUS command sequence can be ended at any
point by issuing a reset pulse.
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Table 3. Command Code Summary
COMMAND
(HEX)
DESCRIPTION
CATEGORY
33h
Read Serialization ROM and CRC
55h
Match Serialization ROM
CCh
Skip Serialization ROM
F0h
Read Memory/Field CRC
AAh
Read EPROM Status
0Fh
Write Memory
55h
Write EPROM Status
ROM Commands Available in Command Level I
Memory Function Commands
Available in Command Level II
SDQ SIGNALING
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or
to begin the start frame for a bit read. Figure 10 shows the initialization timing, whereas Figure 11 and Figure 12
show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit
is initiated, either the host continues controlling the bus during a WRITE, or the bq2026 responds during a
READ.
RESET AND PRESENCE PULSE
If the DATA bus is driven low for more than 120 μs, the bq2026 may be reset. Figure 10 shows that if the DATA
bus is driven low for more than 480 μs, the bq2026 resets and indicates that it is ready by responding with a
PRESENCE PULSE.
VPU
VIH
VIL
RESET
(Sent by Host)
Presence Pulse
(Sent by bq2026)
t PPD
t RST
t PP
t RSTREC
Figure 10. Reset Timing Diagram
WRITE
The WRITE bit timing diagram in Figure 11 shows that the host initiates the transmission by issuing the tWSTRB
portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a
WRITE 1.
V PU
Write ”1”
V IH
V IL
Write ”0”
t rec
t WSTRB
t WDSU
t WDH
Figure 11. Write Bit Timing Diagram
12
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READ
The READ bit timing diagram in Figure 12 shows that the host initiates the transmission of the bit by issuing the
tRSTRB portion of the bit. The bq2026 then responds by either driving the DATA bus low to transmit a READ 0 or
releasing the DATA bus to transmit a READ 1.
VPU
Read ”1”
V IH
V IL
Read ”0”
t RSTRB
t REC
t ODD
t ODHO
Figure 12. Read Bit Timing Diagram
PROGRAM PULSE
VPP
VPU
tPSU
tPFE
tPRE
tPREC
tEPROG
VSS
Figure 13. Program Pulse Timing Diagram
IDLE
If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in
IDLE. Bus transactions can resume at any time from the IDLE state.
CRC Generation
The bq2026 has a 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute
a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the bq2026 to
determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of
this CRC is shown in Figure 14.
Under certain conditions, the bq2026 also generates a 16-bit CRC value using the polynomial function is shown
in Figure 15 and provides this value to the bus master which validates the transfer of command, address, and
data bytes from the bus master to the bq2026. The bq2026 computes a 16-bit CRC for the command, address,
and data bytes received for the WRITE MEMORY and the WRITE STATUS commands, and then outputs this
value to the bus master which confirms proper transfer. Similarly, the bq2026 computes a 16-bit CRC for the
command and address bytes received from the bus master for the READ MEMORY, and READ STATUS
commands to confirm that these bytes have been received correctly.
In each case, where a CRC is used for data transfer validation, the bus master must calculate a CRC value
using the polynomial function in Figure 14 or Figure 15 and compares the calculated value to either the 8-bit
CRC value stored in the 64-bit ROM portion of the bq2026 (for ROM reads) or the 16-bit CRC value computed
within the bq2026. The comparison of CRC values and the decision to continue with an operation are determined
entirely by the bus master. No circuitry on the bq2026 prevents a command sequence from proceeding if the
CRC stored in or calculated by the bq2026 does not match the value generated by the bus master. Proper use of
the CRC can result in a communication channel with a high level of integrity.
SPACER
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :bq2026
13
bq2026
SLUS938 – DECEMBER 2011
www.ti.com
CLK
DAT
Q
D
Q
D
R
Q
D
R
R
+
Q
D
R
+
Q
D
Q
D
R
R
Q
D
R
+
Q
D
R
Figure 14. 8-bit CRC Generator Circuit (X8 + X5 + X4 + 1) for Serial Number Read
SPACER
CLK
DAT
Q
D
Q
D
R
Q
D
R
Q
D
R
Q
D
Q
D
R
R
Q
D
R
Q
D
R
Q
D
R
Q
D
R
Q
D
Q
D
R
R
Q
D
R
Q
D
R
R
Q
D
Q
D
R
R
Figure 15. 16-bit CRC Generator Circuit (X16 + X15 + X2 + 1) for Memory Interface
14
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :bq2026
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
BQ2026DBZR
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
BQ2026LPR
ACTIVE
TO-92
LP
3
2000
Pb-Free (RoHS)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CU NIPDAU Level-1-260C-UNLIM
CU SN
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ2026DBZR
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
DBZ
3
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
179.0
8.4
Pack Materials-Page 1
3.15
B0
(mm)
K0
(mm)
P1
(mm)
2.95
1.22
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Sep-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ2026DBZR
SOT-23
DBZ
3
3000
203.0
203.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSOT002A – OCTOBER 1994 – REVISED NOVEMBER 2001
LP (O-PBCY-W3)
PLASTIC CYLINDRICAL PACKAGE
0.205 (5,21)
0.175 (4,44)
0.165 (4,19)
0.125 (3,17)
DIA
0.210 (5,34)
0.170 (4,32)
Seating
Plane
0.157 (4,00) MAX
0.050 (1,27)
C
0.500 (12,70) MIN
0.104 (2,65)
FORMED LEAD OPTION
0.022 (0,56)
0.016 (0,41)
0.016 (0,41)
0.014 (0,35)
STRAIGHT LEAD OPTION
D
0.135 (3,43) MIN
0.105 (2,67)
0.095 (2,41)
0.055 (1,40)
0.045 (1,14)
1
2
3
0.105 (2,67)
0.080 (2,03)
0.105 (2,67)
0.080 (2,03)
4040001-2 /C 10/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead dimensions are not controlled within this area
D. FAlls within JEDEC TO -226 Variation AA (TO-226 replaces TO-92)
E. Shipping Method:
Straight lead option available in bulk pack only.
Formed lead option available in tape & reel or ammo pack.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSOT002A – OCTOBER 1994 – REVISED NOVEMBER 2001
LP (O-PBCY-W3)
PLASTIC CYLINDRICAL PACKAGE
0.539 (13,70)
0.460 (11,70)
1.260 (32,00)
0.905 (23,00)
0.650 (16,50)
0.610 (15,50)
0.020 (0,50) MIN
0.098 (2,50)
0.384 (9,75)
0.335 (8,50)
0.748 (19,00)
0.217 (5,50)
0.433 (11,00)
0.335 (8,50)
0.748 (19,00)
0.689 (17,50)
0.114 (2,90)
0.094 (2,40)
0.114 (2,90)
0.094 (2,40)
0.169 (4,30)
0.146 (3,70)
DIA
0.266 (6,75)
0.234 (5,95)
0.512 (13,00)
0.488 (12,40)
TAPE & REEL
4040001-3 /C 10/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Tape and Reel information for the Format Lead Option package.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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