K4F660812D,K4F640812D CMOS DRAM 8M x 8bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • Fast Page Mode operation • Part Identification - K4F660812D-JC/L(3.3V, 8K Ref., SOJ) - K4F640812D-JC/L(3.3V, 4K Ref., SOJ) - K4F660812D-TC/L(3.3V, 8K Ref., TSOP) - K4F640812D-TC/L(3.3V, 4K Ref., TSOP) • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • Active Power Dissipation Unit : mW • JEDEC Standard pinout Speed 8K 4K • Available in Plastic SOJ and TSOP(II) packages -45 324 432 • +3.3V±0.3V power supply -50 288 396 -60 252 360 • Refresh Cycles Refresh cycle K4F660812D* 8K K4F640812D 4K FUNCTIONAL BLOCK DIAGRAM Refresh time Normal L-ver 64ms 128ms RAS CAS W * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) Control Clocks Refresh Timer Refresh Counter Speed tRAC tCAC tRC tPC -45 45ns 12ns 80ns 31ns -50 50ns 13ns 90ns 35ns -60 60ns 15ns 110ns 40ns Row Decoder Refresh Control • Performance Range A0~A12 (A0~A11)*1 Row Address Buffer A0~A9 (A0~A10)*1 Col. Address Buffer Vcc Vss VBB Generator Memory Array 8,388,608 x 8 Cells Column Decoder Note) *1 : 4K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O Part NO. Data in Buffer DQ0 to DQ7 Data out Buffer OE K4F660812D,K4F640812D CMOS DRAM PIN CONFIGURATION (Top Views) • K4F660812D-T • K4F640812D-T • K4F660812D-J • K4F640812D-J VCC DQ0 DQ1 DQ2 DQ3 N.C VCC W RAS A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS VCC DQ0 DQ1 DQ2 DQ3 N.C VCC W RAS A0 A1 A2 A3 A4 A5 VCC (J : 400mil SOJ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (T : 400mil TSOP(II)) * (N.C) : N.C for 4K Refresh product Pin Name Pin Function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 7 Data In/Out VSS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection VSS DQ7 DQ6 DQ5 DQ4 VSS CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS K4F660812D,K4F640812D CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Units VIN,VOUT -0.5 to +4.6 V Voltage on V CC supply relative to VSS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C PD 1 W IOS Address 50 mA Voltage on any pin relative to VSS Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Symbol Min Typ Max Units Supply Voltage Parameter VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 - Vcc+0.3*1 V Input Low Voltage VIL -0.3 *2 - 0.8 V *1 : Vcc+1.3V at pulse width≤15ns which is measured at VCC *2 : -1.3 at pulse width≤15ns which is measured at V SS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH =-2mA) VOH 2.4 - V Output Low Voltage Level(I OL=2mA) VOL - 0.4 V K4F660812D,K4F640812D CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Max Speed Units K4F660812D K4F640812D ICC1 Don′t care -45 -50 -60 90 80 70 120 110 100 mA mA mA ICC2 Normal L Don′t care 1 1 1 1 mA mA ICC3 Don′t care -45 -50 -60 90 80 70 120 110 100 mA mA mA ICC4 Don′t care -45 -50 -60 70 60 50 70 60 50 mA mA mA ICC5 Normal L Don′t care 0.5 200 0.5 200 mA uA ICC6 Don′t care -45 -50 -60 120 110 100 120 110 100 mA mA mA ICC7 L Don′t care 350 350 uA ICCS L Don′t care 350 350 uA ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH ) ICC3* : RAS-only Refresh Current (CAS=V IH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @ tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @ tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH )=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V, W, OE=V IH, Address=Don′t care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=V CC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1, ICC3 and ICC6, address can be changed maximum once while RAS=V IL. In I CC4, address can be changed maximum once within one fast page mode cycle time, tPC. K4F660812D,K4F640812D CMOS DRAM CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] CIN1 - 5 pF Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ7] C DQ - 7 pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2) Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter -45 Symbol Min -50 Max Min -60 Max Min Units Note Max Random read or write cycle time tRC 80 90 110 ns Read-modify-write cycle time tRWC 115 133 153 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay tOFF 0 13 0 13 0 13 ns 6 Transition time (rise and fall) tT 1 50 1 50 1 50 ns 2 RAS precharge time tRP 25 0 0 30 40 ns RAS pulse width tRAS 45 RAS hold time tRSH 12 13 15 ns CAS hold time tCSH 45 50 60 ns CAS pulse width 10K 50 10K 60 10K ns tCAS 12 10K 13 10K 15 10K ns RAS to CAS delay time tRCD 18 33 20 37 20 45 ns 4 RAS to column address delay time tRAD 13 22 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 8 10 10 ns Column address set-up time tASC 0 0 0 ns Column address hold time tCAH 8 10 10 ns Column address to RAS lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 8 Read command hold time referenced to RAS tRRH 0 0 0 ns Write command hold time tWCH 8 10 10 ns Write command pulse width tWP 8 10 10 ns Write command to RAS lead time tRWL 13 15 15 ns Write command to CAS lead time tCWL 12 13 15 ns Data set-up time tDS 0 0 0 ns 9 Data hold time tDH 10 10 10 ns 9 K4F660812D,K4F640812D CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -45 Symbol Min -50 Max Min -60 Max Min Units Note Max Refresh period (Normal) tREF Refresh period (L-ver) tREF Write command set-up time tWCS 0 0 0 ns 7 CAS to W delay time tCWD 32 36 38 ns 7 RAS to W delay time tRWD 67 73 83 ns 7 Column address to W delay time tAWD 43 48 53 ns 7 CAS precharge W delay time tCPWD 48 53 60 ns CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 5 ns CAS hold time (CAS -before-RAS refresh) tCHR 10 10 10 ns RAS to CAS precharge time tRPC 5 5 5 ns Access time from CAS precharge tCPA Fast Page mode cycle time tPC 31 35 40 ns Fast Page mode read-modify-write cycle time tPRWC 70 76 85 ns CAS precharge time (Fast page cycle) tCP 9 10 10 ns 64 64 128 128 26 RAS pulse width (Fast page cycle) tRASP 45 RAS hold time from CAS precharge tRHCP 28 OE access time tOEA OE to data delay 200K 30 50 200K 30 12 64 ms 128 ms 35 60 200K 35 13 13 ns 3 ns ns 15 3 tOED 12 Output buffer turn off delay time from OE tOEZ 0 OE command hold time tOEH 12 13 15 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns 11 11 13 0 13 ns 13 0 ns 13 ns 6 Write command hold time (Test mode in) tWTH 15 15 15 ns W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 13,14,15 RAS precharge time (C-B-R self refresh) tRPS 80 90 110 ns 13,14,15 CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 13,14,15 K4F660812D,K4F640812D CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -45 Symbol Min -50 Max Min -60 Max Min Units Note Max Random read or write cycle time tRC 85 95 115 ns Read-modify-write cycle time tRWC 120 138 160 ns Access time from RAS tRAC 50 55 65 ns 3,4,10,12 Access time from CAS tCAC 17 18 20 ns 3,4,5,12 Access time from column address tAA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10K 65 10K ns CAS pulse width tCAS 17 10K 18 10K 20 10K ns RAS hold time tRSH 17 18 20 ns CAS hold time tCSH 50 55 65 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time tCWD 37 41 43 ns 7 RAS to W delay time tRWD 72 78 88 ns 7 Column Address to W delay time tAWD 48 53 58 ns 7 Fast Page mode cycle time tPC 36 40 45 ns Fast Page mode read-modify-write cycle time tPRWC 75 RAS pulse width (Fast page cycle) tRASP 50 81 Access time from CAS precharge tCPA 31 OE access time tOEA 17 OE to data delay tOED 17 18 18 ns OE command hold time tOEH 17 18 20 ns 200K 55 90 200K 65 ns 200K ns 35 40 ns 3 18 20 ns 3 K4F660812D,K4F640812D CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC (max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced V oh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD ≥tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP. 14. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 15. For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. K4F660812D,K4F640812D CMOS DRAM READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEZ tOEA VIL - tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE tWCH VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH DATA-IN Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS VIL - tRSH tCAS VIH VIL - tCRP tRAD tASR A tRCD VIH - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tOED tOEH tDS tDH DATA-IN Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM READ - MODIFY - WRTIE CYCLE tRWC tRP tRAS RAS VIH VIL - tCRP CAS tRCD tRSH tCAS VIH VIL - tASR tRAD tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tRWL tCWL tAWD tCWD W OE VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC DQ0 ~ DQ3(7) VI/OH VI/OL - tAA tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM FAST PAGE READ CYCLE tRP tRASP RAS VIH - tRHCP VIL - ¡ó tCRP CAS tCP tRCD VIH - tRAD tASC VIL - VIH VIL - tCSH tRAH tCAH ROW ADDR tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tRCH tRCS VIH - tASC ¡ó tCAH COLUMN ADDRESS ¡ó tRAL tRCS ¡ó tRRH tRCH VIL - tCAC tOEA tCAC tOEA OE tRSH tCAS ¡ó tRCS W tCP tCAS tCAS tASR A tPC VIH VIL - VOH VOL - ¡ó ¡ó tAA tAA DQ0 ~ DQ3(7) tCAC tOEA tRAC tCLZ tOEZ VALID DATA-OUT tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOFF tOEZ VALID DATA-OUT Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS tRHCP VIH VIL - ¡ó tPC tCRP CAS tCP tRCD VIH - tRAD tASC VIL - VIH VIL - tRAL tCSH tCAH tRAH tASC COLUMN ADDRESS ROW ADDR VIH - tWCH tCAH tASC ¡ó COLUMN ADDRESS tWCS tWP ¡ó tWCH tWP tCAH COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL OE tRSH tCAS ¡ó tWCS W tCP tCAS tCAS tASR A tPC ¡ó VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tCWL tRWL tCWL ¡ó tDS tDH VALID DATA-IN tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN ¡ó Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM FAST PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tRSH tRCD CAS tCP VIH - tCRP tCAS tCAS VIL - tRAD tPRWC tRAH tASR A VIH VIL - tCAH tASC COL. ADDR ROW ADDR COL. ADDR tRWL tRCS W tRAL tCAH tASC tCWL VIH - tCWL tWP VIL - tWP tCWD tCWD tAWD OE tAWD tCPWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA DQ0 ~ DQ3(7) tRAC tOEZ tDH tOED tDH tAA tDS tDS tOEZ VI/OH VI/OL - tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - DQ0 ~ DQ3(7) VOH - tOFF OPEN VOL Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CAS tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRAL tRCS W VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRC tRP tRAS VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRAL tWRH tWRP W OE VIH - tWCS tWCH tWP VIL - VIH VIL - tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CAS tCHS VIH - tCSR VIL - DQ0 ~ DQ3(7) VOH - tOFF OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined K4F660812D,K4F640812D CMOS DRAM PACKAGE DIMENSION 32 SOJ 400mil Units : Inches (millimeters) 0.360 (9.15) 0.380 (9.65) 0.435 (11.06) 0.445 (11.30) 0.400 (10.16) #32 0.006 (0.15) 0.012 (0.30) #1 0.148 (3.76) MAX 0.027 (0.69) MIN 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0.0375 (0.95) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 32 TSOP(II) 400mil 0.455 (11.56) 0.471 (11.96) 0.400 (10.16) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.037 (0.95) 0.050 (1.27) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50) 0.018 (0.45) 0.030 (0.75) 0~8 O