SAMSUNG K4G323222A

K4G323222A
CMOS SGRAM
32Mbit SGRAM
512K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 1.3
December 2000
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 (Dec. 2000)
-1-
K4G323222A
CMOS SGRAM
Revision History
Revision 1.3 (December 12, 2000)
• Removed WPB(Write Per Bit) function.
Revision 1.2 (August 1, 2000)
• Removed K4G323222A-40
• Changed tSH of K4G323222A from 0.7ns to 1.0ns
Revision 1.1 (June 27, 2000)
• Changed ICC5 of K4G323222A-40/45/50/60/70 :Refer to "DC Characteristics table" on page 6.
Revision 1.0 (June 07, 2000)
• Removed K4G323222A-55 and add K4G323222A-70
Revision 0.3 (March 06, 2000)
• For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
• Changed tCH/tCL of K4G323222A-60 from 2ns to 2.5ns
Revision 0.0 (January 14, 2000) - Target Spec
• Define target spec
Rev. 1.3 (Dec. 2000)
-2-
K4G323222A
CMOS SGRAM
512K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The K4G323222A is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
8 columns block write improves performance in graphics systems.
•
•
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Dual bank operation
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
100 Pin PQFP, TQFP (14 x 20 mm)
ORDERING INFORMATION
Part NO.
K4G323222A-PC/L45
K4G323222A-PC/L50
K4G323222A-PC/L7C
K4G323222A-PC/L60
K4G323222A-PC/L70
K4G323222A-QC/L45
K4G323222A-QC/L50
K4G323222A-QC/L7C
K4G323222A-QC/L60
K4G323222A-QC/L70
Graphics Features
• SMRS cycle.
-. Load color register
• Block Write(8 Columns)
Max Freq.
Interface Package
222MHz
200MHz
[email protected] LVTTL 100 PQFP
166MHz
143MHz
222MHz
200MHz
100 TQFP
[email protected] LVTTL
166MHz
143MHz
DQMi
CLK
•
CKE
COLUMN
MASK
MASK
BLOCK
WRITE
CONTROL
LOGIC
COLOR
REGISTER
WRITE
CONTROL
LOGIC
MUX
INPUT BUFFER
FUNCTIONAL BLOCK DIAGRAM
DQMi
DQi
(i=0~31)
SENSE
AMPLIFIER
COLUMN
DECORDER
512Kx32
CELL
ARRAY
DSF
512Kx32
CELL
ARRAY
OUTPUT BUFFER
WE
•
LATENCY &
BURST LENGTH
CAS
PROGRAMING
REGISTER
RAS
TIMING REGISTER
CS
ROW DECORDER
BANK SELECTION
DQMi
•
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
* Samsung Electronics reserves the right to
change products or specification without
CLOCK ADDRESS(A0~A10,BA)
notice.
Rev. 1.3 (Dec. 2000)
-3-
K4G323222A
CMOS SGRAM
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin QFP
Forward Type
20 x 14 mm2
0.65mm pin Pitch
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
VSS
A10
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VDD
A3
A2
A1
A0
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA
A9
DQ29
VSSQ
DQ30
DQ31
VSS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VDD
DQ0
DQ1
VSSQ
DQ2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A8/AP
PIN CONFIGURATION (TOP VIEW)
*PQFP (Height = 3.0mmMAX)
TQFP (Height = 1.2mmMAX)
PIN CONFIGURATION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tSS prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
DQMi
Data Input/Output Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
DQi
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
block write and special mode register set.
VDD/VSS
Power Supply /Ground
Power Supply : +3.3V±0.3V/Ground
VDDQ /VSSQ
Data Output Power /Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
N.C
No Connection
Rev. 1.3 (Dec. 2000)
-4-
K4G323222A
CMOS SGRAM
ABSOLUTE MAXIMUM RATINGS(Voltage referenced to VSS)
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, V OUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 4.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
Note
VDD, V DDQ
3.0
3.3
3.6
V
5
Input high voltage
VIH
2.0
3.0
VDDQ +0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
ILI
-10
-
10
uA
3
Output leakage current
ILO
-10
-
10
uA
4
Output Loading Condition
see figure 1
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ .
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDD.
5. The VDD condition of K4G323222A-45/50/7C/60 is 3.135V~3.6V.
CAPACITANCE
(VDD/VDDQ = 3.3V, TA = 23°C, f = 1MHz)
Pin
Symbol
Min
Max
Unit
Clock
CCLK
-
4.0
pF
RAS, CAS, WE, CS, CKE, DQM i,DSF
CIN
-
4.0
pF
Address
C ADD
-
4.0
pF
DQi
C OUT
-
5.0
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and V SS
CDC1
0.1 + 0.01
uF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
uF
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Rev. 1.3 (Dec. 2000)
-5-
K4G323222A
CMOS SGRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC1
Test Condition
CAS
Latency -45
Burst Length =1
tRC ≥ tRC(min), tCC ≥ tCC(min), Io =
0mA
Speed
-7C
-60
-70
3
220
200
-
180
160
2
150
150
200
150
150
mA
ICC2P
CKE ≤ VIL(max), t CC = 15ns
2
ICC2PS
CKE & CLK ≤ VIL(max), tCC = ∞
2
ICC2N
CKE ≥ VIH (min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
30
ICC2NS
CKE ≥ VIH (min), CLK ≤ VIL(max), t CC = ∞
Input signals are stable
15
Active Standby Current
in power-down mode
ICC3P
CKE ≤ VIL(max), t CC = 15ns
4
ICC3PS
CKE ≤ VIL(max), tCC = ∞
4
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3N
CKE ≥ VIH (min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
50
ICC3NS
CKE ≥ VIH (min), CLK ≤ VIL(max), t CC = ∞
Input signals are stable
30
Operating Current
(Burst Mode)
ICC4
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
Refresh Current
ICC5
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Self Refresh Current
Operating Current
(One Bank Block Write)
Note :
ICC6
ICC7
tRC ≥ tRC(min)
Unit Note
-50
2
mA
mA
mA
mA
3
310
290
-
260
230
2
160
160
290
160
160
mA
2
mA
3
2
mA
4
450
uA
5
3
260
240
-
220
200
2
190
190
240
190
190
CKE ≤ 0.2V
tCC ≥ tCC(min), Io=0mA, t BWC(min)
250
230
230
200
170
mA
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4G323222A-C*
5. K4G323222A-L* : Low Power version
Rev. 1.3 (Dec. 2000)
-6-
K4G323222A
CMOS SGRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Value
Unit
2.4 / 0.4
V
1.4
V
tr/tf =1 / 1
ns
1.4
V
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
•
Output
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
•
Output
•
Z0=50Ω
30pF
870Ω
30pF
•
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
Note : 1. The VDD condition of K4G323222A-45/50/7C/60 is 3.135V~3.6V.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-45
-50
-7C
-60
Unit
-70
CAS Latency
CL
3
2
3
2
-
2
3
2
3
2
CLK cycle time
tCC(min)
4.5
10
5
10
-
7.5
6
10
7
10
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
4
2
3
2
-
2
3
2
3
tRP(min)
4
2
3
2
-
2
3
2
tRAS(min)
9
5
8
5
-
6
7
5
Row precharge time
Row active time
2
tRAS(max)
Row cycle time
tRC( min)
Last data in to row precharge
tRDL(min)
Last data in to new col.address delay
tCDL(min)
Last data in to burst stop
Col. address to col. address delay
1
2
CLK
1
3
2
CLK
1
7
5
CLK
1
7
-
us
1
2
CLK
2,5
1
CLK
2
tBDL(min)
1
CLK
2
tCCD(min)
1
CLK
Block Write data-in to PRE command
tBPL(min)
2
CLK
Block write cycle time
tBWC(min)
1
CLK
tMRS(min)
1
CLK
Number of valid output
data
11
ns
CLK
Mode Register Set cycle time
7
CLK
CLK
100
13
Note
8
CAS Latency=3
2
CAS Latency=2
1
10
7
10
7
ea
3
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
Rev. 1.3 (Dec. 2000)
-7-
K4G323222A
CMOS SGRAM
Parameter
Version
Symbol
Unit
-45
-50
-7C
-60
-70
Row active to row active delay
tRRD(min)
9
10
15
12
14
ns
RAS to CAS delay
tRCD(min)
18
15
15
18
20
ns
Row precharge time
tRP(min)
18
15
15
18
20
ns
tRAS(min)
40.5
40
45
42
49
ns
60
70
Row active time
tRAS(max)
Row cycle time
100
tRC(min)
58.5
55
us
60
ns
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-45
Symbol
Min
CLK cycle time
CAS Latency=3
tCC
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
CLK high pulse
width
CLK low
pulse width
Input setup time
CAS Latency=3
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
1000
10
Min
-
Max
Min
1000
7.5
6
-70
Max
1000
10
Min
7
Unit
Note
ns
1
ns
1, 2
ns
2
ns
3
ns
3
ns
3
Max
1000
10
-
4.5
-
-
-
5.5
-
5.5
-
6
-
6
-
6
-
6
-
6
2
-
2
-
2
-
2
-
2
-
1.75
-
2
-
-
-
2.5
-
3
-
3
-
3
-
2
-
3
-
3
-
1.75
-
2
-
-
-
2.5
-
3
-
3
-
3
-
2
-
3
-
3
-
1.2
-
1.5
-
-
-
1.5
-
1.75
-
2.5
-
2.5
-
1.5
-
2.5
-
2.5
-
tSH
1
-
1
-
1
-
1
-
1
-
ns
3
tSLZ
1
-
1
-
1
-
1
-
1
-
ns
2
-
4
-
4.5
-
-
-
5.5
-
5.5
ns
-
-
6
-
6
-
6
-
6
-
6
tOH
tCH
tCL
tSS
CAS Latency=2
Input hold time
5
Max
-60
4
CAS Latency=3
CAS Latency=3
1000
Min
-7C
-
tSAC
CAS Latency=2
CAS Latency=2
Max
10
CAS Latency=2
Output data hold time
4.5
-50
tSHZ
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.3 (Dec. 2000)
-8-
K4G323222A
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn CS
Mode Register Set
H
X
L
RAS CAS WE DSF DQM BA
L
L
L
Special Mode Register Set
Refresh
Auto Refresh
H
Exit
Bank Active & Row Addr.
Auto Precharge Disable
Write &
Column
Address
Auto Precharge Disable
Block Write
&
Column
Auto Precharge Disable
L
L
L
L
H
L
1,2,7
X
H
X
3
L
H
H
H
H
X
X
X
L
L
H
H
X
X
X
L
H
L
H
3
L
X
V
L
X
L
X
L
H
L
L
L
X
L
X
L
H
L
L
H
X
Column
Address
(A0~A7)
V
Auto Precharge Enable
H
H
X
L
H
H
L
L
X
H
X
L
L
H
L
L
X
Both Banks
H
L
Exit
L
H
Entry
H
L
Precharge Power Down
Mode
Exit
Column
Address
(A0~A7)
V
H
H
Entry
Column
Address
(A0~A7)
V
Auto Precharge Enable
Clock Suspend or
Active Power Down
Row Address
H
H
L
DQM
H
No Operation Command
H
H
L
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
V
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
V
L
X
H
4,9
4
4, 6
4
4,6,9
4
4,6,9
7
X
X
X
X
X
X
X
X
X
X
3
X
Auto Precharge Enable
Bank Selection
3
X
L
H
Burst Stop
Precharge
H
Note
1, 2
OP CODE
L
H
Read &
Column
Address
X
H
Entry
Self
Refresh
L
A10 ,A9,
A7~A0
A8
X
X
V
X
X
X
8
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code
A0 ~ A10, BA : Program keys. (@MRS)
A6 : LCR select. (@SMRS)
Color register exists only one per DQi which both banks share.
Color is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ′s are idle.
A new command can be issued at the next clock of MRS/SMRS.
Rev. 1.3 (Dec. 2000)
-9-
K4G323222A
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both precharge state.
4. BA : Bank select address.
If "Low" at read, (block) write, Row active and precharge, bank A is selected.
If "High" at read, (block) write, Row active and precharge, bank B is selected.
If A8 is "High" at Row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/(block) write command cannot be issued.
Another bank read/(block) write command can be issued at tRP after the end of burst.
6. Burst stop command is valid only at full page burst length.
7. DQM sampled at positive going edge of a CLK.
masks the data-in at the very CLK(Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
8. Graphic features added to SDRAM′s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 32M SDRAM with 32 DQ′s.
SGRAM vs SDRAM
Function
MRS
Write
DSF
L
H
L
H
SGRAM
Function
MRS
SMRS
Normal
Write
Block
Write
If DSF is low, SGRAM functionality is identical to SDRAM functionality.
SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory
Rev. 1.3 (Dec. 2000)
- 10
K4G323222A
CMOS SGRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
BA
A10
Function
RFU
A9
A8
W.B.L
(Note 1)
Test Mode
Type
0
0
Mode Register Set
0
1
Vendor
Use
Only
0
1
TM
A5
A4
A3
CAS Latency
CAS Latency
A7
1
A6
A2
BT
A1
A0
Burst Length
(Note 2)
A8
1
A7
A6
Write Burst Length
Burst Type
Burst Length
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
0
Reserved
0
Sequential
0
0
0
1
Reserved
0
0
1
-
1
Interleave
0
0
1
2
Reserved
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved
Reserved
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
A9
(Note 3)
Special Mode Register Programmed with SMRS
Address
BA
A 10
Function
A9
A8
A7
X
A6
A5
LC
0
A4
A3
A2
A1
A0
X
Load Color
A6
Function
0
Disable
1
Enable
POWER UP SEQUENCE
SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
3. The full column burst(256bit) is available only at Sequential mode of burst type.
Rev. 1.3 (Dec. 2000)
- 11
K4G323222A
CMOS SGRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
PIXEL to DQ MAPPING(at BLOCK WRITE)
Column address
3 Byte
2 Byte
1 Byte
0 Byte
A2
A1
A0
I/O31 - I/O24
I/O23 - I/O16
I/O15 - I/O8
I/O7 - I/O0
0
0
0
DQ24
DQ16
DQ8
DQ 0
0
0
1
DQ25
DQ17
DQ9
DQ 1
0
1
0
DQ26
DQ18
DQ10
DQ 2
0
1
1
DQ27
DQ19
DQ11
DQ 3
1
0
0
DQ28
DQ20
DQ12
DQ 4
1
0
1
DQ29
DQ21
DQ13
DQ 5
1
1
0
DQ30
DQ22
DQ14
DQ 6
1
1
1
DQ31
DQ23
DQ15
DQ 7
Rev. 1.3 (Dec. 2000)
- 12
K4G323222A
CMOS SGRAM
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock for proper
functionality and I CC specifications.
SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Power must be applied to both CKE and DQM inputs to pull
them high and other pins are NOP condition at the inputs
before or along with VDD(and VDDQ ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause of
200 microseconds is required with inputs in NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the CAS
latency, burst length and burst type as the default value of
mode register is undefined.
At the end of one clock cycle from the mode register set cycle,
the device is ready for operation.
When the above sequence is used for Power-up, all the outputs
will be in high impedance state. The high impedance of outputs
is not guaranteed in any other power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SGRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When both banks
are in the idle state and CKE goes low synchronously with clock,
the SGRAM enters the power down mode from the next clock
cycle. The SGRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least " tSS + 1CLOCK " before the high going
edge of the clock, then the SGRAM becomes active from the
same clock edge accepting all the input commands.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SGRAM. It programs the CAS latency,
BANK SELECT (BA)
addressing mode, burst length, test mode and various vendor
This SGRAM is organized as two independent banks of 524,288
words x 32 bits memory arrays. The BA inputs is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. When BA is asserted low, bank A is selected.
When BA is asserted high, bank B is selected. The bank select
BA is latched at bank activate, read, write mode register set and
precharge operations.
specific options to make SGRAM useful for variety of different
applications. The default value of the mode register is not
defined, therefore the mode register must be written after power
up to operate the SGRAM. The mode register is written by
asserting low on CS, RAS, CAS, WE and DSF (The SGRAM
should be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0 ~ A10 and BA in
ADDRESS INPUT (A0 ~ A10)
the same cycle as CS, RAS, CAS, WE and DSF going low is the
The 19 address bits required to decode the 524,288 word locations are multiplexed into 11 address input pins(A0~A10). The 11
bit row address is latched along with RAS and BA during bank
activate command. The 8 bit column address is latched along
with CAS, WE and BA during read or write command.
data written in the mode register. One clock cycle is required to
complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle
requirements during operation as long as both banks are in the
idle state. The mode register is divided into various fields
NOP and DEVICE DESELECT
depending on functionality. The burst length field uses A0 ~ A2,
When RAS, CAS and WE are high, the SGRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE, DSF and all the address inputs are ignored.
burst type uses A3, addressing mode uses A 4 ~ A 6, A7 ~ A8 , A10
and BA are used for vendor specific options or test mode. And
the write burst length is programmed using A9. A7 ~ A8 , A10 and
BA must be set to low for normal SGRAM operation. Refer to
table for specific codes for various burst length, addressing
modes and CAS latencies.
Rev. 1.3 (Dec. 2000)
- 13
K4G323222A
CMOS SGRAM
DEVICE OPERATIONS
BANK ACTIVATE
cycles in adjacent addresses depending on burst length and
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank addresses, a row access is initiated. The read or write
operation can occur after a time delay of tRCD(min) from the time
of bank activation. tRCD(min) is an internal timing parameter of
SGRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD(min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SGRAM has two
internal banks on the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of both banks immediately. Also the noise generated during
sensing of each bank of SGRAM is high requiring some time for
power supplies to recover before the other bank can be sensed
reliably. tRRD(min) specifies the minimum time required between
activating different banks. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be
active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing may not
have been completed yet. The writing can not complete to burst
length. The burst write can be terminated by issuing a burst
read and DQM for blocking data inputs or burst write in the same
or the other active bank. The burst stop command is valid only at
full page burst length where the writing continues at the end of
burst and the burst is wrapped around. The write burst can also
be terminated by using DQM for blocking data and precharging
the bank "tRDL" after the last data input to be written into the
active row. See DQM OPERATION also.
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock,
therefore the masking occurs for a complete cycle. The DQM
signal is important during burst interrupts of write with read or
precharge in the SGRAM. Due to asynchronous nature of the
internal write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not required.
DQM is also used for device selection, byte selection and bus
control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. DQM masks the DQ′s by a byte
regardless that the corresponding DQ′s are in a state of Pixel
masking. Please refer to DQM timing diagram also.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read command is issued. The first output appears CAS latency number of
clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid only at full page burst length
where the output does not go into high impedance at the end of
burst and the burst is wrapped around..
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A8/AP with valid BA of the
bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank activate command in the desired bank. "tRP" is defined as the minimum time required to precharge a bank. The minimum number
of clock cycles required to complete row precharge is calculated
by dividing "tRP" with clock cycle time and rounding up to the
next higher integer. Care should be taken to make sure that
burst write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any bank
can be active is specified by tRAS(max). Therefore, each bank
has to be precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the idle
state and is ready to be activated again.
BURST WRITE
The burst write command is similar to burst read command, and
is used to write data into the SGRAM on consecutive clock
Rev. 1.3 (Dec. 2000)
- 14
K4G323222A
CMOS SGRAM
DEVICE OPERATIONS (Continued)
SELF REFRESH
Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state.
The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SGRAM. In self refresh
mode, the SGRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP′s
for a minimum time of "tRC" before the SGRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to use burst
2048 auto refresh cycles immediately after exiting self refresh.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SGRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A8/AP. If
burst read or burst write command is issued with low on A8/AP,
the bank is left active until a new command is asserted. Once
auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with
high on A8/AP after both banks have satisfied tRAS(min) requirement, performs precharge on both banks. At the end of tRP after
performing precharge all, both banks are in idle state.
DEFINE SPECIAL FUNCTION(DSF)
The DSF controls the graphic applications of SGRAM. If DSF is
tied to low, SGRAM functions as 512K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate
DSF command. All the graphic function modes can be entered
only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands. SDRAM functions
such as Write, and WCBR change to SGRAM functions such as
Block Write and SWCBR respectively. See the section below for
the graphic functions that DSF controls.
AUTO REFRESH
The storage cells of SGRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,RAS
and CAS with high on CKE and WE. The auto refresh command
SPECIAL MODE REGISTER SET(SMRS)
can only be asserted with both banks being in idle state and the
There is special mode registers in SGRAM. it is color register.
That usage will be explained in the "BLOCK WRITE" sections.
when A6 and DSF goes high in the same cycle as CS, RAS,
CAS and WE going low, Load Color Register(LCR) process is
executed and the color register is filled with color data for associated DQ′s through the DQ pins. If A 6 is high at SMRS, color
cycle is required to complete the write in the color register at
LCR. A new command can be issued in the next clock of LCR.
SMRS, compared with MRS, can be issued at the active state
under the condition that DQ′s are idle. As in write operation,
SMRS accepts the data needed through DQ pins. Therefore bus
contention must be avoided. The more detailed materials can be
obtained by referring corresponding timing diagram.
device is not in power down mode (CKE is high in the previous
cycle). The time required to complete the auto refresh operation
is specified by "tRC(min)". The minimum number of clock cycles
required can be calculated by driving "tRC" with clock cycle time
and them rounding up to the next higher integer. The auto
refresh command must be followed by NOP′s until the auto
refresh operation is completed. Both banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 2048 auto refresh cycles once in
32ms.
Rev. 1.3 (Dec. 2000)
- 15
K4G323222A
CMOS SGRAM
DEVICE OPERATIONS (Continued)
Timing Diagram to lllustrate tBWC
BLOCK WRITE
Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during a single access cycle. During block write the data to be written comes
from an internal "color" register and DQ I/O pins are used for
independent column selection. The block of column to be written
is aligned on 8 column boundaries and is defined by the column
address with the 3 LSB′s ignored. Write command with DSF=1
enables block write for the associated bank. A write command
with DSF=0 enables normal write for the associated bank. The
block width is 8 column where column="n" bits for by "n" part.
The color register is the same width as the data port of the
chip.It is written via a SWCBR where data present on the DQ pin
is to be coupled into the internal color register. The color register
provides the data masked by the DQ column select, and DQM
byte mask. Column data masking(Pixel masking) is provided on
an individual column basis for each byte of data. The column
mask is driven on the DQ pins during a block write command.
The DQ column mask function is segmented on a per bit
basis(i.e. DQ[0:7] provides the column mask for data bits[0:7],
DQ[8:15] provides the column mask for data bits[8:15], DQ0
masks column[0] for data bits[0:7], DQ9 masks column [1] for
data bits [8:15], etc). Block writes are always non-burst, independent of the burst length that has been programmed into the
mode register. Back to back block writes are allowed provided
that the specified block write cycle time(tBWC) is satisfied. DQM
masking provides independent data byte masking during block
write exactly the same as it does during normal write operations,
except that the control is extended to the consecutive 8 columns
of the block write.
0
1
2
CLOCK
CKE
HIGH
CS
RAS
CAS
WE
DSF
1 CLK BW
Rev. 1.3 (Dec. 2000)
- 16
K4G323222A
CMOS SGRAM
SUMMARY OF 4M Byte SGRAM BASIC FEATURES AND BENEFITS
Features
Interface
Bank
Page Depth / 1 Row
Total Page Depth
Burst Length(Read)
Burst Length(Write)
512K x 32 x 2 SGRAM
Synchronous
2 ea
CAS Latency
Block Write
Color Register
Mask function
Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.
256 bit
High speed vertical and horizontal drawing.
2048 bytes
High speed vertical and horizontal drawing.
1, 2, 4, 8 Full Page
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
1, 2, 4, 8 Full Page
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
BRSW
Burst Type
Benefits
Sequential & Interleave
2, 3
8 Columns
1 ea.
DQM0-3
Pixel Mask at Block Write
Switch to burst length of 1 at write without MRS.
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.
A and B bank share.
Byte masking(pixel masking for 8bpp system) for data-out/in
Byte masking(pixel masking for 8bpp system) for color by DQi
Rev. 1.3 (Dec. 2000)
- 17
K4G323222A
CMOS SGRAM
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
2) Clock Suspended During Read (BL=4)
1) Clock Suspended During Write (BL=4)
CLK
CMD
WR
RD
CKE
Masked by CKE
Masked by CKE
Internal
CLK
DQ(CL2)
D0
D1
DQ(CL3)
D0
D1
D2
D3
D2
D3
Q0
D
Q01
Q0
Not Written
Q2
Q3
Q1
Q2
Q3
Suspended Dout
Note : CKE to CLK disable/enable=1 clock
2. DQM Operation
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK
CMD
WR
RD
DQMi
Note 1
Masked by DQM
DQ(CL2)
D0
DQ(CL3)
D0
D1
Q0
D3
D1
Masked by DQM
Hi-Z
Hi-Z
D3
DQM to Data-in Mask = 0CLK
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2CLK
3) DQM with Clock Suspended (Full Page Read) Note 2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Hi-Z
Q2
Hi-Z
Q1
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
*Note : 1. There are 4 DQMi(i=0~3).
Each DQMi masks 8 DQi′s.(1 Byte, 1 Pixel for 8 bpp)
2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE " L".
Rev. 1.3 (Dec. 2000)
- 18
K4G323222A
CMOS SGRAM
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4)Note 1
CLK
CMD
RD
RD
ADD
A
B
DQ(CL2)
QA0
DQ(CL3)
QB0
QB1
QB2
QB3
QA0
QB0
QB1
QB2
QB3
tCCD
Note 2
2) Write interrupted by(Block) Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CMD
WR
WR
tCCD
ADD
A
WR
tCCD
Note 2
B
BW
C
WR
RD
tCCD
Note 2
D
A
Note 2
B
Note 4
DQ
DA0
DB0
DB1
DC0
Pixel
tCDL
tCDL
Note 3
Note 3
DQ(CL2)
DA0
DQ(CL3)
DA0
QB0
QB1
QB0
QB1
tCDL
Note 3
4) Block Write to Block Write
CLK
CMD
BW
BW
ADD
A
B
Note 4
DQ
Pixel Pixel
tBWC
Note 5
*Note : 1. By " Interrupt ", It is possible to stop burst read/write by external command before the end of burst.
By "CAS Interrupt" , to stop burst read/write by CAS access ; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
4. Pixel :Pixel mask.
5. tBWC : Block write minimum cycle time.
Rev. 1.3 (Dec. 2000)
- 19
K4G323222A
CMOS SGRAM
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
DQ
ii) CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii) CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
Note 1
D0
D3
(2) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
D0
DQ
ii) CMD
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
DQ
iii) CMD
D0
RD
WR
DQM
D0
DQ
iv) CMD
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
Note 2
D0
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Rev. 1.3 (Dec. 2000)
- 20
K4G323222A
CMOS SGRAM
5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMD
WR
PRE
Note 1
DQM
DQ
D0
D1
D2
D3
Masked by DQM
*Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
CMD
DQ
D0
PRE
D1
D2
BW
DQ
D3
PRE
Pixel
tRDL
tBPL
Note 1,4
Note 1
3) Read (BL=4)
CLK
CMD
RD
PRE
DQ(CL2)
Q0
DQ(CL3)
Note 2
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
DQ
D0
CMD
D1
D2
DQ
(CL 2, 3)
D3
Note 3,4
Auto Precharge Starts
3) Read (BL=4)
BW
Pixel
tBPL
tRP
Note 3
Auto Precharge Starts
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Note 3
Auto Precharge Starts
*Note :1. tBPL : Block write data-in to PRE command delay
2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated
bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
4. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
- 21
K4G323222A
CMOS SGRAM
8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4)
2) Write Burst Stop (Full Page Only)
CLK
CMD
CLK
WR
PRE
CMD
WR
DQ
D0
STOP
DQM
DQ
D0
D1
D2
D3
tRDL
D2
tBDL
3) Read Interrupted by Precharge (BL=4)
4) Read Burst Stop (Full Page Only)
CLK
CMD
D1
Note 1,5
CLK
RD
CMD
PRE
RD
STOP
Note 3
DQ(CL2)
Q0
Q1
Note 3
1
DQ(CL2)
2
DQ(CL3)
Q0
Q0
Q1
2
DQ(CL3)
Q1
1
Q0
Q1
9. MRS & SMRS
2) Special Mode Register Set
1) Mode Register Set
CLK
CLK
Note 4
CMD
PRE
CMD
MRS ACT
tRP
1CLK
SMRS ACT SMRS SMRS BW
1CLK
1CLK
1CLK
1CLK
*Note : 1. tRDL : 2 CLK, Last Data in to Row Precharge.
2. tBDL : 1 CLK, Last Data in to Burst Stop Delay.
3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
5. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
- 22
K4G323222A
CMOS SGRAM
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
CKE
tSS
tSS
Internal
CLK
Note 1
CMD
Note 2
CMD
RD
NOP ACT
11. Auto Refresh & Self Refresh
∼
1) Auto RefreshNote 3
CLK
Note 4
Note 5
PRE
AR
CMD
∼∼ ∼
CMD
CKE
tRP
tRC
∼
2) Self RefreshNote 6
∼
CLK
Note 4
SR
PRE
CMD
∼
CMD
∼
∼
CKE
tRP
tRC
*Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don′t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (2K cycles) is recommended.
Rev. 1.3 (Dec. 2000)
- 23
K4G323222A
CMOS SGRAM
12. About Burst Type Control
Sequential Counting
At MRS A 3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page wrap around.
Interleave Counting
At MRS A 3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Basic
MODE
PseudoDecrement Sequential
Counting
At MRS A 3 = "1".(See to Interleave Counting Mode)
Starting Address LSB 3 bits A0-2 should be "000" or "111"[email protected]=8.
-- if LSB="000" : Increment Counting.
-- if LSB="111" : Decrement Counting.
For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8)
-- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7
-- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at Interleave Counting mode,
by confining starting address to some values, Pseudo-Decrement Counting Mode can be
realized. See the BURST SEQUENCE TABLE carefully.
PseudoBinary Counting
At MRS A 3 = "0".(See to Sequential Counting Mode)
A 0-2 = "111".(See to Full Page Mode)
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized.
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8)
-- @ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command)
Note. The next column address of 256 is 0.
PseudoMODE
Random
MODE
Random column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
2
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
4
At MRS A2,1,0 = "010".
8
Full Page
BRSW
Special
MODE
Block Write
Random
MODE
Burst Stop
RAS Interrupt
(Interrupted by Precharge)
Interrupt
MODE
CAS Interrupt
At MRS A2,1,0 = "011".
At MRS A2,1,0 = "111".
Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
tBWC should not be violated.
At auto precharge, tRAS should not be violated.
tBDL = 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
stops read/write burst with Row precharge.
tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge, CAS interrupt can not be issued.
Rev. 1.3 (Dec. 2000)
- 24
K4G323222A
CMOS SGRAM
14. Mask Functions
Block Write
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color.
Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011"
i) STEP
- SMRS(LCR) :Load color(for 8bpp, through x32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011"
- Row Active with DSF "L"
- Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110"
i) ILLUSTRATION
I/O(=DQ)
31
DQMi
Color Register
000
Before
Block
Write
&
DQ
(Pixel
data)
After
Block
Write
24
DQM3=0
23
16
15
8
DQM2=0
DQM1=0
7
0
DQM0=1
Color3=Blue
Color2=Green
Color1=Yellow
Color0=Red
White DQ24=H
White DQ16=H
White DQ8=H
White DQ0=L
White DQ1=H
001
White DQ25=H
White DQ17=H
White DQ9=L
010
White DQ26=H
White DQ18=L
White DQ10=H
White DQ2=H
011
White DQ27=L
White DQ19=H
White DQ11=H
White DQ3=H
100
White DQ28=H
White DQ20=H
White DQ12=H
White DQ4=L
101
White DQ29=H
White DQ21=H
White DQ13=L
White DQ5=H
110
White DQ30=H
White DQ22=L
White DQ14=H
White DQ6=H
111
White DQ31=L
White DQ23=H
White DQ15=H
White DQ7=H
000
Blue
Green
Yellow
White
001
Blue
Green
White
White
010
Blue
White
Yellow
White
011
White
Green
Yellow
White
100
Blue
Green
Yellow
White
101
Blue
Green
White
White
110
Blue
White
Yellow
White
111
White
Green
Yellow
White
Note 2
*Note : 1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A2-0 (000-111).
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
Rev. 1.3 (Dec. 2000)
- 25
K4G323222A
CMOS SGRAM
Power On Sequence & Auto Refresh
1
2
3
4
6
7
8
9
10
12
13
14
15
16
17
18
19
High level is necessary
∼
∼
CKE
11
∼
∼
∼
CLOCK
5
∼
0
CS
tRC
∼ ∼
Ra
∼ ∼
KEY
High level is necessary
∼
High-Z
DQ
Precharge
(All Banks)
Auto Refresh
∼
DQM
BS
∼
∼
DSF
KEY
∼ ∼
∼ ∼
WE
∼ ∼
∼ ∼
A8/AP
Ra
∼ ∼
∼ ∼
BA
KEY
∼ ∼
∼ ∼
ADDR
∼ ∼
CAS
∼ ∼
RAS
∼ ∼
∼ ∼
tRP
Auto Refresh
Mode Register Set
Row Active
: Don′t care
Rev. 1.3 (Dec. 2000)
- 26
K4G323222A
CMOS SGRAM
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
CKE
HIGH
tRAS
tRC
*Note 1
tSH
CS
tRCD
tRP
tSS
tSH
RAS
tCCD
tSS
tSH
CAS
tSS
tSH
ADDR
Ra
tSS
Ca
Cb
Cc
Rb
tSH
tSS
*Note 2
*Note 2,3
*Note 2,3
BA
BS
BS
BS
A8/AP
Ra
*Note 3
*Note 2
*Note 2,3 *Note 4
BS
*Note 3
BS
BS
*Note 3 *Note 4
Rb
tSH
WE
tSS
*Note 5
*Note 5
*Note 5
*Note 3
DSF
tSS
tSH
tSS
tSH
DQM
tRAC
tSH
tSAC
Qa
DQ
tSLZ
Db
Qc
tSS
tOH
tSHZ
Row Active
Read
Write
or
Block Write
Read
Row Active
Precharge
: Don′t care
Rev. 1.3 (Dec. 2000)
- 27
K4G323222A
CMOS SGRAM
*Note : 1. All input can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
Active & Read/Write
0
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A8/AP in read/write command.
A8/AP
0
1
BA
0
Operation
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A8/AP and BA control bank precharge when precharge command is asserted.
A8/AP
BA
Precharge
0
0
Bank A
0
1
Bank B
1
X
Both Bank
5. Block write/normal write is controlled by DSF.
DSF
Operation
Minimum cycle time
L
Normal write
H
Block write
tCCD
tBWC
Rev. 1.3 (Dec. 2000)
- 28
K4G323222A
CMOS SGRAM
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
tRC
*Note 1
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Rb
Cb0
BA
A8/AP
Ra
Rb
WE
DSF
DQM
tOH
DQ
(CL=2)
Qa0
tRAC
*Note 3
Qa1
Qa2
Qa3
tSAC
Db0
tSHZ
Db1
Db2
Db3
tRDL
*Note 4
*Note 5
tOH
DQ
(CL=3)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
tRAC
*Note 3
Row Active
(A-Bank)
Read
(A-Bank)
tSAC
tSHZ
Precharge
(A-Bank)
tRDL
*Note 4
Row Active
(A-Bank)
*Note 5
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clcok.
3. Access time from Row address. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8). At Full page bit burst, burst is wrap-around.
5. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
- 29
K4G323222A
CMOS SGRAM
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A8/AP
Ra
tRDL
tCDL
*Note 4
WE
*Note 2
DSF
*Note 1
*Note 3
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Row Active
(A-Bank)
Read
(A-Bank)
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
- 30
K4G323222A
CMOS SGRAM
Block Write cycle(with Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
*Note 2
ADDR
RAa
CAa
CAb
RBa
CBa CBb
BA
A8/AP
RAa
RBa
WE
DSF
tBWC
DQM
*Note 1
Pixel
Mask
DQ
Row Active
Pixel
Mask
Block Write
(A-Bank)
Pixel
Mask
Row Active
(B-Bank)
Pixel
Mask
Block Write with
Auto Precharge
(B-Bank)
Block Write
(B-Bank)
Block Write with
Auto Precharge
(A-Bank)
: Don′t care
*Note : 1. Column Mask(DQi=L : Mask, DQi=H :Non Mask)
2. At Block Write, CA0~2 are ignored.
Rev. 1.3 (Dec. 2000)
- 31
K4G323222A
CMOS SGRAM
SMRS and Block/Normal Write @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
A0-2
RAa
A3,4,7,8
RAa
A5
RBa
CBa
CAa
RBa
CBa
RAa
CAa
RBa
CBa
A6
RAa
CAa
RBa
CBa
A8/AP
RAa
RBa
BA
WE
DSF
DQM
DQ
Color
Pixel
Mask
Load Color
Register
Row Active
(A-Bank)
DBa0 DBa1 DBa2 DBa3
Row Active
(B-Bank)
Block Write
(A-Bank)
Write
with Auto
Precharge
(B-Bank)
: Don′t care
Rev. 1.3 (Dec. 2000)
- 32
K4G323222A
CMOS SGRAM
Page Read Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A8/AP
RAa
RBb
WE
LOW
DSF
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DQ
(CL=3)
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
QBd0 QBd1 QAe0 QAe1
QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
QBd0 QBd1 QAe0 QAe1
Precharge
(A-Bank)
Read
(A-Bank)
: Don′t care
*Note : 1. CS can be don ′t care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Rev. 1.3 (Dec. 2000)
- 33
K4G323222A
CMOS SGRAM
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
RAa
RBb
A8/AP
tCDL
WE
DSF
DQM
DQ
DAa0 DAa1 DAa2
Row Active
(B-Bank)
Row Active
(A-Bank)
DAa3
DBb0 DBb1 DBb2 DBb3
Write
(B-Bank)
DAc0
DAc1 DAc2
Write
with auto
precharge
(A-Bank)
Write
(A-Bank)
DAc3
DBd0 DBd1 DBd2 DBd3
Write with auto
Precharge
(B-Bank)
: Don′t care
Rev. 1.3 (Dec. 2000)
- 34
K4G323222A
CMOS SGRAM
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A8/AP
RAa
RAc
RBb
tCDL
*Note 1
WE
DSF
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
DBb0
DBb1 DBb2 DBb3
DBb0
DBb1 DBb2 DBb3
Write
(B-Bank)
QAc0
QAc1 QAc2
QAc0
QAc1
Read
(A-Bank)
Row Active
(A-Bank)
: Don′t care
*Note : 1. tCDL should be met to complete write.
Rev. 1.3 (Dec. 2000)
- 35
K4G323222A
CMOS SGRAM
Read & Write Cycle with Auto Precharge I @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
BA
A8/AP
WE
DSF
DQMi
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
DBb0
DBb1 DBb2 DBb3
DBb0
DBb1 DBb2 DBb3
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
: Don′t care
*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
Rev. 1.3 (Dec. 2000)
- 36
K4G323222A
CMOS SGRAM
Read & Write Cycle with Auto Precharge II @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Ra
Cb
Ca
BA
A8/AP
Ra
WE
DSF
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Qa1
Qb0
Qb1
Qb2
Qb3
Qa0
Qa1
Qb0
Qb1
Qb2
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank) *Note 1
Precharge
(B-Bank)
Qb3
Row Active
(A-Bank)
Da0
Da1
Da0
Da1
Write with
Auto Precharge
(A-Bank)
: Don′t care
*Note:
1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Rev. 1.3 (Dec. 2000)
- 37
K4G323222A
CMOS SGRAM
Read & Write Cycle with Auto Precharge III @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
BA
A8/AP
Rb
Ra
WE
DSF
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qb0
Qa3
Qb1
Qb0
Qb2
Qb1
Qb3
Qb2
Qb3
*Note 1
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don′t care
*Note :
1. Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
Rev. 1.3 (Dec. 2000)
- 38
K4G323222A
CMOS SGRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note 1
*Note 1
BA
A8/AP
RAa
WE
DSF
DQM
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
*Note 2
DQ
(CL=2)
DQ
(CL=3)
Row Active
(A-Bank)
Read
(A-Bank)
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ′s after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
Rev. 1.3 (Dec. 2000)
- 39
K4G323222A
CMOS SGRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note 1
*Note 1
BA
A8/AP
RAa
tBDL
tRDL
*Note 5
WE
DSF
*Note 3
DQM
*Note 2
DAa0 DAa1 DAa2 DAa3 DAa4
DQ
Row Active
(A-Bank)
Write
(A-Bank)
DAb0 DAb1 DAb2 DAb3 DAb4
Burst Stop
DAb5
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.
It is defined by AC parameter of tBDL(=1CLK).
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(=2CLK).
DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
4. Burst stop is valid only at full page burst length.
5. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
- 40
K4G323222A
CMOS SGRAM
Burst Read Single bit Write Cycle @Burst Length=2, BRSW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note 1
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A8/AP
RAa
RBb
RAc
WE
DSF
DQMi
DQ
(CL=2)
DAa0
DQ
(CL=3)
DAa0
Row Active
(A-Bank)
QAb0
QAb1
QAb0
Row Active
(B-Bank)
Write
(A-Bank)
QAd0 QAd1
DBc0
QAb1
QAd0 QAd1
DBc0
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
: Don′t care
*Note : 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Rev. 1.3 (Dec. 2000)
- 41
K4G323222A
CMOS SGRAM
Clock suspension & DQM operation cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A8/AP
Ra
WE
DSF
*Note 1
DQM
DQ
Qa0
Qa1
Qa2
Qb0
Qa3
tSHZ
Row Active
Read
Read
Clock
Suspension
Qb1
Dc0
Dc2
tSHZ
Write
DQM
Read DQM
Write
Clock
Suspension
: Don′t care
*Note : 1. DQM needed to prevent bus contention.
Rev. 1.3 (Dec. 2000)
- 42
K4G323222A
CMOS SGRAM
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
2
3
4
CLOCK
tSS
6
7
8
9
*Note 2
10
11
12
13
14
15
16
17
18
19
tSS
tSS
tSS
∼
*Note 1
∼
CKE
5
∼
1
∼ ∼
0
∼ ∼
∼ ∼
*Note 3
∼ ∼
∼ ∼
∼ ∼
Ra
∼ ∼
DQM
∼ ∼
∼ ∼
DQ
∼
∼
DSF
∼ ∼
∼ ∼
WE
Precharge
Power-down
Entry
Ca
∼ ∼
∼ ∼
A8/AP
Ra
∼ ∼
BA
∼ ∼
ADDR
∼ ∼
CAS
∼ ∼
RAS
∼ ∼
∼ ∼
CS
Precharge
Power-down
Exit
Row Active
Qa0
Read
Active
Power-down
Entry
Active
Power-down
Exit
*Note : 1. All banks should be in idle state prior to entering precharge power down mode.
Qa1
Qa2
Precharge
: Don′t care
2. CKE should be set high at least "1CLK + tSS" prior to Row active command.
3. Cannot violate minimum refresh specification. (32ms)
Rev. 1.3 (Dec. 2000)
- 43
K4G323222A
CMOS SGRAM
Self Refresh Entry & Exit Cycle
1
2
3
4
5
6
7
8
9
10
11
12
*Note 4
*Note 2
13
16
17
18
19
*Note 6
∼
*Note 3
CKE
15
tRCmin.
tSS
*Note 1
14
∼
∼ ∼
0
CLOCK
∼
tSS
*Note 7
∼ ∼
∼ ∼
RAS
∼ ∼
∼ ∼
ADDR
∼ ∼
∼ ∼
BA
∼ ∼
∼ ∼
A8/AP
∼ ∼
∼ ∼
WE
∼ ∼
∼ ∼
DSF
Self Refresh Entry
∼
Hi-Z
∼
Hi-Z
∼ ∼
∼ ∼
DQM
*Note 7
∼ ∼
∼ ∼
CAS
DQ
*Note 5
∼
∼ ∼
CS
Self Refresh Exit
Auto Refresh
*Note : TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don′t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
: Don′t care
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit
if the system uses burst refresh.
Rev. 1.3 (Dec. 2000)
- 44
K4G323222A
CMOS SGRAM
Mode Register Set Cycle
0
1
2
3
4
5
Auto Refresh Cycle
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
∼ ∼
HIGH
HIGH
CKE
∼
CS
*Note 2
RAS
∼∼ ∼
tRC
*Note 1
∼ ∼
CAS
Key
∼ ∼
*Note 3
ADDR
Ra
∼ ∼
WE
∼ ∼
DSF
∼ ∼
DQM
Hi-Z
Hi-Z
MRS New
Command
∼
DQ
New Command
Auto Refresh
: Don′t care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal
mode register.
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Rev. 1.3 (Dec. 2000)
- 45
K4G323222A
CMOS SGRAM
FUNCTION TRUTH TABLE(TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
CS
RAS
CAS
WE
DSF
BA
ADDR
ACTION
NOTE
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
2
L
H
L
X
X
BA
CA
ILLEGAL
2
L
L
H
H
L
BA
RA
Row Active ; Latch Row Address ; Non-IO Mask
L
L
H
L
L
BA
PA
NOP
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
L
X
X
Auto Refresh or Self Refresh
L
L
L
H
H
X
X
ILLEGAL
L
L
L
L
L
OP Code
Mode Register Access
5
L
L
L
L
H
OP Code
Special Mode Register Access
6
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Begin Write ;Latch CA ; Determine AP
L
H
L
L
H
BA
CA,AP
Block Write ;Latch CA ; Determine AP
L
L
H
H
X
BA
RA
ILLEGAL
L
L
H
L
L
BA
PA
Precharge
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
X
X
X
ILLEGAL
L
L
L
L
L
X
X
ILLEGAL
L
L
L
L
H
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
L
L
X
X
Term burst --> Row active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Term burst ; Begin Write ; Latch CA ; Determine AP
3
L
H
L
L
H
BA
CA.AP
Term burst ; Block Write ; Latch CA ; Determine AP
3
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst ; Precharge timing for Reads
3
L
L
H
L
H
X
X
ILLEGAL
OP Code
4
5
2
Begin Read ; Latch CA ; Determine AP
ILLEGAL
2
Special Mode Register Access
6
Term burst ; Begin Read ; Latch CA ; Determine AP
3
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
L
L
X
X
Term burst --> Row active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Term burst ; Begin Write ; Latch CA ; Determine AP
3
L
H
L
L
H
BA
CA,AP
Term burst ; Block Write ; Latch CA ; Determine AP
3
Term burst ; Begin Read ; Latch CA ; Determine AP
3
ILLEGAL
Rev. 1.3 (Dec. 2000)
- 46
K4G323222A
CMOS SGRAM
FUNCTION TRUTH TABLE(TABLE 1, Continued)
Current
State
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Precharging
Block
Write
Recovering
Row
Activating
Refreshing
CS
RAS
CAS
WE
DSF
BA
ADDR
ACTION
NOTE
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst : Precharge timing for Writes
3
L
L
H
L
H
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Precharge)
2
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP --> Idle after tRP
2
L
H
H
H
X
X
X
L
H
H
L
X
X
X
NOP --> Idle after tRP
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
2
L
L
L
X
X
X
X
NOP --> Idle after tRP
ILLEGAL
H
X
X
X
X
X
X
NOP --> Row Active after tBWC
L
H
H
H
X
X
X
L
H
H
L
X
X
X
NOP --> Row Active after tBWC
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
Term Block Write : Precharge timing for Block Write
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP --> Row Active after tRCD
L
H
H
H
X
X
X
L
H
H
L
X
X
X
NOP --> Row Active after tRCD
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
ILLEGAL
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP --> Idle after tRC
L
H
H
X
X
X
X
L
H
L
X
X
X
X
NOP --> Idle after tRC
ILLEGAL
L
L
H
X
X
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
4
Rev. 1.3 (Dec. 2000)
- 47
K4G323222A
CMOS SGRAM
FUNCTION TRUTH TABLE (TABLE 1, Continued)
ABBREVIATIONS
RA = Row Address(A0~A10)
NOP = No Operation Command
BA = Bank Address
CA = Column Address(A0~A7)
PA = Precharge All(A 8)
AP = Auto Precharge(A 8)
*Note : 1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).
5. Illegal if any banks is not idle.
6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE(TABLE 2)
Current
State
Self
Refresh
Both
Bank
Precharge
Power
Down
All
Banks
Idle
CKE
n-1
CKE
n
H
L
CS
RAS
CAS
WE
DSF
ADDR
ACTION
NOTE
X
X
X
X
X
X
X
INVALID
H
H
X
X
X
X
X
Exit Self Refresh --> ABI after tRC
7
L
H
L
H
H
H
X
X
Exit Self Refresh --> ABI after tRC
7
L
H
L
H
H
L
X
X
ILLEGAL
L
H
L
H
L
X
X
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Self Refresh)
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Exit Power Down --> ABI
8
L
H
L
H
H
H
X
X
Exit Power Down --> ABI
8
L
H
L
H
H
L
X
X
ILLEGAL
L
H
L
H
L
X
X
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Power Down Mode)
H
H
X
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
X
Enter Power Down
9
H
L
L
H
H
H
X
X
Enter Power Down
9
H
L
L
H
H
L
X
X
ILLEGAL
H
L
L
H
L
X
X
X
ILLEGAL
H
L
L
L
H
H
L
RA
H
L
L
L
L
H
L
X
H
L
L
L
L
L
L
OP Code
Mode Register Access
Special Mode Register Access
Row (& Bank) Active
Enter Self Refresh
9
H
L
L
L
L
L
H
OP Code
L
L
X
X
X
X
X
X
NOP
H
H
X
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
10
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
10
L
L
X
X
ABBREVIATIONS : ABI = All Banks Idle
X
X
X
X
Maintain clock Suspend
Any State
other than
Listed
Above
*Note : 7. After CKE′s low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE ′s low to high
transition to issue a new command.
8. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time "tSS + one clock" must be satisfied before any command other than exit.
9. Power-down and self refresh can be entered only from the all banks idle state.
10. Must be a legal command.
Rev. 1.3 (Dec. 2000)
- 48
K4G323222A
CMOS SGRAM
PACKAGE DIMENSIONS (TQFP)
Dimensions in Millimeters
0 ~ 7°
17.20 ±
0.20
14.00 ±
0.10
#100
#1
23.20 ± 0.20
0.575
20.00 ± 0.10
0.825
0.30 ± 0.08
0.13 MAX
0.09~0.20
0.65
1.00 ± 0.10
1.20 MAX *
0.10 MAX
0.05 MIN
0.80 ±
0.20
* All Package Dimensions of PQFP & TQFP are same except Height.
- PQFP (Height = 3.0mmMAX)
- TQFP (Height = 1.2mmMAX)
Rev. 1.3 (Dec. 2000)
- 49