ON NTHS4166N Power mosfet 30 v, 8.2 a, single n-channel, chipfet package Datasheet

NTHS4166N
Power MOSFET
30 V, 8.2 A, Single N-Channel,
ChipFETt Package
Features
•Trench Technology
•Low RDS(on) to Minimize Conduction Losses
•Leadless ChipFET Package has 40% Smaller Footprint than TSOP-6
•Excellent Thermal Capabilities
•This is a Pb-Free Device
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V(BR)DSS
RDS(on) Max
ID Max
22 mW @ 10 V
30 V
8.2 A
27 mW @ 4.5 V
Applications
•Load Switching
•DC-DC Converters
•Low Side Switching
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
G
Value
Unit
Drain-to-Source Voltage
VDSS
30
V
Gate-to-Source Voltage
VGS
±20
V
ID
6.6
A
Continuous Drain
Current RqJA (Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
1.5
W
TA = 25°C
ID
4.9
A
Continuous Drain
Current RqJA (Note 2)
TA = 85°C
Steady
State
TA = 25°C
PD
0.8
W
Continuous Drain
Current RqJA, t v 5 s
(Note 1)
TA = 25°C
ID
8.2
A
TA = 85°C
5.9
PD
2.2
W
IDM
32
A
TJ,
TSTG
-55 to
150
°C
IS
2.6
A
Single Pulse Drain-to-Source Avalanche
Energy TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 20 Apk, L = 0.1 mH, RG = 25 W
EAS
20
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Pulsed Drain Current
TA = 25°C
TA = 25°C,
tp = 10 ms
Operating Junction and Storage Temperature
Source Current (Body Diode) RqJF
MARKING DIAGRAM
AND PIN ASSIGNMENT
8
D D D S
466 M
G
1
3.6
Power Dissipation
RqJA (Note 2)
Power Dissipation
RqJA (Note 1)
N-Channel MOSFET
4.8
TA = 85°C
Steady
State
S
ChipFET
CASE 1206A
STYLE 1
1
D D D G
466 = Specific Device Code
M = Month Code
G
= Pb-Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NTHS4166NT1G
ChipFET
(Pb-Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq. pad, 1 oz Cu.
2. Surface Mounted on FR4 Board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2007
December, 2007 - Rev. 0
1
Publication Order Number:
NTHS4166N/D
NTHS4166N
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Unit
Junction-to-Ambient – Steady State (Note 3)
RqJA
86
°C/W
Junction-to-Ambient – t ≤ 5 s (Note 3)
RqJA
57
Junction-to-Ambient – t ≤ 5 s (Note 4)
RqJA
155
Junction-to-Foot (Drain) Steady State (Note 3)
RqJF
20
3. Surface Mounted on FR4 Board using 1 in sq. pad, 1 oz Cu.
4. Surface Mounted on FR4 Board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Units
OFF CHARACTERISTICS
V
18.3
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V, VDS = 30 V
Gate-to-Source Leakage Current
IGSS
VDS = 0 V, VGS = ±20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 mA
Negative Threshold
Temperature Coefficient
VGS(TH)/TJ
TJ = 25°C
mV/°C
1.0
TJ = 125°C
mA
10
±100
nA
2.3
V
ON CHARACTERISTICS (Note 5)
Drain-to-Source On-Resistance
Forward Transconductance
RDS(on)
gFS
1.1
5.5
mV/°C
mW
VGS = 10 V, ID = 4.9 A
18
22
VGS = 4.5 V, ID = 3.7 A
23
27
VDS = 5 V, ID = 4.9 A
9.0
S
900
pF
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
VGS = 0 V, f = 1.0 MHz, VDS = 15 V
210
CRSS
140
Total Gate Charge
QG(TOT)
9.2
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
Total Gate Charge
Gate Resistance
QG(TOT)
VGS = 4.5 V, VDS = 15 V, ID = 4.9 A
nC
0.85
2.86
3.84
VGS = 10 V, VDS = 15 V, ID = 4.9 A
18
RG
1.6
td(on)
12
tr
13
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 4.9 A, RG = 3.0 W
16
tf
5.0
td(on)
8.0
tr
td(off)
VGS = 10 V, VDS = 15 V,
ID = 4.9 A, RG = 3.0 W
tf
11
20
4.0
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
ns
NTHS4166N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
TJ = 25°C
0.83
1.0
V
TJ = 125°C
0.7
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, IS = 5.2 A
16
VGS = 0 V, IS = 5.2 A,
dIS/dt = 100 A/ms
QRR
7.5
8.5
6.0
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
ns
nC
NTHS4166N
TYPICAL PERFORMANCE CURVES
25
15
VDS ≥ 10 V
TJ = 25°C
3.4 V
3.2 V
10
3.0 V
5
2.8 V
0
0.5
1
1.5
2.5
2
TJ = 125°C
5
TJ = 25°C
TJ = -55°C
1
2
3
4
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.085
0.075
0.065
0.055
0.045
0.035
0.025
0.015
2
4
6
8
10
0.030
TJ = 25°C
0.028
0.025
0.023
VGS = 4.5 V
0.020
0.018
VGS = 10 V
0.015
0.013
0.010
5
6
7
8
9
10
11
12
13
14
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate-to-Source
Voltage
Figure 4. On-Resistance vs. Drain Current and
Gate Voltage
10000
1.6
VGS = 0 V
ID = 4.9 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
10
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID = 4.9 A
TJ = 25°C
1.4
15
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.095
0.005
20
0
3
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
0
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
4.5 V
3.6 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
10 V
1.2
1.0
TJ = 150°C
1000
TJ = 125°C
100
0.8
0.6
-50
10
-25
0
25
50
75
100
125
150
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with
Temperature
Figure 6. Drain-to-Source Leakage Current
vs. Drain Voltage
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4
30
NTHS4166N
TYPICAL PERFORMANCE CURVES
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS)
1400
VGS = 0 V
1200
TJ = 25°C
C, CAPACITANCE (pF)
Ciss
1000
800
600
Coss
400
200
Crss
0
0
5
10
15
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
8
4
ID = 4.9 A
TJ = 25°C
0
0
t, TIME (ns)
IS, SOURCE CURRENT (AMPS)
td(off)
100
tf
tr
td(on)
10
6
8
10
12
14
16
18
10
RG, GATE RESISTANCE (OHMS)
VGS = 0 V
4
2
1
0
0.4
100
1
VGS = 20 V
SINGLE PULSE
TC = 25°C
dc
10
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
10 ms
1
0.6
0.8
0.7
1.0
0.9
Figure 10. Diode Forward Voltage vs. Current
1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.5
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
100
10
TJ = 25°C
3
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
I D, DRAIN CURRENT (AMPS)
4
QG, TOTAL GATE CHARGE (nC)
5
VDD = 15 V
ID = 4.9 A
VGS = 10 V
0.01
0.1
2
Figure 8. Gate-To-Source and Drain-To-Source
Voltage vs. Total Charge
1000
0.1
QT
Q2
Q1
2
Figure 7. Capacitance Variation
1
1
VGS
6
20
ID = 20 A
15
10
5
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
150
NTHS4166N
PACKAGE DIMENSIONS
ChipFETt
CASE 1206A-03
ISSUE H
D
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
q
6
L
5
HE
5
6
7
8
4
3
2
1
E
1
2
3
e1
4
b
c
e
A
0.05 (0.002)
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
DIM
A
b
c
D
E
e
e1
L
HE
q
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
MIN
1.00
0.25
0.10
2.95
1.55
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.011
0.014
0.071
0.075
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
SOLDERING FOOTPRINTS*
1
2.032
0.08
2.032
0.08
1
1.727
0.068
2.362
0.093
0.635
0.025
PITCH
2.362
0.093
8X
8X
0.66
0.026
0.457
0.018
2X
2X
mm Ǔ
ǒinches
0.457
0.018
0.66
0.026
Basic
Style 1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NTHS4166N/D
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