512M GDDR3 SDRAM K4J52324QC-B 512Mbit GDDR3 SDRAM Revision 1.0 March 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Revision History Revision 1.0 (March 8, 2005) • Removed -BC10/11/12 from the spec. • Separated VDD spec as below - VDD & VDDQ = 2.0V + 0.1V distinguished by part number as -BJ - VDD & VDDQ = 1.8V + 0.1V distinguished by part number as -BC Accordingly, defined -BJ12/14 and -BC14/16/20 along with supported operating voltage. • Changed tRCDR and tRP of -BC16 from 9tCK and 8tCK to 10tCK and 9tCK. Accordingly, tRCDW/tRC/tDAL changed each from 5tCK/ 27tCK/17tCK to 6tCK/28tCK/18tCK. • Changed tRCDR and tRP of -BC20 from 7tCK and 6tCK to 8tCK and 7tCK. Accordingly, tRCDW/tRC/tDAL changed each from 4tCK/ 21tCK/13tCK to 5tCK/22tCK/14tCK. • Added Vendor ID read timing on page 18 & clock frequency change timing on page 19. • Changed package dimension from 12mm x 14mm to 11mm x 14mm. • DC spec updated. • Capacitance values changed. Input(Clock,Address,Command) capacitance changed from 2.0pF/2.5pF to 1.5pF/3.0pF and DQ,DQS and DM capacitance changed from 2.0pF/2.5pF to 1.5pF/2.0pF. - 2 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Revision History Revision 0.9 (November 11, 2004) • Corrected typo in boundary scan order table. Revision 0.8 (October 10, 2004) • Changed part number from K4J52324QB-G to K4J52324QC-B -Package code attribute re-defined : G .... 144FBGA, Leaded V .... 144FBGA, Lead-free A .... 136FBGA, Leaded B .... 136FBGA, Lead-free Revision 0.7 (October 5, 2004) • DC spec defined. • Comment added on how to change the clock frequency after the power-up (page 14) • Comment added on read to write timing diagram on page 32 which specify the timing interval from data termination enable to the first data-in should be greater than 1tCK. • Changed CL(Cas Latency) of -GC14 from 9tCK to 10tCK . Changed CL(Cas Latency) of -GC16 from 8tCK to 9tCK • Typo corrected in boundary scan order table and additional remark for boundary scan added on page 17. • Changed tDCERR from 0.2tCK to 0.03tCK (Typo) Revision 0.6 (September 15, 2004) • Typo corrected • Removed tWR_A to avoid confusion. Instead, tWR represent write recovery time for both normal precharge and Auto-precharge cases. Accordingly tDAL adjusted by tWR for each frequency. • Clock jitter spec added. • Changed input capacitance. • Fixed CL of -GC12 to 11tCK where as specified with 10tCK or 11tCK previousely. Revision 0.5 (June 4, 2004) • Typo corrected (Package ball out) Revision 0.4 (May 13, 2004) • Changed tRRD from 12ns to 10ns • Added tFAW specification in the spec which defined as five times of tRRD • Added boundary scan specification & added package dimension Revision 0.3 (January 26, 2004) • Changed part number of 512Mb(x32) GDDR3 from K4J53324QB-GC to K4J52324QB-GC Revision 0.2 (January 5, 2004) • Added Write Latency 5, 6, and 7 (clock) in the spec. • Added tWR_A 8 and 9 (clock) in the spec. Revision 0.1 (December 18, 2003) • Changed CL of -GC12 from 9tCK to 10tCK • Changed tCK(max) from 3.0ns to 3.3ns Revision 0.0 (December 18 , 2003) - Target Spec - 3 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B 2M x 32Bit x 8 Banks Graphic Double Data Rate 3 Synchronous DRAM with Uni-directional Data Strobe FEATURES • 2.0V + 0.1V power supply for device operation for -BJ** • Single ended READ strobe (RDQS) per byte • 2.0V + 0.1V power supply for I/O interface for -BJ** • Single ended WRITE strobe (WDQS) per byte • 1.8V + 0.1V power supply for device operation for -BC** • RDQS edge-aligned with data for READs • 1.8V + 0.1V power supply for I/O interface for -BC** • WDQS center-aligned with data for WRITEs • On-Die Termination (ODT) • Data Mask(DM) for masking WRITE data • Output Driver Strength adjustment by EMRS • Auto & Self refresh modes • Calibrated output drive • Auto Precharge option • 1.8V Pseudo Open drain compatible inputs/outputs • 32ms, auto refresh (8K cycle) • 4 internal banks for concurrent operation • 136 Ball FBGA • Differential clock inputs (CK and CK) • Maximum clock frequency up to 800MHz • Commands entered on each positive CK edge • Maximum data rate up to 1.6Gbps/pin • CAS latency : 4, 5, 6, 7, 8, 9, 10, 11 (clock) • DLL for outputs • Additive latency (AL): 0 and 1 (clock) • Boundary scan function with SEN pin • Programmable Burst length : 4 and 8 • Mirror function with MF pin • Programmable Write latency : 1, 2, 3, 4, 5, 6 and 7 (clock) ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4J52324QC-BJ12 800MHz 1.6Gbps/pin K4J52324QC-BJ14 700MHz 1.4Gbps/pin K4J52324QC-BC14 700MHz 1.4Gbps/pin K4J52324QC-BC16 600MHz 1.2Gbps/pin K4J52324QC-BC20 500MHz 1.0Gbps/pin VDD&VDDQ Package 2.0V+0.1V 136 Ball FBGA 1.8V+0.1V * K4J52324QC-A*** is leaded package part number GENERAL DESCRIPTION FOR 2M x 32Bit x 8 Bank GDDR3 SDRAM The K4J52324QC is 536,870,912 bits of hyper synchronous data rate Dynamic RAM organized as 8 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 6.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 4 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B PIN CONFIGURATION Normal Package (Top View) 1 2 3 A VDDQ VDD VSS B VSSQ DQ0 C VDDQ D 4 5 6 7 8 9 10 11 12 ZQ MF VSS VDD VDDQ DQ1 VSSQ VSSQ DQ9 DQ8 VSSQ DQ2 DQ3 VDDQ VDDQ DQ11 DQ10 VDDQ VSSQ WDQS0 RDQS0 VSSQ VSSQ RDQS1 WDQS1 VSSQ E VDDQ DQ4 DM0 VDDQ VDDQ DM1 DQ12 VDDQ F VDD DQ6 DQ5 CAS CS DQ13 DQ14 VDD G VSS VSSQ DQ7 BA0 BA1 DQ15 VSSQ VSS H VREF A1 RAS CKE WE BA2 A5 VREF J VSSA RFU1 RFU2 VDDQ VDDQ CK CK VSSA K VDDA A10 A2 A0 A4 A6 A8/AP VDDA L VSS VSSQ DQ25 A11 A7 DQ17 VSSQ VSS M VDD DQ24 DQ27 A3 A9 DQ19 DQ16 VDD N VDDQ DQ26 DM3 VDDQ VDDQ DM2 DQ18 VDDQ P VSSQ WDQS3 RDQS3 VSSQ VSSQ RDQS2 WDQS2 VSSQ R VDDQ DQ28 DQ29 VDDQ VDDQ DQ21 DQ20 VDDQ T VSSQ DQ30 DQ31 VSSQ VSSQ DQ23 DQ22 VSSQ V VDDQ VDD VSS SEN RESET VSS VDD VDDQ NOTE : 1. RFU1 is reserved for future use 2. RFU2 is reserved for future use - 5 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function Input Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CK and CK should be maintained stable except self-refresh mode. CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during powerdown. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM0 ~DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM pins are input only, the DM loading matches the DQ and WDQS loading. BA0 ~ BA2 Input Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. A0 ~ A11 Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2. The address inputs also provide the op-code during Mode Register Set commands. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto precharge. DQ0 ~ DQ31 Input/ Output Data Input/ Output: Bi-directional data bus. RDQS0 ~ RDQS3 Output READ Data Strobe: Output with read data. RDQS is edge-aligned with read data. WDQS0 ~ WDQS3 Input CK, CK NC/RFU WRITE Data Strobe: Input with write data. WDQS is center-aligned to the inout data. No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply VSSQ Supply DQ Ground VDD Supply Power Supply VSS Supply Ground VDDA Supply DLL Power Supply VSSA Supply DLL Ground VREF Supply Reference voltage: 0.7*VDDQ , 2 Pins : (H12) for Data input , (H1) for CMD and ADDRESS MF ZQ Input Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input. Reference Resistor connection pin for On-die termination. RES Input Reset pin: RESET pin is a VDDQ CMOS input SEN Input Scan enable : Must tie to the ground in case not in use. VDDQ CMOS input. - 6 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Mirror Function The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F5, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0, BA1 and BA2 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4, G9 and H10 respectively and only detects a DC input. The MF ball should be tied directly to VSS or VDD depending on the control line orientation desired. When the MF ball is tied low the ball orientation is as follows, RAS - H3, CAS - F4, WE - H9, CS - F9, CKE - H4, A0 - K4, A1 - H2, A2 - K3, A3 - M4, A4 - K9, A5 - H11, A6 - K10, A7 - L9, A8 - K11, A9 - M9, A10 - K2, A11 - L4, BA0 - G4, BA1 - G9 and BA2 - H10. The high condition on the MF ball will change the location of the control balls as follows; CS - F4, CAS - F9, RAS - H10, WE - H4, CKE - H9, A0 - K9, A1 - H11, A2 - K10, A3 - M9, A4 - K4, A5 - H2, A6 - K3, A7 - L4, A8 - K2, A9 - M4, A10 - K11, A11 - L9, BA0 - G9, BA1 - G4 and BA2 - H3. Mirror Function Signal Mapping MF LOGIC STATE PIN RAS HIGH LOW H10 H3 CAS F9 F4 WE H4 H9 CS F4 F9 CKE H9 H4 A0 K9 K4 A1 H11 H2 A2 K10 K3 A3 M9 M4 A4 K4 K9 A5 H2 H11 A6 K3 K10 A7 L4 L9 A8 K2 K11 A9 M4 M9 A10 K11 K2 A11 L9 L4 BA0 G9 G4 BA1 G4 G9 BA2 H3 H10 - 7 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B BLOCK DIAGRAM (2Mbit x 32I/O x 8 Bank) WDQS Input Buffer 32 Input Buffer I/O Control LWE Data Input Register Serial to parallel LDMi 128 Bank Select 2M x 32 2M x 32 2M x 32 128 32 Output Buffer Sense AMP Row Decoder Refresh Counter Row Buffer ADDR Address Register iCK 2M x 32 4-bit prefetch 2M x 32 x32 DQi 2M x 32 2M x 32 2M x 32 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length LRAS LCBR Strobe Gen. Programming Register LCKE Output DLL RDQS LWE LCAS LWCBR CK,CK LDMi Timing Register iCK CKE CS RAS CAS WE DMi * iCK : internal clock - 8 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B FUNCTIONAL DESCRIPTION Simplified State Diagram Power Applied Power On Self Refresh Precharge PREALL REFS REFSX MRS EMRS MRS Auto Refresh REFA Idle CKEL CKEH Active Power Down ACT Precharge Power Down CKEH CKEL Row Active Read Write Write A Write Write Read A Read Read Read A Write A Read A PRE Write A PRE PRE PRE Read A Precharge PREALL Automatic Sequence Command Sequence PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge - 9 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B INITIALIZATION GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF is applied ) 2. Required minimum 100us for the stable power before RESET pin transition to HIGH - Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE. - On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value. If CKE is sampled at a zero the address termination is set to 1/2 of ZQ. If CKE is sampled at a one the address termination is set to ZQ. - RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will be in a High-Z state, all active terminators off, and all DLLs off. 4. Minimum 200us delay required prior to applying any executable command after stable power and clock. 5. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be brought to HIGH, 6. Issue a PRECHARGE ALL command following after NOP command. 7. Issue a EMRS command (BA1BA0="01") to enable the DLL. 8. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters. 20K clock cycles are required between the DLL to lock. 9. Issue a PRECHARGE ALL command 10 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers. Following these requirements, the GDDR3 SDRAM is ready for normal operation. VDDQ VDD VREF T0 T1 Ta0 Tb0 Tc0 Td0 Te0 Tf0 PRE LMR LMR PRE AR AR ACT CK CK RES t CH tATS t t ATH IS t tCL IH CKE CKE tIS COMMAND t IH NOP DM t IS tIH CODE CODE t IS ALL BANKS A0-A7, A9-A11 ALL BANKS IH CODE A8 t IS t t IS IH CODE RA tIH t BAO=H, BA1 =L BA0, BA1 RA t IS t IH BAO=L, BA1 =L BA High RDQS High WDQS High DQ T = 200us T=10ns Power-up: VDD and CK stable tRP Precharge All Banks Load Extended Mode Register - 10 - tMRD tMRD Load Mode Register DLL Reset tRP Precharge All Banks 20K tRFC 1st Auto Refresh tRFC 2nd Auto Refresh Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3 SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1, BA2 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum clock cycles specified as tMRD are required to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The Burst length uses A0 ~ A1. CAS latency (read latency from column address) uses A2, A6 ~ A4. A7 is used for test mode. A8 is used for DLL reset. A9 ~ A11 are used for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies. BA2 BA1 BA0 A11 A10 A9 RFU 0 0 BA1 BA0 An ~ A0 A7 0 0 MRS 0 Normal 0 1 EMRS 1 Test WL A8 A7 A6 DLL TM A5 A4 CAS Latency A3 A2 BT CL A1 A0 Burst Length Test Mode mode Burst Type A3 DLL A8 0 Write Latency A11 A10 A9 0 0 0 Write Latency Reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 RFU(Reserved for future use) should stay "0" during MRS cycle DLL Reset 0 No 1 Yes Burst Type 0 Sequential 1 Reserved Note : DLL reset is self-clearing Burst Length A1 A0 CAS Latency 0 0 Reserved 8 0 1 Reserved 9 1 0 4 1 1 8 CAS Latency A2 A6 A5 A4 0 0 0 0 0 0 0 1 0 0 1 0 10 0 0 1 1 11 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 Reserved(12) 1 0 0 1 Reserved(13) 1 0 1 0 Reserved(14) 1 0 1 1 Reserved(15) 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved - 11 - Burst Length Rev 1.0 (Mar 2005) 0 512M GDDR3 SDRAM K4J52324QC-B PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times of the desired output impedance. For example, a 240Ω resistor is required for an output impedance of 40 Ω. To ensure that output impedance is one sixth the value of RQ (within 10 %), the range of RQ is 120Ω to 360Ω (20Ω to 60Ω) output impedance. MF,SEN, RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in progress to compensate for variations in voltage supply and temperature. The output impedance updates are transparent to the system. Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during update. To guarantee optimum output driver impedance after power-up, the GDDR3(x32) needs at least 20us after the clock is applied and stable to calibrate the impedance upon power-up. The user may operate the part with less than 20us, but the optimal output impedance is not guaranteed. The value of ZQ is also used to calibrated the internal address/command termination resisters. The two termination values that are selectable during power up are 1/2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ. BURST LENGTH Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when the burst length is set to four (Where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmable burst length applies to both READ and WRITE bursts. BURST TYPE Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit M3. This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition Burst Definition Burst Length 4 8 Starting Column Address Order of Accesses Within a Burst Type= Sequential A2 A1 0 0 A0 0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 1 0 0 4-5-6-7-0-1-2-3 0-1-2-3 NOTE : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be set to zero 2. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block. - 12 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B CAS LATENCY (READ LATENCY) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 4~11 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. CAS Latency Allowable operating frequency (MHz SPEED -12 CL=11 CL=10 ≤ 800 CL=9 - -16 - - - - ≤ 600 - - - ≤ 500 -20 T0 COMMAND READ 0 RDQS DQ ∼ ∼∼ ∼ ∼ ∼ ∼∼ /CK CK T0 COMMAND RDQS DQ READ ∼ ∼∼ ∼ ∼ ∼ ∼∼ /CK CK CL=7 - ≤ 700 -14 CL=8 - T5 T6 T7 NOP NOP NOP T6 T7 T8 NOP NOP NOP T7n CL = 7 T8n CL = 8 Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ DON’T CARE TRANSITIONING DATA - 13 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B WRITE LATENCY The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency can be set from 1 to 7 clocks depending in the operating frequency and desired current draw. When the write latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved states should not be used as unknown operation or incompatibility with future versions may result. T0 T2 T3 NOP NOP T2 T3 T4 NOP NOP NOP T1 T3n /CK CK COMMAND WRITE NOP WL = 3 WDQS DQ T0 COMMAND WDQS DQ WRITE ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ /CK CK T4n WL = 4 Burst Length = 4 in the cases shown DON’T CARE TRANSITIONING DATA - 14 - Rev 1.0 (Mar 2005) TEST MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user. DLL RESET The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0A7 and A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero. After DLL Reset MRS, Power down can not be issued within 10 clock. In case the clock frequency need to be changed after the power-up, 512Mb GDDR3 doesn’t require DLL reset. Instead, DLL should be disabled first before the frequency changed and then change the clock frequency as needed. After the clock frequency changed, there needed some time till clock become stable and then enable the DLL and then 20K cycle required to lock the DLL Clock frequency change sequence after the power-up(example) Command EMRS DLL Disable Wait until clock stable - 15 - EMRS DLL Enable ~ CK,CK ~ 1000Mbps ~ 700Mbps ~ 0 512M GDDR3 SDRAM K4J52324QC-B Any Command 20K cycle for DLL locking time Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0,BA1,BA2 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. The minimum clock cycles specified as tMRD are required to complete the write operation in the extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes. BA2 BA1 BA0 A11 A10 A9 A8 A7 A6 RFU 0 1 Term ID RON AL tWR DLL 0 0 BA0 0 1 An ~ A 0 MRS EMRS A10 Vendor ID 0 Off 1 A4 tWR A3 A2 Termination On A8 ADDR/CMD Termination Termination 0 Default 1 Half of deafult Default value is determined by CKE status at the rising edge of RESET during power-up A0 Driver Strength Drive Strength A6 DLL 0 Enable A1 A0 1 Disable 0 0 Autocal 0 1 30Ω 1 0 40Ω 1 1 50Ω Additive Latency A11 A1 DLL Vendor ID BA1 A5 AL 0 0 1 1 Data Termination Ron of Pull-up A9 RON 0 40Ω tWR 1 60Ω A7 RFU(Reserved for future use) should stay "0" during EMRS cycle Driver Strength A5 A4 tWR 0 0 0 11 0 0 1 13 0 1 0 5 0 1 1 6 1 0 0 7 1 0 1 8 1 1 0 9 1 1 1 10 A3 A2 0 0 Termination ODT Disabled*1 0 1 Reserved 1 0 ZQ/4 1 1 ZQ/2 * ZQ : Resistor connection pin for On-die termination * 1 : ALL ODT will be disabled - 16 - Rev 1.0 (Mar 2005) 0 512M GDDR3 SDRAM K4J52324QC-B DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before a READ command can be issued. DATA TERMINATION The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SDRAM supports 60Ω and 120Ω termination. The termination may also be disabled for testing and other purposes. DATA DRIVER IMPEDANCE The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When autocalibration is used the data driver impedance is set to 40Ωs and it’s tolerance is determined by the calibration accuracy of the device. When any other value is selected the target impedance is set nominally to the desired impedance. However, the accuracy is now determined by the device’s specific process corner, applied voltage and operating temperature. ADDITIVE LATENCY The Additive Latency function (AL) is used to optimize the command bus efficiency. The AL value is used to determine the number of clock cycles that is to be added to CL after CAS is captured by the rising edge of CK. Thus the total CAS latency is determined by adding CL and AL. MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A10 set to one, and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers vendor code on DQ[3:0] and revision identification on DQ[7:4] Manufacturer DQ[3:0] Manufacturer DQ[3:0] Manufacturer DQ[3:0] Reserved 0 Hynix 6 Reserved C Samsung 1 Mosel 7 Reserved D Infineon 2 Winbond 8 Reserved E 3 ESMT 9 Micron F Etron 4 Reserved A Nanya 5 Reserved B Elpida - 17 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Vendor ID Read T0 T1 Ta2 Tb3 Tc4 Td5 Te6 Tf7 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CK tCH ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ RES ~ ~ CK tCL ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ CKE ~ ~ ~ ~ CKE ~ ~ tIS tIH ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ MRS EMRS ~ ~ ~ ~ ~ ~ EMRS PRE COMMAND ~ ~ tIS tIH 200 cycle High Precharge All Banks ~ ~ ~ ~ ~ ~ ~ ~ >20ns ~ ~ >20ns ~ ~ DQ[3:0] tRP tMRD tMRD tMRD tRP Vendor Code EMRS Vendor_ID Off EMRS Vendor_ID On DON’T CARE - 18 - MRS Precharge All Banks 1st Auto Refresh TRANSITIONING DATA Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Clock frequency change sequence during the device operation Both existing tCK and desired tCK are in DLL-On mode - Change frequency from existing frequency to desired frequency - Issue Precharge All Banks command - Issue MRS command to reset the DLL while other fields are valid and required 20K tCK to lock the DLL - Issue Precharge All Banks command. Issue at least Auto-Refresh command NOP NOP Frequency Change PRE All Banks Precharge tFCHG MRS NOP AR NOP All Banks Precharge DLL Reset tRP PRE ∼ NOP ∼ NOP ∼ NOP ∼ NOP ∼ CMD ∼ CK ∼ CK tMRD 20tCK (DLL locking time) Existing tCK is in DLL-on mode while desired tCK is in DLL-off mode - Issue Precharge All Banks command - Issue EMRS command to disable the DLL - Issue Precharge All Banks command - Change the frequency from existing to desired. - Issue Auto-Refresh command at least two. Issue MRS command EMRS PRE All Banks Precharge DLL OFF All Banks Precharge tRP NOP NOP NOP AR ∼ PRE ∼ CMD ∼ CK ∼ CK MRS NOP NOP NOP NOP Frequency Change tMRD tFCHG Clock frequency change in case existing tCK is in DLL-off mode while desired tCK is in DLL-on mode - Issue Precharge All Banks command and issue EMRS command to disable the DLL. - Issue Precharge All Banks command. - Change the clock frequency from existing to desired - Issue Precharge All Banks command. - Issue EMRS command to enable the DLL - Issue MRS command to reset the DLL and required 20K tCK to lock the DLL. - Issue Precharge All Banks command. - Issue Auto-Refresh command at least two tFCHG tRP - 19 - DLL On MRS DLL Reset tMRD PRE NOP ∼ All Banks Precharge EMRS ∼ PRE ∼ Frequency Change NOP ∼ tMRD NOP ∼ All Banks Precharge NOP ∼ tRP DLL OFF PRE ∼ All Banks Precharge EMRS ∼ PRE ∼ CMD ∼ CK CK AR All Banks Precharge tMRD 20tCK (DLL locking time) Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B BOUNDARY SCAN FUNCTION GENERAL INFORMATION The 512Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn’t operate in accordance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located at V-4 of 136 ball package. For the normal device operation other than boundary scan, there required device re-initialization by device power-off and then power-on. DISABLING THE SCAN FEATURE It is possible to operate the 512Mb GDDR3 without using the boundary scan feature. SEN(at V-4 of 136 ball package) should be tied LOW(VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS# will be operating at normal GDDR3 functionalities when SEN is deasserted. Figure 1. Internal Block Diagram (Reference Only) Dedicated Scan Flops (1per signal under test) Tie to Iogic 0 DM0 D DQ CK Pins under test DQS D DQ CK DQ4 D DQ CK The following lists the rest of the signals on the scan chain: DQ[3:0], DQ[31:6], RDQS[3:1], WDQS[3:1], DM[3:1], RFU, CAS#, WE#, CKE, BA[2:0], A[11:0], CK, CK# and ZQ Two RFU’s(I-2 and J-3 on 136-ball package) will be on the scan chain and will read as a logic "0" RDQS0 RES (SSH,Scan Shift) The following lists signals not on the scan chain: NC, VDD, VSS, VDDQ, VSSQ, VREF D DQ CK In case ZQ pin is connected to the external resistor, it will be read as logic "0". However, if the ZQ pin is open, it will be read as floating. Accordingly, ZQ pin should be driven by any signal. CS# (SCK, Scan Clock) WDQS0 (SOUT,Scan Out) RFU at V-4 (SEN, Scan Enable) Puts device into scan mode and re-maps pins to scan functionality MF (SOE#, Output Enable) - 20 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B BOUNDARY SCAN EXIT ORDER BIT# BALL BIT# BALL 1 2 BIT# BALL BIT# BALL BIT# D-3 13 E-10 25 C-2 14 F-10 26 3 C-3 15 E-11 27 K-9 4 B-2 16 G-10 28 M-9 40 T-3 52 5 B-3 17 F-11 29 M-11 41 T-2 53 6 A-4 18 G-9 30 L-10 42 R-3 54 7 B-10 19 H-9 31 N-11 43 R-2 8 B-11 20 H-10 32 M-10 44 P-3 BALL BIT# BALL K-11 37 R-10 49 K-10 38 T-11 50 L-3 61 G-4 M-2 62 39 T-10 51 M-4 F-4 63 F-2 K-4 64 G-3 K-3 65 E-2 K-2 66 F-3 55 L-4 67 E-3 56 J-3 9 C-10 21 H-11 33 N-10 45 P-2 57 J-2 10 C-11 22 J-11 34 P-11 46 N-3 58 H-2 11 D-10 23 J-10 35 P-10 47 M-3 59 H-3 12 D-11 24 L-9 36 R-11 48 N-2 60 H-4 *Note : 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the condinuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. Two RFU balls(#57and #58) in the scan order, will be read as a logic"0". SCAN PIN DESCRIPTION Package Ball Symbol Normal Function Type V-9 SSH RES Input Scan shift. Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. F-9 SCK CS Input Scan Clock. Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock. D-2 SOUT WDQS0 Output V-4 A-9 SEN SOE RFU MF Description Scan Output. Input Scan Enable. Logic HIGH would enable the device into scan mode and will be disabled at logic LOW. Must be tied to GND when not in use. Input Scan Output Enable. Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor (tyically 1K Ω ) for normal operation. Tester needs to overdrive this pin gurarantee the required input logic level in scan mode. *Note : 1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies to both user commands and manufacturing commands which may exist while RES is deasserted. 2. All scan functionalities are valid only after the appropriate power-up and initialization sequesnce. (RES and CKE, to set the ODT of the C/A) 3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ’s will be disabled. It is not necessary for the termination to be calibrated. 4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE’s should be provided to top and bottem devices to access the scanned output. When either of the devices is in scan mode, SOE for the other device which not in a scan will be disabled. - 21 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B SCAN DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage PARAMETER/CONDITON VIH(DC) VREF+0.15 - V 1,2 Input Low (Logic 0) Voltage VIL(DC) - VREF-0.15 V 1,2 *Note : 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. Figure 2. Scan Capture Timing Not a true clock, but a single pulse or series of pulses SCK tSES SEN SSH LOW tSCS SOE tSDS tSDS Pins under Test VALID DON’T CARE Figure 3.Scan Shift Timing SCK tSES SEN tSCS SSH tSCS SOE SOUT tSAC Scan Out bit 0 Scan Out bit 1 Scan Out bit 2 Scan Out bit 3 tSOH TRANSITIONING DATA - 22 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B SCAN AC ELECTRICAL CHARACTERISTICS PARAMETER/CONDITON SYMBOL MIN MAX UNITS NOTES tSCK 40 - ns 1 tSES 20 - ns 1,2 Scan enable hold time tSEH 20 - ns 1 Scan command setup time for SSH, SOE# and SOUT tSCS 14 - ns 1 Scan command hold time for SSH, SOE# and SOUT tSCH 14 - ns 1 Scan capture setup Time tSDS 10 - ns 1 Scan capture hold Time tSCH 10 - ns 1 Scan clock to valid scan output tSAC - 6 ns 1 Scan clock to scan output hold tSOH 1.5 - ns 1 Clock Clock cycle time Scan Command Time Scan enable setup time Scan Capture Time Scan Shift Time *Note : 1. The parameter applies only when SEN is asserted. 2. Scan Enable should be issued earlier than other Scan Commands by 3ns. Figure 4. Scan Initialization Sequence ∼ ∼ ∼ tSCH tSCS tSCH tSES tSCS tSCS ∼ ∼ ∼ ∼ ∼ ∼ ∼ VALID ∼ ∼ ∼ ∼ ∼ ∼ VALID tSDS tSDH ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ SOE# ∼ SCK ∼ SEN tSCS tSDS tSDH ∼ ∼ ∼ ∼ ∼ ∼ CKE (Quad-load C/A) tATS tATS ∼ ∼ CKE (Dual-load C/A) ∼ RES (SSH in Scan Mode) ∼ VREF ∼ VDDQ ∼ ∼ ∼ ∼ VDD SOUT Scan Out Bit0 tSDS tSDH VALID ∼∼ ∼∼ ∼ ∼ Pins Under Test T = 200us RESET at power - up Boundary Scan Mode Note : To set the pre-defined ODT for C/A, a boundary scan mode should be issued after an appropriate ODT initialization sequence with RES and CKE signals - 23 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B COMMANDS Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information. TRUTH TABLE - COMMANDs Name (Function) CS RAS CAS WE ADDR NOTES DESELECT (NOP) H X X X X 8, 11 NO OPERATION (NOP) L H H H X 8 ACTIVE (Select bank and activate row) L L H H Bank/Row 3 READ (Select bank and column, and start READ burst) L H L H Bank/Col 4 WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X 6, 7 LOAD MODE REGISTER L L L L Op-Code 2 DATA TERMINATOR DISABLE X H L H X TRUTH TABLE - DM Operation Name (Function) DM DQS Write Enable L Valid Write Inhibit H X Note : NOTES 10 1. CKE is HIGH for all commands except SELF REFRESH. 2. BA0~BA1 select either the mode register or the extended mode register (BA0=0, BA1=0 select the mode register; BA0=1, BA1=0 select extended mode register; other combinations of BA0~BA1 are reserved). A0~A11 provide the op-code to be written to the selected mode register. 3. BA0~BA2 provide bank address and A0~A11 provide row address. 4. BA0~BA2 provide bank address; A0~A7 and A9 provide column address; A8 HIGH enables the auto precharge feature (nonpersistent) , and A8 LOW disables the auto precharge feature. 5. A8 LOW : BA0~BA2 determine which bank is precharged. A8 HIGH : All banks are precharged and BA0~BA2 are "Don’t Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; ll inputs and I/Os are "Don’t Care" except for CKE. 8. DESELECT and NOP are functionally interchangeable. 9. Cannot be in powerdown or self-refresh state. 10. Used to mask write data ; provided coincident with the corresponding data. 11. Except DATA Termination disable. - 24 - Rev 1.0 (Mar 2005) 0 512M GDDR3 SDRAM K4J52324QC-B DESELECT The DESELECT function (/CS high) prevents new commands from being executed by the DDR(x32). The GDDR3(x32) SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The Load Mode Register command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,BA1, BA2 inputs selects the bank, and the address provided on inputsA0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1, BA2 inputs selects the bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE ,V The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1, BA2 inputs selects the bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on inputs A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW. the corresponding data will be written to memory; If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one banks are to be precharged, inputs BA0,BA1,BA2 select the bank. Otherwise BA0, BA1,BA2 are treated as "Don’t Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command will be treated as a NOP if there is no open row is already in the process of precharging. - 25 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enable or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid state within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS(min), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time(tRP) is completed. AUTO REFRESH Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don’t Care" during an Auto Refresh command. The 512Mb(x32) GDDR3 requires Auto Refresh cycles at an average interval of 3.9us (maximum). A maximum Auto Refresh commands can be posted to any given GDDR3(x32) SDRAM, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 3.9us(35.1us). This maximum absolute interval is to allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes. SELF REFRESH The SELF REFRESH command can be used to retain data in the GDDR3(x32) SDRAM ,even if the rest of the system is powered down. When in the self refresh mode,the GDDR3(x32) SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The active termination is also disabled upon entering Self Refresh and enabled upon exiting Self Refresh. (20K clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don’t Care" during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and /CK must be stable prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands issued for tXSNR because tine is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and out-put calibration is to apply NOPs for 20K clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. DATA TERMINATOR DISABLE (BUS SNOOPING FOR READ COMMAND) The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands excluding /CS. The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators are disable CL-1 Clocks after the READ command is detected. In a two rank system both dram devices will snoop the bus for READ commands to either device and both will disable their terminators if a READ command is detected. The command and address terminators and always enabled. - 26 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B ON-DIE TERMINATION Bus snooping for READ commands other than /CS is used to control the on-die termination in the dual load configuration. The GDDR3 SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of /CS, when the ODT for the DQ pins are set for dual loads (120Ω). The on-die termination is disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2 + 2, as below figure, Data Termination Disable Timing. In a two-rank system, both DRAM devices snoop the bus for READ commands to either device and both will disable the on-die termination if a READ command is detected. The on-die termination for all other pins on the device are always on for both a single-rank system and a dual-rank system. The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on the first transition of RESET. On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to be a single-rank system. The on-die termination is then set to one-half ZQ for the address pins. On the rising edge of RESET, if CKE is sampled HIGH, then the configuration is determined to be a dual-rank system. The on-die termination for the DQs, WDQS, and DM pins is set in the EMRS. Data Termination Disable Timing T0 T7 T8 T8n NOP NOP T9 T9n T10 T11 NOP NOP ∼ ∼ ∼ ∼ CK# CK ∼ ∼ READ ADDRESS Bank a, Col n NOP ∼ ∼ COMMAND ∼ ∼ ∼ ∼ ∼ ∼ CL = 8 RDQS ∼ ∼ DQ DQ TERMINATION DO n GDDR3 Data Termination is Disabled DON’T CARE TRANSITIONING DATA Note : 1. DO n = data-out from column n. 2. Burst length = 4. 3. Three subsequent elements of data-out appear in the specified order following DO n. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high one-half cycle prior to the first falling edge. 6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2 7. READS to either rank disable both ranks’ termination regardless of the logic level of /CS. - 27 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B OPERATIONS BANK/ROW ACTIVATION /CK CK Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD(min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command in which a READ or WRITE command can be entered. For example, a tRCD specification of 16ns with a 800MHz clock (1.25ns period) results in 12.8 clocks rounded to 13. This is reflected in below figure, which covers any case where 12<tRCD(min)/tCK≤ 13. The same procedure is used to convert other specification limits from tome units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed"(precharged). The minimum time interval between successive ACTIVE commads to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. CKE HIGH /CS /RAS /CAS /WE A0-A11 RA BA0,1,2 BA RA = Row Address BA = Bank Address Activating a Specific Row in a Specific Bank Example : Meeting tRCD T1 T2 T3 T4 COMMAND ACT NOP NOP ACT NOP A0-A11 Row Row Bank x Bank y T12 T13 T14 NOP RD/WR NOP ∼ ∼ T0 /CK ∼ ∼ CK ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ BA0~BA2 Col Bank y tRRD tRCD DON’T CARE - 28 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B READs READ bursts are initiated with a READ command, as below figure. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is prechrged at the completion of the burst after tRAS(min) has been met. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS Latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative strobe edge. READ burst figure shows general timing for 2 of the possible CAS latency settings. The GDDR3(x32) drives the output data edge aligned to the crossing of CK and /CK and to RDQS. The initial HIGH transitioning LOW of RDQS is known as the read preamble ; the half cycle coincident with the last data-out element is known as the read postamble. /CK CK CKE HIGH /CS /RAS /CAS /WE Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tDV (data-out window hold), the valid data window are depicted in Data Output Timing (1) figure. A detailed explanation of tAC (DQS and DQ transition skew to CK) is shown in Data Output Timing (2) figure. Data from any READ burst may be concatenated with data from a subsequent READ command. A continuous flow of data can be maintained. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals the number of data element nibbles (nibbles are required by the 4n-prefetch architecture) depending on the burst length. This is shown in consecutive READ bursts figure. Nonconsecutive read data is shown for illustration in nonconsecutive READ bursts figure. Full-speed random read accesses within a page (or pages) can be performed as shown in Random READ accesses figure. Data from a READ burst cannot be terminated or truncated. During READ commands the GDDR3 Dram disables its data terminators. A0-A7, A9 CA A10, A11 EN AP A8 DIS AP BA0,1,2 BA CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON’T CARE READ Command - 29 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Data Output Timing (1) - tDQSQ, tQH and Data Valid Window T0 T1 T2 T2n T3 T3n T4 CK# CK tCH tCH tDQSQ2 (MAX) tDQSQ2 (MAX) 2 RDQS tDQSQ2 (MIN) tDQSQ (MIN) 1.6 tDQSH4 DQ(Last data valid) tDQSH4 T2 DQ(First data no longer valid) T2 All DQs and RDQS, collectively5 T3 T2n T3n T3 T2n T3n T2 T2n T3 T3n tDV4 tDV4 tDV4 tDV4 Data Output Timing (2) - tDQSQ, tQH and Data Valid Window T0 T1 T2 T2n T3 T3n tDQSH4 tDQSH4 T2n T3 T4 CK# CK tCH tCH tAC(MAX) RDQS 1.6 All DQs and RDQS, collectively5 T2 RDQS 1.6 T3n tAC(MIN) All DQs and RDQS, collectively5 T2 tDQSH4 tDQSH4 T2n T3 T3n Note : 1. tDQSQ represents the skew between the 8 DQ lines and the respective RDQS pin. 2. tDQSQ is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends with the last valid transition of DQs. 3. tAC is show in the nominal case 4. tDQHP is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active. 5. The data valid window is derived for each RDQS transitions and is defined by tDV. 6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31. 7. This diagram only represents one of the four byte lanes. 8. tAC represents the relationship between DQ, RDQS to the crossing of CK and /CK. - 30 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B READ Burst T0 NOP NOP ADDRESS Bank a, Col n CL = 8 RDQS DQ ∼∼ ∼ ∼∼ ∼ READ ∼ ∼ COMMAND T0 T8n T9 T9n READ ADDRESS Bank a, Col n CL = 9 ∼ ∼∼ ∼ ∼ ∼ ∼ ∼ COMMAND NOP T11 NOP NOP T10 T11 NOP NOP DO n T7 T8 T9 NOP NOP NOP T9n DO n DON’T CARE NOTE : T10 ∼ ∼ /CK CK DQ T8 ∼ ∼ /CK CK RDQS T7 TRANSITIONING DATA 1. DO n=data-out from column n. 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Shown with nominal tAC and tDQSQ. 5. RDQS will start driving high 1/2 clock cycle prior to the first falling edge. - 31 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Consecutive READ Bursts T2 T0 Bank a, Col n RDQS CL = 8 T8 NOP NOP ∼ ∼ ∼ ∼ DQ Bank a, Col b T7 T8n T9 T9n NOP T10 T10n NOP ∼∼ ∼∼ ADDRESS READ ∼ ∼ ∼ ∼ READ ∼ ∼∼ ∼ COMMAND ∼ ∼ ∼ ∼ /CK CK DO b DO n DON’T CARE TRANSITIONING DATA NOTE :1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Three subsequent elements of data-out appear in the programmed order following DQ b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. - 32 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Nonconsecutive READ Bursts T0 NOP NOP ∼ ∼ ∼ ∼ ∼ ∼ READ NOP ADDRESS Bank a, Col n T8 NOP READ T8n T9 T10 NOP NOP T10n T11 NOP Bank a, Col b ∼ ∼ DQ T18 DO b T7 ∼∼ ∼∼ COMMAND /CK CK ∼ ∼ ∼ ∼ T1 RDQS NOP DO n T0 CL = 8 READ Bank a, Col b ∼ ∼ DQ T17n ∼ ∼ RDQS T17 ∼ ∼ CL = 8 T10 ∼ ∼ Bank a, Col n NOP T9n ∼ ∼ ADDRESS NOP T9 ∼ ∼ READ T8n ∼∼ ∼∼ COMMAND T8 ∼ ∼ ∼ ∼ /CK CK T7 DO b DO n DON’T CARE TRANSITIONING DATA NOTE : 1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Three subpsequent elements of data-out appear in the programmed order following DQ b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. - 33 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Random READ Accesses T1 T2 COMMAND READ NOP NOP ADDRESS Bank a, Col n /CK CK T8 ∼ ∼ ∼ ∼ T0 RDQS ∼∼ ∼∼ DQ ∼ ∼ Bank a, Col b CL = 8 COMMAND READ NOP ADDRESS Bank a, Col n /CK CK CL = 8 RDQS DO n T8 READ NOP T9n T10 NOP DO n T8n T10n NOP DO n T9 DO n T9n DO b T10 NOP T10n NOP Bank a, Col b DO n DON’T CARE NOTE : T9 NOP T7 ∼ ∼ DQ ∼∼ ∼∼ T1 ∼ ∼ ∼ ∼ T0 T8n DO n DO n DO n DO b TRANSITIONING DATA 1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g). 2. Burst length = 4 3. n’ or x or b’ or g’ indicates the next data-out following DO n or DO x or DO b OR DO g, respectively 4. READs are to an active row in any bank. 5. Shown with nominal tAC and tDQSQ. 6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. - 34 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B READ to WRITE COMMAND READ ADDRESS Bank Col n RDQS ∼ ∼ ∼ ∼∼ ∼ ∼ ∼ T0 /CK CK T7 T8 T8n NOP WRITE T9 T9n NOP T10 T11 T12 NOP NOP NOP T12n Bank a, Col b CL = 8 tWL = 4 DQ ∼∼ ∼∼ WDQS DM ∼ ∼ DQ Termination DI b DO n ∼ ∼ DQ Termination Disabled 1tCK < DON’T CARE NOTE : DQ Termination Enbaled TRANSITIONING DATA 1. DO n = data-out from column n. 2. DI b = data-in from column b. 3. Burst length = 4 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC and tDQSQ. 7. tDQSS in nominal case. 8. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. 9. The gap between data termination enable to the first data-in should be greater than 1tCK - 35 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B READ to PRECHARGE T1 T2 COMMAND READ NOP PRE ADDRESS Bank a, Col n Bank a, (a or all) T8 ∼ ∼ ∼ ∼ ∼ ∼ T0 /CK CK RDQS ∼ ∼ DQ ∼ ∼ CL = 8 T1 COMMAND READ NOP ADDRESS Bank a, Col n /CK CK ∼ ∼ ∼ ∼ ∼ ∼ T0 T8n NOP T9 NOP T9n T10 ACT Bank a, Row tRP DO n T7 T8 T8n PRE NOP Bank a, (a or all) T9 T10 NOP ACT Bank a, Row tRP RDQS ∼ ∼ DQ ∼ ∼ CL = 8 DO n DON’T CARE TRANSITIONING DATA NOTE : 1. DO n (or b) = data-out from column n (or column b). 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. 4. Three subsequent elements of data-out appear in the programmed order following DQ b. 5. Shown with nominal tAC and tDQSQ. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. 7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS. - 36 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered in a rising edge of WDQS following the WRITE latency set in the mode register and subsequent data elements will be registered on successive edges of WDQS. Prior to the first valid WDQS edge a half cycle is needed and specified as the WRITE Preamble; the half cycle in WDQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first valid falling edge of WDQS (tDQSS) is specified with a relative to the write latency. All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS(min) and tDQSS(max)) might not be intuitive, they have also been included. Write Burst figure shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may not be truncated with a subsequent WRITE command. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command after the burst has completed. The new WRITE command should be issued x cycles after the first WRITE command should be equals the number of desired nibbles (nibbles are required by 4n-prefetch architecture). An example of nonconsecutive WRITEs is shown in Nonconsecutive WRITE to READ figure. Full-speed random write accesses within a page or pages can be performed as shown in Random WRITE cycles figure. Data for any WRITE burst may be followed by a subsequent READ command. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE the WRITE burst, tWR should be met as shown in WRITE to PRECHARGE figure. Data for any WRITE burst can not be truncated by a subsequent PRECHARGE command. - 37 - /CK CK CKE HIGH /CS /RAS /CAS /WE A0-A7, A9 CA A10, A11 EN AP A8 DIS AP BA0,1,2 BA CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON’T CARE WRITE Command Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B WRITE Burst T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS Bank a, Col b T3n T4 T4n T5 T5n T6 /CK CK tDQSS(NOM) NOP NOP NOP tDQSS WDQS DI b DQ DM tDQSS(MIN) tDQSS WDQS DI b DQ DM tDQSS(MAX) tDQSS WDQS DI b DQ DM DON’T CARE NOTE : TRANSITIONING DATA 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. A burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled). 5. Write latency is set to 4 - 38 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Consecutive WRITE to WRITE T0 T1 T2 T3 COMMAND WRITE NOP WRITE NOP ADDRESS Bank Col b T3n T4 T4n T5 T5n T6 T6n T7 CK# CK NOP NOP NOP NOP Bank Col n tDQSS (NOM) WDQS DQ DI b DI n DM DON’T CARE NOTE : TRANSITIONING DATA 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. Burst of 4 is shown. 5. Each WRITE command may be to any bank of the same device. 6. Write latency is set to 3 - 39 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Nonconsecutive WRITE to WRITE T0 T1 T2 T3 COMMAND WRITE NOP NOP WRITE ADDRESS Bank, Col b T3n T4 T4n T5 T5n T6 T6n T7 /CK CK NOP NOP NOP NOP Bank, Col n tDQSS (NOM) WDQS DQ DI b DI n DON’T CARE DM DON’T CARE NOTE : TRANSITIONING DATA 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. burst of 4 is shown. 5. Each WRITE command may be to any bank. 6. Write latency is set to 3 - 40 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Random WRITE Cycles T0 T1 T2 T3 COMMAND WRITE NOP WRITE NOP ADDRESS Bank Col b T3n T4 T4n T5 T5n T6 T6n T7 /CK CK WRITE Bank Col x NOP NOP NOP Bank Col g tDQSS (NOM) WDQS DQ DI b DI b DI b DI b DI x DI x DI x DI x DI g DI g DM DON’T CARE NOTE : TRANSITIONING DATA 1. DI b, etc. = data-in for column b, etc. 2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order. 3. Programmed burst length = 4 cases shown. 4. Each WRITE command may be to any bank. 5. Last write command will have the rest of the nibble on T8 and T8n 6. Write latency is set to 3 - 41 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B WRITE to READ T2 T3 COMMAND WRITE NOP WRITE NOP ADDRESS Bank Col b T3n T4 T4n T5 T6 NOP NOP CK NOP Bank Col b tCDLR = 5 tDQSS (NOM) tDQSS WDQS DI b DQ DM RDQS T19 NOP NOP T19n CL = 8 DI n RDQS ∼ ∼∼∼ ∼ ∼∼∼ DM tDQSS DI n CL = 8 DI b DM RDQS ∼ ∼ ∼ ∼∼ ∼∼ ∼ ∼ ∼ ∼ ∼∼ ∼∼ ∼ WDQS NOTE : T18 CL = 8 DI b DQ DQ Bank a. Col n tDQSS WDQS tDQSS (MAX) READ ∼ ∼∼∼ ∼ ∼∼∼ tDQSS (MIN) T10 ∼ ∼ ∼∼ ∼ ∼ ∼∼ ∼ ∼ ∼∼ ∼ ∼ ∼∼ T1 ∼ ∼ ∼∼ ∼ ∼ ∼∼ ∼ ∼ ∼∼ ∼ ∼ ∼∼ T0 /CK DI n DON’T CARE TRANSITIONING DATA 1. DI b = data-in for column b. 2. Three subsequent elements of data-in the programmed order following DI b. 3. A burst of 4 is shown. 4. tCDLR is referenced from the first positive CK edge after the last data-in pair. 5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices, in which case tCDLR is not required and the READ command could be applied earlier. 6. A8 is LOW with the WRITE command (auto precharge is disabled). 7. WRITE latency is set to 3 - 42 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B WRITE to PRECHARGE T1 T2 T3 COMMAND WRITE NOP WRITE NOP ADDRESS Bank Col b T3n T4 T4n T5 CK tDQSS (NOM) NOP Bank Col b DM T10 T11 NOP tWR PRE NOP tRP NOP ∼ ∼ ∼ ∼ ∼ ∼ DI b DQ DM tDQSS ∼ ∼ ∼ ∼ ∼ ∼ WDQS DI b DM DON’T CARE NOTE : Bank (a or all) tDQSS WDQS DQ T9 ∼ ∼ ∼ ∼ ∼ ∼ DI b DQ tDQSS (MAX) T8 tDQSS WDQS tDQSS (MIN) NOP ∼ ∼ ∼ ∼ ∼ ∼ T0 /CK TRANSITIONING DATA 1. DI b = data-in for column b. 2. Three subsequent elements of data-in the programmed order following DI b. 3. A burst of 4 is shown. 4. A8 is LOW with the WRITE command (auto precharge is disabled). 5. WRITE latency is set to 3 - 43 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B PRECHARGE /CK The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1, BA2 select the bank. When all banks are to be precharged, inputs BA0, BA1, BA2 are treated as "Don’t Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to the bank. CK CKE HIGH /CS /RAS /CAS POWER-DOWN (CKE NOT ACTIVE) Unlike SDR SDRAMs,GDDR3(x32) SDRAM requires CKE to be active at all times an access is in progress; from the issuing of a READ or WRITE command until completion of the burst. For READs, a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst completion is defined BL/2 cycles after the Write Postamble is satisfied. /WE A0-A7, A9-A11 ALL BANKS A8 ONE BANK Power-down is entered when CKE is registered LOW. If power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK,/CK and CKE. For maximum power savings, the user has the option of disabling the DLL prior to entering powerdown. However, power-down duration is limited by the refresh requirements of the device, so in most applications,the self-refresh mode is preferred over the DLL-disabled power-down mode. BA0,1,2 BA DON’T CARE BA=Bank Address (if A8 is LOW; otherwise "Don’t Care") PRECHARGE Command When in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the GDDR3 SDRAM, while all other input signals are "Don’t Care" except data terminator disable command. The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied tPDEX later. Power-Down T0 T1 Ta0 T2 Ta1 Ta2 Ta7 /CK CK tIS tIS tPDEX CKE COMMAND VALID No PEAD/WRITE access in progress NOP NOP * Enter power - down mode NOP VALID Exit power - down mode * Once the device enters the power down mode, it should be in NOP state at least for 10ns - 44 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B GDDR3 tFAW Definition For eight bank GDDR3 devices, there is a need to limit the number of activates in a rolling window to ensure that the instanteous current supplying capability of the devices is not exceeded. To reflect the true capability of the DRAM instantaneous current supply, the same parameter tFAW(four activate window) as DDR2 is defined. Eight bank device Sequential Bank Activation Restriction : No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW(ns) by tCK(ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clocks N+1 through N+9. CLK CMD ACT ACT tRRD ACT tRRD ACT ACT tRRD ACT tRRD ACT tRRD ACT tRRD tFAW tFAW + 3*tRRD - 45 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B TRUTH TABLE - Clock Enable (CKE) CKEn-1 CKEn L L L H CURRENT STATE COMMANDn ACTIONn NOTES Power-Down X Maintain Power-Down Self Refresh X Maintain Self Refresh Power-Down DESELECT or NOP Exit Power-Down Self Refresh DESELECT or NOP Exit Self Refresh All Banks Idle DESELECT or NOP Precharge Power-Down Entry Bank(s) Active DESELECT or NOP Active Power-Down Entry All Banks Idle AUTO REFRESH Self Refresh Entry H L 5 NOTES : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR2(x32) immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn 4. All state and sequence not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSA period. - 46 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK n CURRENT STATE Any /CS /RAS /CAS /WE COMMAND/ ACTION NOTES H X X X DESELECT (NOP/ continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) X H L H DATA TERMINATOR DISABLE L L H H ACTIVE (Select and activate row) L L L H AUTO REFRESH 7 L L L L LOAD MODE REGISTER 7 L H L H READ (Select column and start READ burst) 10 L H L L WRITE (Select Column and start WRITE burst) 10 L L H L PRECHARGE (Deactivate row in bank or banks) 8 L H L H READ (Select column and start new READ burst) 10 L H L L WRITE (Select column and start WRITE burst) L L H L PRECHARGE (Only after the READ burst is complete) L H L H READ (Select column and start READ burst) L H L L WRITE (Select column and start new WRITE burst) L L H L PRECHARGE (Only after the WRITE burst is complete) Idle Row Active Read (Auto-Precharge Disable) Write (Auto-Precharge Disabled) 10, 12 8 10, 11 10 8, 11 NOTES : 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see CKE Truth Table) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions : Idle : The bank has been precharged, and tRP has been met. Row Active : A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and truth table- current state bank n command to bank n. and according to truth table - current state bank n -command to bank m. Precharging : Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating : Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the :row active" state. - 47 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing : Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR2(x32) will be in the all banks idle state. Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the GDDR3(x32) SDRAM will be in the all banks idle state. Precharge All : Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging. 9. Left blank 10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Requires appropriate DM masking. 12. A WRITE command may be applied after the completion of the READ burst. - 48 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m CURRENT STATE Any Idle Row Activating, Active, or Prechrging Read (Auto-Precharge Disable) Write (Auto-Precharge Disabled) Read (With Auto-Precharge) Write (With Auto-Precharge) /CS /RAS /CAS /WE COMMAND/ ACTION NOTES H X X X DESELECT (NOP/ continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) X H L H DATA TERMINATOR DISABLE X X X X Any Command Otherwise Allowed to Bank m L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst) 6 L H L L WRITE (Select Column and start WRITE burst) 6 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start new READ burst) 6 L H L L WRITE (Select column and start WRITE burst) 6 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst) L H L L WRITE (Select column and start new WRITE burst) L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start new READ burst) 6 L H L L WRITE (Select column and start WRITE burst) 6 L L H L PRECHARGE L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start READ burst) 6 L H L L WRITE (Select column and start new WRITE burst) 6 L L H L PRECHARGE 6, 7 6 NOTES : 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see TRUTH TABLE- CKE ) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. - 49 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B 3. Current state definitions : Idle : The bank has been precharged, and tRP has been met. Row Active : A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. Read w/ Auto- Precharge Enabled : See following text Write w/ Auto- Precharge Enabled : See following text 3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts : the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR command and ends where the precharge period (or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related Limitations apply (e.g., contention between read data write data must be avoided). 3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. From Command To Command Minimum delay (with concurrent auto precharge) READ or READ w/AP [WL + (BL/2)] tCK + tWR WRITE or WRITE w/AP (BL/2) * tCK WRITE w/AP PRECHARGE 1 tCK ACTIVE 1 tCK READ or READ w/AP (BL/2) * tCK WRITE or WRITE w/AP [CLRU + (BL/2)] + 1 - WL * tCK READ w/AP PRECHARGE 1 tCK ACTIVE 1 tCK 4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. All states and sequences not shown are illegal or reserved. 6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 7. Requires appropriate DM masking. - 50 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, VOUT -0.5 ~ VDDQ + 0.5V V Voltage on VDD supply relative to Vss VDD -0.5 ~ 2.5 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 2.5 V Voltage on any pin relative to Vss TJ +125 °C TSTG -55 ~ +150 °C Power dissipation PD TBD W Short Circuit Output Current IOS 50 mA MAX Junction Temperature Storage temperature Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure periods may affect reliability. POWER & DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to 0°C ≤ Tc ≤ 85°C) Symbol Min Typ Max Unit Note Device Supply voltage Parameter VDD 1.9 2.0 2.1 V 1,7 Output Supply voltage VDDQ 1.9 2.0 2.1 V 1,7 Device Supply voltage VDD 1.7 1.8 1.9 V 1,8 Output Supply voltage VDDQ 1.7 1.8 1.9 V 1,8 VREF 0.69*VDDQ - 0.71*VDDQ V 3 DC Input logic high voltage VIH (DC) VREF+0.15 - - V 4 DC Input logic low voltage VIL (DC) - - VREF-0.15 V 4 Output logic low voltage VOL(DC) - - 0.76 V AC Input logic high voltage VIH(AC) VREF+0.25 - - V 4,5,6 AC Input logic low voltage VIL(AC) - - VREF-0.25 V 4,5,6 II -5 - 5 uA IIOZ -5 - 5 uA Reference voltage Input leakage current Any input 0V-<VIN -< VDDQ (All other pins not under test = 0V) Output leakage current (DQs are disabled ; 0V-<VOUT -< VDDQ) Note : 1.Under all conditions, VDDQ must be less than or equal to VDD. 3. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV for AC noise. 4. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate through the AC values. 5. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between Vih and Vil. DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. 6. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot : VIL(min)=0.0V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate. 7. K4J52324QC-BJ** 8. K4J52324QC-BC** - 51 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B CLOCK INPUT OPERATING CONDITIONS Recommended operating conditions (0°C ≤ Tc ≤85°C) Parameter/ Condition Symbol Min Max Unit Note Clock Input Mid-Point Voltage ; CK and /CK VMP(DC) 1.16 1.36 V 1,2,3 Clock Input Voltage Level; CK and /CK VIN(DC) 0.42 VDDQ + 0.3 V 2 Clock Input Differential Voltage ; CK and /CK VID(DC) 0.22 VDDQ + 0.5 V 2,4 Clock Input Differential Voltage ; CK and /CK VID(AC) 0.22 VDDQ + 0.3 V 4 Clock Input Crossing Point Voltage ; CK and /CK VIX(AC) VREF - 0.15 VREF + 0.15 V 3 Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ 2. For AC operations, all DC clock requirements must be satisfied as well. 3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same. 4. VID is the magnitude of the difference between the input level in CK and the input level on /CK. 5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross; the input reference level for signals other than CK and /CK is VREF. 6. CK and /CK input slew rate must be > 3V/ns 7. VDD & VDDQ=2.0V+0.1V for -BJ** and VDD&VDDQ=1.8V+0.1V for -BC** 1.26V VDDQ VREF 60Ω GDDR3 Z0=60 Ω 10pf 240 Ω ZQ Output Load Circuit Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40 Ω. CAPACITANCE (VDD=1.8V, TA= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance ( CK, CK ) CIN1 1.5 3.0 pF Input capacitance (A0~A11, BA0~BA1) CIN2 1.5 3.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.5 3.0 pF Data & DQS input/output capacitance(DQ0~DQ31) COUT 1.5 2.0 pF Input capacitance(DM0 ~ DM3) CIN4 1.5 2.0 pF - 52 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B DC CHARACTERISTICS-I (0°C ≤ Tc ≤85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V) Parameter Symbol Version Test Condition Unit -BJ12 -BJ14 Operating Current (One Bank Active) ICC1 Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 510 490 mA Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) 120 110 mA Precharge Standby Current in Non Power-down mode ICC2N 270 240 mA Active Standby Current power-down mode ICC3P 140 130 mA Active Standby Current in in Non Power-down mode ICC3N 420 400 mA CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 1075 980 mA Refresh Current ICC5 tRC≥ tRFC 525 500 mA Self Refresh Current ICC6 CKE ≤ 0.2V 50 50 mA Operating Current (4Bank interleaving) ICC7 Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 1195 1100 mA DC CHARACTERISTICS-II (0°C ≤ Tc ≤85°C ; VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V) Parameter Symbol Version Test Condition Unit -BC14 -BC16 -BC20 Operating Current (One Bank Active) ICC1 Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 420 410 400 mA Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) 90 85 80 mA Precharge Standby Current in Non Power-down mode ICC2N 200 190 170 mA Active Standby Current power-down mode ICC3P 110 100 95 mA Active Standby Current in in Non Power-down mode ICC3N 320 315 310 mA CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 830 760 655 mA Refresh Current ICC5 tRC≥ tRFC 480 460 440 mA Self Refresh Current ICC6 CKE ≤ 0.2V 50 50 50 mA Operating Current (4Bank interleaving) ICC7 Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 935 860 830 mA Note : 1. Measured with outputs open and ODT off 2. Refresh period is 32ms - 53 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B AC CHARACTERISTICS (I-I) Parameter -BJ12 -BJ14 Symbol Min Max Min Max Unit Note DQS out access time from CK tDQSCK -0.23 +0.23 -0.26 +0.26 ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 3.3 ns ns ns ns ns CK cycle time CL=11 CL=10 CL=9 CL=8 CL=7 tCK 1.25 1.4 1.6 2.0 2.0 3.3 1.4 1.6 2.0 2.0 WRITE Latency tWL 6 - 5 - tCK DQ and DM input hold time relative to DQS tDH 0.16 - 0.18 - ns DQ and DM input setup time relative to DQS tDS 0.16 - 0.18 - ns Active termination setup time tATS 10 - 10 - ns Active termination hold time tATH DQS input high pulse width tDQSH DQS input low pulse widthl tDQSL 0.48 0.52 Data strobe edge to Dout edge tDQSQ -0.140 0.140 DQS read preamble tRPRE 0.4 0.6 DQS read postamble tRPST 0.4 0.6 Write command to first DQS latching transition tDQSS WL-0.2 DQS write preamble tWPRE DQS write preamble setup time tWPRES DQS write postamble tWPST 10 - 10 - ns 0.48 0.52 0.48 0.52 tCK 0.48 0.52 tCK -0.160 0.160 ns 0.4 0.6 tCK 0.4 0.6 tCK WL+0.2 WL-0.2 WL+0.2 tCK 0.35 - 0.4 0.6 tCK 0 - 0 - ns 0.4 0.6 0.4 0.6 tCK - tCLmin or tCHmin - tCK Half strobe period tHP tCLmin or tCHmin Data output hold time from DQS tQH tHP-0.14 - tHP-0.16 - ns 1 2 3 Data-out high-impedance window from CK and /CK Data-out low-impedance window from CK and /CK tHZ -0.3 - -0.3 - ns 4 tLZ -0.3 - -0.3 - ns 4 Address and control input hold time tIH 0.3 - 0.35 - ns Address and control input setup time tIS 0.3 - 0.35 - ns Address and control input pulse width tIPW 0.9 - 1.0 - ns Jitter over 1~6 clock cycle error tJ 0.03 tDCERR Rise and fall times of CK tR, tF - 0.03 Cycle to cyde duty cycle error - tCK tCK tCK 0.03 0.2 0.03 0.2 5 Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks which must be greater than 7ns, the input buffers are turned on during the WRITE commands for lower power operation. 2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble. 3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by the on-die termination alone. 4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 5. The cycle to cycle jitter over 1~6 cycle short term jitter - 54 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B AC CHARACTERISTICS (I-II) Parameter Symbol Min -BC14 Max Min -BC16 Max Min -BC20 Max Unit Note DQS out access time from CK tDQSCK -0.26 +0.26 -0.29 +0.29 -0.35 +0.35 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tCK 1.4 1.6 2.0 2.0 CK cycle time CL=11 CL=10 CL=9 CL=8 CL=7 - - 3.3 1.6 2.0 2.0 3.3 2.0 3.3 ns ns ns ns ns WRITE Latency tWL 5 - 5 - 4 - tCK DQ and DM input hold time relative to DQS tDH 0.18 - 0.20 - 0.25 - ns DQ and DM input setup time relative to DQS tDS 0.18 - 0.20 - 0.25 - ns Active termination setup time tATS 10 - 10 - 10 - ns Active termination hold time tATH DQS input high pulse width tDQSH DQS input low pulse widthl tDQSL 0.48 0.52 0.48 0.52 Data strobe edge to Dout edge tDQSQ -0.160 0.160 0.180 0.180 10 - 10 - 10 - ns 0.48 0.52 0.48 0.52 0.48 0.52 tCK 0.48 0.52 tCK 0.225 0.225 ns DQS read preamble tRPRE 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 tCK DQS write preamble tWPRE 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS write preamble setup time tWPRES 0 - 0 - 0 - ns DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK - tCLmin or tCHmin - tCLmin or tCHmin - tCK Half strobe period tHP tCLmin or tCHmin Data output hold time from DQS tQH tHP-0.16 - tHP-0.18 - tHP-0.225 - ns 1 2 3 Data-out high-impedance window from CK and /CK Data-out low-impedance window from CK and /CK tHZ -0.3 - -0.3 - -0.3 - ns 4 tLZ -0.3 - -0.3 - -0.3 - ns 4 Address and control input hold time tIH 0.35 - 0.4 - 0.5 - ns Address and control input setup time tIS 0.35 - 0.4 - 0.5 - ns Address and control input pulse width tIPW 1.0 - 1.1 - 1.3 - ns Jitter over 1~6 clock cycle error tJ tR, tF - 0.03 Rise and fall times of CK - 0.03 tDCERR - 0.03 Cycle to cyde duty cycle error tCK tCK tCK 0.03 0.2 0.03 0.2 0.03 0.2 5 Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks which must be greater than 7ns, the input buffers are turned on during the WRITE commands for lower power operation. 2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble. 3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by the on-die termination alone. 4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 5. The cycle to cycle jitter over 1~6 cycle short term jitter - 55 - Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B AC CHARACTERISTICS II-I Parameter -BJ12 Symbol -BJ14 Min Max Min Max Unit Row active time tRAS 25 100K 22 100K tCK Row cycle time tRC 35 - 31 - tCK Refresh row cycle time tRFC 45 - 39 - tCK RAS to CAS delay for Read tRCDR 12 - 10 - tCK RAS to CAS delay for Write tRCDW 8 - 6 - tCK Row precharge time tRP 10 - 9 - tCK Row active to Row active tRRD 8 - 8 - tCK Four activate window tFAW 40 - 40 - tCK 11 - 10 - tCK 5 - tCK Last data in to Row precharge (PRE or Auto-PRE) tWR Last data in to Read command tCDLR 6 - Mode register set cycle time tMRD 7 - 6 - tCK Auto precharge write recovery time + Precharge tDAL 21 - 19 - tCK Exit self refresh to Read command tXSR 20000 - 20000 - tCK Power-down exit time tPDEX 7tCK +tIS - 6tCK +tIS - tCK Refresh interval time tREF - 3.9 - 3.9 us Note AC CHARACTERISTICS II-II Parameter Symbol -BC14 Min Max -BC16 Min Max -BC20 Min Max Unit Row active time tRAS 22 100K 19 100K 15 100K tCK Row cycle time tRC 31 - 28 - 22 - tCK Refresh row cycle time tRFC 39 - 33 - 27 - tCK RAS to CAS delay for Read tRCDR 10 - 10 - 8 - tCK RAS to CAS delay for Write tRCDW 6 - 6 - 5 - tCK Row precharge time tRP 9 - 9 - 7 - tCK Row active to Row active tRRD 8 - 7 - 5 Four activate window tFAW 40 - 35 - 25 - tCK 10 - 9 - 7 - tCK Last data in to Row precharge (PRE or Auto-PRE) tWR tCDLR Last data in to Read command tCK 5 - 4 - 3 - tCK Mode register set cycle time tMRD 6 - 5 - 4 - tCK Auto precharge write recovery time + Precharge tDAL 19 - 18 - 14 - tCK Exit self refresh to Read command tXSR 20000 - 20000 - 20000 - tCK Power-down exit time tPDEX 6tCK +tIS - 6tCK +tIS - 4tCK +tIS - tCK Refresh interval time tREF - 3.9 - 3.9 - 3.9 us - 56 - Note Rev 1.0 (Mar 2005) 512M GDDR3 SDRAM K4J52324QC-B PACKAGE DIMENSIONS (FBGA) A1 INDEX MARK 14.0 11.0 <Top View> 0.8x11=8.8 0.12 Max 0.8 0.8 0.35 ± 0.05 1.20 Max 0.8x16=12.8 0.45 ± 0.05 A B C D E F G H J K L M N P R T V 1 2 3 4 5 6 7 8 9 10 11 12 0.40 <Top View: See the balls through the package> Ball existing Depopulated ball - 57 - Rev 1.0 (Mar 2005)