SDRAM 16Mb H-die(x16) CMOS SDRAM 16Mb H-die SDRAM Specification Revision 1.5 August 2004 Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM Revision History Revision 0.0 (May, 2003) - Target spec release. Revision 0.1 (October, 2003) - Modified tRDL from 1CLK to 2CLK. Revision 0.2 (October, 2003) - Deleted AC parameter notes 5. Revision 0.3 (October, 2003) - Modified tRDL & deleted speed 200MHz. Revision 1.0 (November, 2003) - Revision 1.0 spec. release. Revision 1.1 (December, 2003) - Corrected PKG dimension. Revision 1.2 (January, 2004) - Deleted -10(10ns) speed. - Modified load cap 50pF -> 30pF. - Modified DC current . Revision 1.3 (January, 2004) - Corrected typo Revision 1.4 (May, 2004) - Added Note 8. sentense of tRDL parameter. Revision 1.5 (August, 2004) - Modified CLK cycle time(tcc) parameter in AC Characteristics. ( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.) Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM 512K x 16Bit x 2 Banks SDRAM FEATURES • • • • • • • • • 3.3V power supply LVTTL compatible with multiplexed address two banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 32ms refresh period (2K cycle) GENERAL DESCRIPTION The K4S161622H is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/ O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. MAX Freq. K4S161622H-TC55 Interface Package LVTTL 50pin TSOP(II) 183MHz K4S161622H-TC60 166MHz K4S161622H-TC70 143MHz K4S161622H-TC80 125MHz Organization Row Address Column Address 1Mx16 A0~A10 A0-A7 Row & Column address configuration Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM Package Physical Dimension 20.95 ± 0.10 1.20MAX ± 0.20 (10.76) 10.16 ± 0.10 0.125+0.075 -0.035 11.76 #25 (0.50) #1 0.25 TYP 11.76±0.20 #26 (0.50) 0~8° #50 1.00 ± 0.10 0.10MAX [ 0.075MAX ] (0.875) 0.30 +0.10 -0.05 0.35 +0.10 -0.05 0.80TYP [0.80±0.08] 0.05MIN 50Pin TSOP(II) Package Dimension Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register Bank Select Output Buffer 512K x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter LDQM DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 16 LWE Latency & Burst Length LCKE Programming Register LRAS LCBR LCAS LWE LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP (II) (400mil x 825mil) (0.8 mm PIN PITCH) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A10/AP Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 BA Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)DQM Data Input/Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V VIH 2.0 3.0 VDDQ+0.3 V Input logic high votlage Note 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. : 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol Min Max Unit Clock CCLK 2 4 pF RAS, CAS, WE, CS, CKE, L(U)DQM CIN 2 4 pF Address CADD 2 4 pF DQ0 ~ DQ15 COUT 3 5 pF Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C ) Version Parameter Symbol Test Condition 55 60 70 80 120 115 105 95 Unit Note mA 2 ICC1 Burst Length =1 tRC≥tRC(min) Io = 0 mA ICC2P CKE≤VIL(max), tCC = 10ns 2 ICC2PS CKE & CLK≤VIL(max), tCC = ∞ 2 ICC2N CKE≥VIH(min), CS≥VIH(min), tCC = 10ns Input signals are changed one time during 30ns 15 ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC = ∞ Input signals are stable 5 ICC3P CKE≤VIL(max), tCC = 10ns 3 ICC3PS CKE & CLK≤VIL(max), tCC = ∞ 3 ICC3N CKE≥VIH(min), CS≥VIH(min), tCC = 10ns Input signals are changed one time during 30ns 25 mA ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC = ∞ Input signals are stable 15 mA Operating Current (Burst Mode) ICC4 Io = 0 mA Page Burst 2Banks Activated tCCD = 2CLKs 155 150 140 130 mA 2 Refresh Current ICC5 tRC≥tRC(min) 105 100 90 90 mA 3 Self Refresh Current ICC6 CKE≤0.2V Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) mA mA mA 1 mA Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4S161622H-TC Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C) Parameter Value Unit 2.4 / 0.4 V 1.4 V tr / tf = 1 / 1 ns 1.4 V Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt=1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0=50Ω 30pF 870Ω 30pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter 55 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 60 Max 5.5 1000 10 Min 6 70 Max Min Max 7 1000 10 80 1000 10 Min 8 Unit Note 1000 ns 1 Max 10 Row active to row active delay tRRD(min) 11 - 12 - 14 - 16 - ns RAS to CAS delay tRCD(min) 16.5 - 18 - 20 - 20 - ns Row precharge time tRP(min) 16.5 - 18 - 20 - 20 - ns tRAS(min) 38.5 - 42 - 49 - 48 - ns tRAS(max) - 100 - 100 - 100 - 100 us Row cycle time tRC(min) 55 - 60 - 69 - 70 - ns Last data in to row precharge tRDL(min) Row active time 2 1 CLK 2,8 Last data in to new col.address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK Mode Register Set cycle time tMRS(min) 2 CLK Number of valid output data CAS Latency=3 2 CAS Latency=2 1 ea 4 Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM (AC operating conditions unless otherwise noted) Parameter 55 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 CAS Latency=3 CLK low pulse width CAS Latency=3 Input setup time tSAC tOH CLK high pulse width tCH CAS Latency=2 1000 tCL CAS Latency=2 6 Max 1000 Min 7 -80 Max 1000 10 Min 8 Unit Note ns 5 ns 5, 6 Max 1000 10 - 5 - 5.5 - 5.5 - 6 - 6 - 6 - 6 - 6 2 - 2.5 - 2.5 - 2.5 - ns 6 - 3 - 3 - ns 7 - 3 - 3 - ns 7 - 2 - ns 7 2 - 2 1.5 2.5 3 - 3 tSS Min -70 10 3 CAS Latency=2 CAS Latency=3 Max 10 CAS Latency=2 Output data 5.5 60 2.5 3 - 2 1.5 - 2 1.75 2 Input hold time tSH 1 - 1 - 1 - 1 - ns 7 CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - ns 6 - 5 - 5.5 - 5.5 - 6 - 6 - 6 - 6 - 6 CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 tSHZ ns Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. Parameters depend on programmed CAS latency. 6. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 7. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 8. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 1.5 August 2004 SDRAM 16Mb H-die(x16) CMOS SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X H Entry Self Refresh Exit H BA L H L H H H H X X X X X L L H H X V H X L H L H X V Write & Column Address Auto Precharge Disable Auto Precharge Enable X L H L L X H X X L L H L H H L V H L Exit L H Entry H L Precharge Power Down Mode Exit Column Address L L X X Both Banks Entry L Column Address H H L DQM H No Operation Command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row Address H Auto Precharge Enable Clock Suspend or Active Power Down 3 3 H Precharge 1, 2 X Auto Precharge Disable H Note 3 Read & Column Address Bank Selection A9~ A0 L Bank Active & Row Addr. Burst Stop A10/AP X V L X H 4 4, 5 4 4, 5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A10/AP, BA : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 1.5 August 2004