Preliminary K4S281633D-RL(N) CMOS SDRAM 8Mx16 SDRAM 54CSP (V DD/V DDQ 3.0V/3.0V & 3.3V/3.3V) Revision 0.6 November 2001 Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM Revision History Revision 0.0 (February 21. 2001, Target) • First generation of 128Mb Low Power SDRAM without special function (V DD 3.0V, V DDQ 3.0V) Revision 0.1 (June 4. 2001, Target) • Addition of DC Current value. Revision 0.2 (June 20. 2001, Target) • Changed device name from low power sdram to mobile dram. Revision 0.3 (August 1. 2001, Target) • Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part. • Change of tOH from 3ns to 3.5ns. • Change V IH min. from 2.0 V to 0.8xVDDQ and VOH min. from 2.4V to 0.9xVDDQ. Revision 0.4 (October 6. 2001, Preliminary) • Changed DC current. • Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part. • Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part. • Changed of tOH from 3ns to 2.5ns. • Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part. • Integration of VDDQ 1.8V device and 2.5V device. • Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ. • Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V. • Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA. • Erased -15 bin and added -1H bin. Revision 0.5 (October 12. 2001, Preliminary) • Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V. • Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V. Revision 0.6 (November 7. 2001, Preliminary) • Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V. Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM 2M x 16Bit x 4 Banks SDRAM in 54CSP FEATURES GENERAL DESCRIPTION • 3.0V & 3.3V power supply. The K4S281633D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 • LVTTL compatible with multiplexed address. bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • All inputs are sampled at the positive going edge of the system with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. clock. • Burst read single-bit write operation.. ORDERING INFORMATION • DQM for masking. Part No. Max Freq. K4S281633D-RL/N75 133MHz(CL=3) 100MHz(CL=2) K4S281633D-RL/N1H 100MHz(CL=2) • Auto refresh. • 64ms refresh period (4K cycle). • Commercial Temperature Operation (-25°C ~ 70 °C). Extended Temperature Operation (-25°C ~ 85°C). K4S281633D-RL/N1L 100MHz(CL=3) Interface Package LVTTL 54 CSP *1 -RN ; Low Power, Operating Temperature : -25’C~85’C. -RL ; Low Power, Operating Temperature : -25’C~70’C. FUNCTIONAL BLOCK DIAGRAM Note : 1. In case of 40MHz Frequency, CL1 can be supported. I/O Control Data Input Register LWE LDQM Bank Select Output Buffer Sense AMP Row Decoder ADD Row Buffer Refresh Counter 2M x 16 2M x 16 2M x 16 DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 2M x 16 Latency & Burst Length LCKE Programming Register LRAS LCBR LWE LCAS LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE LDQM UDQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM Package Dimension and Pin Configuration < Bottom View*1 > < Top View*2 > E1 54Ball(6x9) CSP 9 8 7 6 5 4 3 2 1 1 2 3 7 8 9 A V SS DQ15 VSSQ V DDQ DQ0 VD D B B DQ14 DQ13 V DDQ VSSQ DQ2 DQ1 C C DQ12 DQ11 VSSQ V DDQ DQ4 DQ3 D D DQ10 DQ9 V DDQ VSSQ DQ6 DQ5 D D1 e A E E DQ8 NC V SS VD D LDQM DQ7 F F UDQM CLK CKE CAS RAS WE G NC A11 A9 BA0 BA1 CS H A8 A7 A6 A0 A1 A10 J J V SS A5 A4 A3 A2 VD D D/2 G H E E/2 *2: Top View A Pin Function CLK System Clock CS Chip Select CKE Clock Enable A0 ~ A 11 Address BA0 ~ BA 1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable *1: Bottom View L(U)DQM Data Input/Output Mask < Top View*2 > DQ 0 ~ 15 Data Input/Output A1 Max. 0.20 Pin Name ϕb Encapsulant ζ V DD /VSS Power Supply/Ground V DDQ /VSSQ Data Output Power/Ground #A1 Ball Origin Indicator SAMSUNG WEEK K4S281633D-RL(N) [Unit:mm] Symbol Min Typ Max A 0.90 0.95 1.00 A1 0.30 0.35 0.40 E - 8.00 - E1 - 6.40 - D - 8.00 - D1 - 6.40 - e - 0.80 - ϕb 0.40 0.45 0.50 ζ - - 0.08 Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V I N, VOUT -1.0 ~ 4.6 V Voltage on V D D supply relative to Vss VDD , V DDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA =-25°C ~ 70 °C (Commercial), -25 °C ~ 85°C (Extended)) Parameter Symbol Min Typ Max Unit VD D 2.7 3.0 3.6 V V DDQ 2.7 3.0 3.6 V Input logic high voltage VI H 2.2 3.0 V DDQ +0.3 V 1 Input logic low voltage VIL -0.3 0 0.5 V 2 Output logic high voltage VO H 2.4 - - V I O H = -2mA Output logic low voltage V OL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Note : 1. V IH (max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ V DDQ . Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ V OUT ≤ V DDQ. CAPACITANCE (VDD = 3.0V, TA = 23°C, f = 1MHz, V REF =0.9V ± 50 mV) Pin Symbol Min Max Unit CCLK 2.0 4.0 pF CIN 2.0 4.0 pF Address CADD 2.0 4.0 pF D Q0 ~ DQ15 COUT 3.5 6.0 pF Clock RAS, CAS, WE, CS, CKE, DQM Note Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA =-25°C ~ 70°C (Commercial), -25°C ~ 85 °C (Extended)) Parameter Symbol Operating Current (One Bank Active) Precharge Standby Current in power-down mode I CC1 Burst length = 1 tRC ≥ t R C(min) IO = 0 mA ICC2 P CKE ≤ V IL (max), tCC = 10ns -75 -1H -1L 80 75 75 0.5 IC C 2PS CKE & CLK ≤ V IL (max), tCC = ∞ ICC2 N Precharge Standby Current in non power-down mode I CC2NS ICC3 P Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Version Test Condition I CC3NS Note mA 1 mA 0.5 CKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 12 mA CKE ≥ V IH (min), CLK ≤ VIL (max), tCC = ∞ Input signals are stable 10 CKE ≤ V IL (max), tCC = 10ns 7 IC C 3PS CKE & CLK ≤ V IL (max), tCC = ∞ ICC3 N Unit mA 7 CKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 23 mA CKE ≥ V IH (min), CLK ≤ VIL (max), tCC = ∞ Input signals are stable 20 mA Operating Current (Burst Mode) I CC4 IO = 0 mA Page burst 4Banks Activated tC C D = 2CLKs 130 130 110 mA 1 Refresh Current I CC5 tRC ≥ tR C(min) 170 170 155 mA 2 Self Refresh Current I CC6 CKE ≤ 0.2V uA 3 uA 4 -RL -RN 500 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281633D-RL** 4. K4S281633D-RN** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /V IL =V DDQ /V SSQ) Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM AC OPERATING TEST CONDITIONS (V DD = 2.7V ~ 3.6V, TA =-25°C ~ 70°C (Commercial), -25 °C ~ 85 °C (Extended)) Parameter Value Unit 2.4 / 0.4 V 0.5 x VDDQ V tr/tf = 1/1 ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Fig. 2 AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time VDDQ Vtt = 0.5 x VDDQ 1200 Ω 50Ω V OH (DC) = 2.4V, IO H = -2mA V OL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 30pF 30pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol - 75 -1H -1L Unit Note Row active to row active delay tRRD (min) 15 20 20 ns 1 RAS to CAS delay tRCD (min) 20 20 24 ns 1 tRP (min) 20 20 24 ns 1 tRAS (min) 45 50 60 ns 1 Row precharge time Row active time tRAS (max) Row cycle time t R C(min) Last data in to row precharge tR D L(min) Last data in to Active delay 100 ns 1 2 CLK 2 tDAL (min) 2 CLK + tRP - Last data in to new col. address delay tC D L(min) 1 CLK 2 Last data in to burst stop tBDL (min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 3 ea 4 Number of valid output data 65 70 us CAS latency=3 2 CAS latency=2 1 CAS latency=1 - 84 0 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter - 75 Symbol Min CAS latency=3 CLK cycle time CAS latency=2 10 tSAC CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 tO H CAS latency=1 Min -1L Max 10 1000 - CAS latency=3 CAS latency=2 Max 7.5 tC C CAS latency=1 CLK to valid output delay -1H 10 Min Unit Note ns 1 ns 1,2 ns 2 Max 10 1000 - 12 1000 25 5.4 7 7 7 7 8 - - 20 2.5 2.5 2.5 2.5 2.5 2.5 - - 2.5 CLK high pulse width tC H 2.5 3 3 ns 3 CLK low pulse width tC L 2.5 3 3 ns 3 Input setup time tSS 2.0 2.5 2.5 ns 3 Input hold time tSH 1.0 1.5 1.5 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CAS latency=3 CLK to output in Hi-Z CAS latency=2 tSHZ CAS latency=1 5.4 7 7 7 7 8 - - 20 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X L H H H X X H H L BA0,1 L H H X X X Bank Active & Row Addr. H X L L H H X V Read & Column Address Auto Precharge Disable H X L H L H X V Write & Column Address Auto Precharge Disable H X L H L L X V H X L H H L X H X L L H L X Entry H L H X X X L V V V Exit L H X X X X Entry H L H X X X L H H H H X X X L V V V Auto Precharge Enable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Clock Suspend or Active Power Down L DQM H No Operation Command H H X X H X X X L H H H X A11, A9 ~ A 0 Note 1, 2 3 3 3 3 Row Address L Column Address (A 0 ~ A8) H L Precharge Power Down Mode Exit A10 /AP Column Address (A 0 ~ A8) H X V L X H 4 4, 5 4 4, 5 6 X X X X X X V X X X 7 (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A 0 ~ A 11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA 1 : Bank select addresses. If both BA 0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2). Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) CMOS SDRAM MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with Normal MRS Address BA0 ~ BA1*1 A11 ~ A10/AP A9 Function "0" Setting for Normal MRS RFU W.B.L A8 A7 A6 Test Mode A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length Normal MRS Mode Test Mode CAS Latency Burst Type Burst Length A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2 1 0 Reserved 0 1 0 2 0 1 0 4 4 1 1 Reserved 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Write Burst Length A9 Length 1 0 1 Reserved 0 Burst 1 1 0 Reserved 1 Single Bit 1 1 1 Reserved Mode Select BA1 0 BA0 Mode 0 Setting for Normal MRS Full Page Length : 256(x16) Power Up Sequence 1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Power is applied to VDD and VDDQ (simultaneously). 3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 4. Issue precharge commands for all banks of the devices. 5. Issue 2 or more auto-refresh commands. 6. Issue a mode register set command to initialize the mode register. Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely. Rev. 0.6 Nov. 2001