FLASH MEMORY
K9F2808U0C
Document Title
16M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial issue.
Apr. 15th 2002
Advance
1.0
TBGA PKG Dimension Change
48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm
Sep. 5th 2002
Advance
2.0
1.A3 Pin assignment of TBGA Package is changed.(Page 4)
(before) NC --> (after) Vss
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 32)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 33)
Dec.10th 2002
Preliminary
The min. Vcc value 1.8V devices is changed.
Mar. 6th 2003
2.1
K9F28XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
2.2
Pb-free Package is added.
Mar. 13rd 2003
K9F2808U0C-FCB0,FIB0
K9F2808Q0C-HCB0,HIB0
K9F2816U0C-HCB0,HIB0
K9F2816U0C-PCB0,PIB0
K9F2816Q0C-HCB0,HIB0
K9F2808U0C-HCB0,HIB0
K9F2808U0C-PCB0,PIB0
2.3
Some AC parameters are changed(K9F28XXQ0C).
tWC tWH tWP tRC tREH tRP tREA tCEA
Before
45
15
25
50
15
25
30
45
After
60
20
40
60
20
40
40
55
2.4
Mar. 26th 2003
1. New definition of the number of invalid blocks is added.
(Minimum 502 valid blocks are guaranteed for each contiguous 64Mb
memory space)
2. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
2.5
1. K9F2808U(Q)0C-DC(I)B0,K9F2816U(Q)0C-DC(I)B0 is deleted.
2. tWC is changed.
45ns(Before) ---> 50ns(After)
3. Minimum valid block number is changed.
1004(Before) --> 1009(After)
1. Minimum valid block number is changed.
1009(Before) --> 1004(After)
May. 24th 2003
2.6
Oct. 10th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
Package Dimensions
FLASH MEMORY
Document Title
16M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
2.7
1. Add the Protrusion/Burr value in WSOP1 PKG Diagram
2. PKG(TSOP1, WSOP1) Dimension Change
May 21th 2004
2.8
1. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 13)
-Error in write or read operation ( page 14 )
-Program Flow Chart ( page 14 )
Oct. 25th. 2004
2.9
1. The flow chart to creat the initial invalid block table is changed.
May 6th 2005
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
FLASH MEMORY
K9F2808U0C
16M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F2808U0C-Y,P
Vcc Range
Organization
2.7 ~ 3.6V
X8
K9F2808U0C-V,F
PKG Type
TSOP1
WSOP1
FEATURES
• Voltage Supply : 2.7 ~ 3.6 V
• Organization
- Memory Cell Array
-(16M + 512K)bit x 8bit
- Data Register
- (512 + 16)bit x 8bit
• Automatic Program and Erase
- Page Program
-(512 + 16)Byte
- Block Erase :
- (16K + 512)Byte
• Page Read Operation
- Page Size
- (512 + 16)Byte
- Random Access
: 10µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package
- K9F2808U0C-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F2808U0C-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package
- K9F2808U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F2808U0C-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package
* K9F2808U0C-V/F(WSOPI ) is the same device as
K9F2808U0C-Y/P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 16Mx8bit , the K9F2808U0C is 128M bit with spare 4M bit capacity. The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs
on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the page can be read out
at 50ns cycle time per word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F2808U0C’s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F2808U0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
FLASH MEMORY
K9F2808U0C
PIN CONFIGURATION (TSOP1)
K9F2808U0C-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
12.40
0.488 MAX
12.00
0.472
+0.003
( 0.25 )
0.010
#1
0.008-0.001
0.50
0.0197
0.16 -0.03
+0.075
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.125 0.035
+0.07
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
( 0.50 )
0.020
4
1.20
0.047MAX
0.05
0.002 MIN
FLASH MEMORY
K9F2808U0C
PIN CONFIGURATION (WSOP1)
K9F2808U0C-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
0.58±0.04
15.40±0.10
#48
#24
#25
0.20
0.50TYP
(0.50±0.06)
12.40MAX
12.00±0.10
+0.07
-0.03
0.16
+0.07
-0.03
#1
0°~
0.10 +0.075
-0.035
(0.01Min)
8°
0.45~0.75
17.00±0.20
5
FLASH MEMORY
K9F2808U0C
PIN DESCRIPTION
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
GND
GND INPUT FOR ENABLING SPARE AREA
To do sequential read mode including spare area , connect this input pin to Vss or set to static low state
or to do sequential read mode excluding spare area , connect this input pin to Vcc or set to static high state.
DNU
DO NOT USE
Leave it disconnected.
NOTE :
Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
6
FLASH MEMORY
K9F2808U0C
Figure 1-1. K9F2808U0C FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A23
X-Buffers
Latches
& Decoders
A0 - A7
Y-Buffers
Latches
& Decoders
128M + 4M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 32768
Page Register & S/A
A8
Y-Gating
Command
Command
Register
CE
RE
WE
VCC/VCCQ
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9F2808U0C ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
32K Pages
(=1,024 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 1024 Blocks
= 132 Mbits
8 bit
512Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
16 Byte
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
L*
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.
* L must be set to "Low".
7
Column Address
Row Address
(Page Address)
FLASH MEMORY
K9F2808U0C
PRODUCT INTRODUCTION
The K9F2808U0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. Spare eight columns are
located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in
Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 1024 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F2808U0C.
The K9F2808U0C has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and
data are all written through I/O’s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch
Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus.
Some other commands like Page Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution.
The 16K-byte physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low
row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the
required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are
selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F2808U0C.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
Read 1
1st. Cycle
00h/01h
Read 2
2nd. Cycle
Acceptable Command during Busy
-
(1)
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
NOTE: 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on 2nd half of register by the 01h command, start pointer is automatically moved to
1st half register(00h) on the next cycle.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
8
O
O
FLASH MEMORY
K9F2808U0C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
VIN/OUT
-0.6 to + 4.6
VCC
-0.6 to + 4.6
VCCQ
-0.6 to + 4.6
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
K9F2808U0C-XCB0
K9F2808U0C-XCB0
K9F2808U0C-XIB0
V
-10 to +125
TBIAS
K9F2808U0C-XIB0
Unit
°C
-40 to +125
TSTG
-65 to +150
°C
Ios
5
mA
Short Circuit Current
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F2808U0C-XCB0 :TA=0 to 70°C, K9F2808U0C-XIB0:TA=-40 to 85°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
2.7
3.3
3.6
V
Supply Voltage
VCCQ
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Sequential Read
Symbol
ICC1
Test Conditions
tRC=50ns, CE=VIL
IOUT=0mA
Min
Typ
Max
-
10
20
Program
ICC2
-
-
10
20
Erase
ICC3
-
-
10
20
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP=0V/VCC
-
10
50
Input Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
±10
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
Input High Voltage
VIH*
Input Low Voltage, All inputs
VIL*
Output High Voltage Level
VOH
I/O pins
2.0
-
VCCQ+0.3
Except I/O pins
2.0
-
VCC+0.3
-0.3
-
0.8
2.4
-
-
IOH=-400µA
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
Output Low Current(R/B)
IOL(R/B)
VOL=0.4V
8
10
-
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
9
Unit
mA
µA
V
mA
FLASH MEMORY
K9F2808U0C
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
1004
-
1024
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
3. Minimum 502 valid blocks are guaranteed for each contiguous 64Mb memory space.
AC TEST CONDITION
(K9F2808U0C-XCB0 :TA=0 to 70°C, K9F2808U0C-XIB0:TA=-40 to 85°C
K9F2808U0C : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2808U0C
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (VccQ:3.3V +/-10%)
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
Item
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
WE
RE
GND
WP
H
L
L
H
X
X
L
H
L
H
X
X
Mode
Read Mode
Command Input
Address Input(3clock)
H
L
L
H
X
H
L
H
L
H
X
H
L
L
L
H
L
H
Data Input
L
L
L
H
L
X
Data Output
L
L
L
H
H
L
X
During Read(Busy)
X
X
X
X
H
L
X
During Read(Busy)
X
X
X
X
X
L
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X
X
X
L
Write Protect
H
X
X
0V
0V/V
X
X
X
(1)
X
Write Mode
CC(2)
Command Input
Address Input(3clock)
Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Program Time
Number of Partial Program Cycles
in the Same Page
Block Erase Time
Main Array
Spare Array
Symbol
Min
Typ
Max
Unit
tPROG
-
200
500
µs
Nop
tBERS
-
-
2
cycles
-
-
3
cycles
-
2
3
ms
NOTE : Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature of
25°C .
10
FLASH MEMORY
K9F2808U0C
AC Timing Characteristics for Command / Address / Data Input
Parameter
K9F2808U0C
Symbol
Unit
CLE Set-up Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE Setup Time
tCS
0
-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25
-
ns
ALE Setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data Setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
50
-
ns
WE High Hold Time
tWH
15
-
ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC Characteristics for Operation
Parameter
K9F2808U0C
Symbol
Unit
tR
-
10
µs
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
25
-
ns
Data Transfer from Cell to Register
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
CE Access Time
tCEA
-
45
ns
RE Access Time
tREA
-
30
ns
RE High to Output Hi-Z
tRHZ
-
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE or CE High to Output hold
tOH
15
-
ns
RE High Hold Time
tREH
15
-
ns
tIR
0
-
ns
WE High to RE Low
Output Hi-Z to RE Low
tWHR
60
-
ns
Device Resetting Time(Read/Program/Erase)
tRST
-
5/10/500(1)
µs
tRB
-
100
ns
-
50 +tr(R/B)(3)
ns
100
-
ns
Last RE High to Busy
(at sequential read)
K9F2808U0CY,P,V,F only
CE High to Ready(in case of interception by
CE at read)
tCRY
CE High Hold Time(at the last serial read)(2)
tCEH
NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
11
FLASH MEMORY
K9F2808U0C
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which
is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of
every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable
in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize
the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update)
Initial
Invalid Block(s) Table
No
Check "FFh" at the column address
517 of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
12
FLASH MEMORY
K9F2808U0C
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be
reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Single Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
13
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
FLASH MEMORY
K9F2808U0C
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
Erase Error
No
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
1
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
14
FLASH MEMORY
K9F2808U0C
Pointer Operation of K9F2808U0C
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’ area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’ command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’ area(256~512), and will be reset to
’A’ area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’ area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’ command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’ area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’ area can be programmed.
80h
’50h’ command can be omitted.
15
10h
FLASH MEMORY
K9F2808U0C
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
WE
≈
≈
CE
ALE
I/Ox
80h
Start Add.(3Cycle)
tCS
Data Input
tCH
Data Input
10h
tCEA
CE
CE
RE
tWP
tREA
WE
I/O0~15
out
Figure 7. Read Operation with CE don’t-care.
CLE
CE must be held
low during tR
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/Ox
00h
Data Output(sequential)
Start Add.(3Cycle)
16
FLASH MEMORY
K9F2808U0C
I/O
DATA
I/Ox
Data In/Out
I/O 0 ~ I/O 7
~528byte
Device
K9F2808U0C
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/Ox
Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
CE
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tWP
tALH
ALE
tDS
I/Ox
tDH
tDS
tDH
A9~A16
AO~A7
17
tDS
tDH
A17~A23
FLASH MEMORY
K9F2808U0C
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
ALE
tWP
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
tWP
≈
tWP
WE
I/Ox
DIN n
DIN 1
≈
DIN 0
Serial access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tRP
tREA
≈
tREH
tREA
tCHZ*
tOH
tREA
RE
I/Ox
Dout
Dout
≈
tRHZ*
tRHZ*
tOH
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
18
FLASH MEMORY
K9F2808U0C
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR
RE
tDH
tDS
I/Ox
tIR
tRHZ
tOH
tREA
Status Output
70h
READ1 OPERATION(READ ONE PAGE)
CLE
1)
tCEH
CE must be held
low during tR
CE
tCHZ
tOH
tWC
WE
tWB
tCRY
tAR
ALE
tR
RE
tRHZ
tOH
tRC
≈
N Address
I/Ox
Read
CMD
A0~A7
Column
Address
A9~A16
A17~A23
Dout N
Page(Row)
Address
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout m
tRB
Busy
R/B
1)
m = 528 , Read CMD = 00h or 01h
19
FLASH MEMORY
K9F2808U0C
READ1 OPERATION (INTERCEPTED BY CE)
CLE
CE must be held
low during tR
CE
WE
tWB
tCHZ
tOH
tAR
ALE
tRC
tR
RE
N Address
tRR
I/Ox
Read
CMD
Col. Add
Row Add1
Column
Address
Dout N
Row Add2
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Busy
R/B
READ2 OPERATION (READ ONE PAGE)
CLE
CE must be held
low during tR
CE
WE
tR
tWB
tAR
ALE
RE
I/Ox
50h
Col. Add
Row Add1
Dout
n+M
Row Add2
R/B
Dout
n+M+1
≈
≈
tRR
Dout n+m
Selected
Row
M Address
A0~A3 are Valid Address & A4~A7 are Don′t care
n
n = 512, m = 16
20
m
Start
address M
FLASH MEMORY
K9F2808U0C
SEQUENTIAL ROW READ OPERATION
(only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block)
CLE
CE
WE
Row Add1
Dout
N
Row Add2
Dout
N+1
Dout
N+2
Busy
R/B
Dout
0
≈
Ready
Dout
527
Dout
1
Dout
2
Dout
527
≈
Col. Add
≈
≈
00h
≈
RE
I/Ox
≈
ALE
Busy
M
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
tWB
tPROG
ALE
RE
80h
Col. Add
Sequential Data Column
Input Command Address
Row Add1
Row Add2
Page(Row)
Address
≈ ≈
I/Ox
N Address
Din
Din
N
N+1
1 up to m Data
Serial Input
10h
70h
Program
Command
Read Status
Command
≈
R/B
Din
m
m = 528 byte
21
I/O0
I/O0=0 Successful Program
I/O0=1 Error in Program
FLASH MEMORY
K9F2808U0C
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
60h
A9~A16
A17~A23
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Page(Row)
Address
Read Status
Command
22
I/O0=0 Successful Erase
I/O0=1 Error in Erase
FLASH MEMORY
K9F2808U0C
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
tAR
RE
tREA
I/Ox
90h
Read ID Command
00h
ECh
Address. 1cycle
Maker Code
Device
Code*
Device Code
Device
Device Code*
K9F2808U0C
73h
23
FLASH MEMORY
K9F2808U0C
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the
output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing
RE. High to low transitions of the RE clock output the data starting from the selected column address up to the last column
address[column 511/ 527 depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0~A3 set the starting
address of the spare area while addresses A4~A7 are ignored. The Read1 command is needed to move the pointer back to the main
area. Figures 8, 9 show typical sequence and timings for each read operation.
Sequential Row Read is available :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.
Figure 8. Read1 Operation
CLE
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Start Add.(3Cycle)
Data Output(Sequential)
A0 ~ A7 & A9 ~ A23
(00h Command)
1)
(01h Command)
1st half array
Main array
Data Field
Spare Field
2st half array
Data Field
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
24
Spare Field
FLASH MEMORY
K9F2808U0C
Figure 9. Read2 Operation
CLE
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/Ox
Start Add.(3Cycle)
50h
Data Output(Sequential)
A0 ~ A3 & A9 ~ A23
Spare Field
A4 ~ A7 Don’t care
Main array
Data Field
Spare Field
Figure 8-1. Sequential Row Read1 Operation
I/Ox
Data Output
Start Add.(3Cycle)
00h
01h
2nd half array
1st half array
Data Field
Spare Field
Nth
(528 Byte)
(GND input=H, 00h Command)
2nd half array
1st
2nd
Nth
Block
Data Output
2nd
(528 Byte)
(GND input=L, 01h Command)
(GND input=L, 00h Command)
tR
Data Output
1st
A0 ~ A7 & A9 ~ A23
1st half array
≈
tR
tR
R/B
1st half array
2nd half array
1st
2nd
Nth
1st
2nd
Nth
Data Field
25
Spare Field
Data Field
Spare Field
FLASH MEMORY
K9F2808U0C
Figure 9-1. Sequential Row Read2 Operation (GND Input=Fixed Low)
I/Ox
50h
Start Add.(3Cycle)
A0 ~ A3 & A9 ~ A23
≈
tR
tR
R/B
Data Output
1st
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don′t Care)
1st
Block
Nth
Data Field
Spare Field
26
tR
FLASH MEMORY
K9F2808U0C
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the
same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be
done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data
may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. About the pointer operation, please refer to the attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
tPROG
R/B
I/Ox
80h
Address & Data Input
10h
70h
I/O0
Fail
27
Pass
FLASH MEMORY
K9F2808U0C
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A14 to A23 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the
erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence.
Figure 11. Block Erase Operation
tBERS
R/B
I/Ox
60h
Address Input(2Cycle)
I/O0
70h
D0h
Pass
Block Add. : A9 ~ A23
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
Status
I/O 0
Program / Erase
Definition
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O 1
I/O 2
I/O 3
"0"
"0"
Reserved for Future
Use
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
I/O 7
Write Protect
28
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
FLASH MEMORY
K9F2808U0C
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 12 shows the operation sequence.
Figure 12. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
I/Ox
tWHR
00h
90h
tREA
Address. 1cycle
ECh
Device
Code*
Maker code
Device code
Device
Device Code*
K9F2808U0C
73h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 13 below.
Figure 13. RESET Operation
tRST
R/B
I/Ox
FFh
Table5. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
29
FLASH MEMORY
K9F2808U0C
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 14). Its value can be
determined by the following guidance.
Rp
VCC
ibusy
VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Figure 14. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
1.2
300
3m
200
0.8
2m
3.6 tf
3.6
3.6
3.6
1K
2K
3K
Rp(ohm)
4K
200n
Ibusy [A]
400
2.4
tr
100
100n
0.6
1m
Rp value guidance
Rp(min, 3.3V part) =
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
30
FLASH MEMORY
K9F2808U0C
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down and recovery time of minimum 10µs is required before internal circuit gets ready for any command
sequences as shown in Figure 15. The two step command sequence for program/erase provides additional software protection.
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Figure 15. AC Waveforms for Power Transition
3.3V device : ~ 2.5V
3.3V device : ~ 2.5V
VCC
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High
≈
WP
10µs
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WE
31