K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
Document Title
8M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
July 17th 2000
Preliminary
Initial issue.
1. Changed endurance : 1 million -> 100K program/erase cycles
0.1
1. Changed don’t care mode in address cycles
Nov. 20th 2000
- *X can be "High" or "Low" => *L must be set to "Low"
2. Explain how pointer operation works in detail.
3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
4. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
0.2
1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
≈
0.0
~ 2.5V
Jul. 25th. 2001
~ 2.5V
High
≈
VCC
WP
1µ
≈
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 100ns --> 20ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the
SAMSUNG branch office near you.
1
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
8M x 8 Bit NAND Flash Memory
FEATURES
GENERAL DESCRIPTION
• Voltage Supply : 2.7V ~ 3.6V
• Organization
- Memory Cell Array : (8M + 256K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
• Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (8K + 256)Byte
• 528-Byte Page Read Operation
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program Time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 years
• Command Register Operation
• 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
The K9F6408U0B is a 8M(8,388,608)x8bit NAND Flash Memory with a spare 256K(262,144)x8bit. Its NAND cell provides the
most cost-effective solution for the solid state mass storage
market. A program operation programs the 528-byte page in
typical 200µs and an erase operation can be performed in typical 2ms on an 8K-byte block. Data in the page can be read out
at 50ns cycle time per byte. The I/O pins serve as the ports for
address and data input/output as well as command inputs. The
on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal
verification and margining of data. Even the write-intensive systems can take advantage of the K9F6408U0B′s extended reliability of 100K program/erase cycles by providing ECC(Error
Correcting Code) with real time mapping-out algorithm. These
algorithms have been implemented in many mass storage
applications and also the spare 16 bytes of a page combined
with the other 512 bytes can be utilized by system-level ECC.
The K9F6408U0B is an optimum solution for large nonvolatile
storage applications such as solid state file storage, digital
voice recorder, digital still camera and other portable applications requiring non-volatility.
PIN CONFIGURATION
PIN DESCRIPTION
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Pin Name
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
I/O0 ~ I/O7
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
44(40) TSOP (II)
STANDARD TYPE
NOTE : Connect all VCC and VSS pins of each device to power supply outputs.
Do not leave VCC or VSS disconnected.
2
Pin Function
Data Input/Outputs
CLE
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
GND
GND input for enabling spare area
R/B
Ready/Busy output
VCC
Power
VSS
Ground
N.C
No Connection
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
Figure 1. FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
Y-Gating
2nd half Page Register & S/A
X-Buffers
Latches
& Decoders
A9 - A22
64M + 2M Bit
NAND Flash
ARRAY
Y-Buffers
Latches
& Decoders
A 0 - A7
(512 + 16)Byte x 16384
1st half Page Register & S/A
A8
Y-Gating
Command
Command
Register
I/O Buffers & Latches
VSS
CE
RE
WE
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
1 Block =16 Pages
= (8K + 256) Byte
16K Pages
(=1,024 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Byte
1 Block = 528 Byte x 16 Pages
= (8K + 256) Byte
1 Device = 528 Byte x 16Pages x 1024 Blocks
= 66 Mbits
8 bit
512Byte
16 Byte
Page Register
512 Byte
I/O 0
I/O 1
I/O 2
I/O 0 ~ I/O 7
16 Byte
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
*L
*L
Column Address
Row Address
(Page Address)
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
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K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F6408U0B is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 4,224 NAND structures of 16 cells. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F6408U0B.
The K9F6408U0B has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block
address loading. The 8M byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F6408U0B.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
(1)
Read 1
-
00h/01h
Read 2
50h
Acceptable Command during Busy
(2)
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Block Erase
60h
D0h
Read Status
70h
-
NOTE : 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
2. The 50h command is valid only when the GND input(pin #40) is low level.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
4
O
O
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
GND (Pin # 40)
Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
K9F6408U0B-TCB0
Symbol
Rating
Unit
VIN
-0.6 to + 4.6
V
VCC
-0.6 to + 4.6
V
-10 to + 125
TBIAS
K9F6408U0B-TIB0
Storage Temperature
°C
-40 to + 125
TSTG
°C
-65 to + 150
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F6408U0B-TCB0:TA=0 to 70°C, K9F6408U0B-TIB0:TA=-40 to 85°C)
Symbol
Min
Typ.
Max
Unit
Supply Voltage
Parameter
VCC
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Sequential Read
ICC1
Program
ICC2
Erase
ICC3
Stand-by Current(TTL)
ISB1
Stand-by Current(CMOS)
ISB2
Min
Typ
Max
-
10
20
-
-
10
20
-
-
10
20
-
-
1
-
10
50
Test Conditions
tRC=50ns,CE=VIL, IOUT=0mA
CE=VIH, WP=GND input (Pin #40)
= 0V/VCC
CE=VCC-0.2, WP=GND input (Pin
#40) = 0V/VCC
Input Leakage Current
ILI
VIN=0 to 3.6V
-
-
±10
Output Leakage Current
ILO
VOUT=0 to 3.6V
-
-
±10
Input High Voltage,All inputs
VIH
-
2.0
-
VCC+0.3
Input Low Voltage, All inputs
VIL
-
-0.3
-
0.8
Output High Voltage Level
VOH
IOH=-400µA
2.4
-
-
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
Output Low Current(R/B)
IOL(R/B)
VOL=0.4V
8
10
-
6
Unit
mA
µA
V
mA
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
1014
1020
1024
Blocks
NOTE :
1. The K9F6408U0B may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
AC TEST CONDITION
(K9F6408U0B-TCB0:TA=0 to 70°C, K9F6408U0B-TIB0:TA=-40 to 85°C, VCC=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL = 50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
RE
GND
WP
H
L
L
WE
H
X
X
Mode
L
H
L
H
X
X
H
L
L
H
X
H
L
H
L
H
X
H
L
L
L
H
L/H(3)
H
Data Input
L
L
L
H
L/H(3)
X
Sequential Read & Data Output
L
L
L
H
H
L/H(3)
X
During Read(Busy)
(3)
Read Mode
Write Mode
Command Input
Address Input(3clock)
Command Input
Address Input(3clock)
X
X
X
X
X
L/H
H
During Program(Busy)
X
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/VCC(2) 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
3. When GND input is high, spare area is deselected.
Program/Erase Characteristics
Parameter
Symbol
Program Time
Number of Partial Program Cycles
in the Same Page
Block Erase Time
tPROG
Main Array
Spare Array
Nop
tBERS
7
Min
Typ
Max
Unit
-
200
500
µs
-
-
2
cycles
-
-
3
cycles
-
2
4
ms
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE Setup Time
tCS
0
-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25
-
ns
ALE Setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data Setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
50
-
ns
WE High Hold Time
tWH
15
-
ns
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
tR
-
10
µs
ALE to RE Delay( ID read )
tAR1
20
-
ns
ALE to RE Delay(Read cycle)
tAR2
50
-
ns
CLE to RE Delay
tCLR
50
-
ns
CE to RE Delay( ID read)
tCR
100
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
30
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
RE Access Time
tREA
-
35
ns
RE High to Output Hi-Z
tRHZ
15
30
ns
Data Transfer from Cell to Register
CE High to Output Hi-Z
tCHZ
-
20
ns
RE High Hold Time
tREH
15
-
ns
Output Hi-Z to RE Low
tIR
0
-
ns
Last RE High to Busy(at sequential read)
tRB
-
100
ns
CE High to Ready(in case of interception by CE at read)
tCRY
-
50 +tr(R/B)(1)
ns
(2)
tCEH
100
-
ns
RE Low to Status Output
tRSTO
-
35
ns
CE Low to Status Output
tCSTO
-
45
ns
WE High to RE Low
tWHR
60
-
ns
tREADID
-
35
ns
tRST
-
5/10/500(3)
µs
CE High Hold Time(at the last serial read)
RE access time(Read ID)
Device Resetting Time(Read/Program/Erase)
NOTE :
1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
2. To break the sequential read cycle, CE must be held high for longer time than tCEH.
3. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
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K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level or as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block
has non-FFh data at the column address of 517. Since the invalid block information is also erasable in most cases, it is impossible to
recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the
original invalid block information and create the invalid block table via the following suggested flow chart(Figure 1). Any intentional
erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
Check "FFh" ?
*
Check "FFh" at the column address 517
of the 1st and 2nd page in the block
Yes
No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
9
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Write
Read
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Single Bit Failure
ECC
Verify ECC -> ECC Correction
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Wait for tR Time
Write Data
Write 10h
Verify Data
Read Status Registe
No
*
Program Error
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
I/O 0 = 0 ?
Yes
10
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
No
Erase Error
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
{
nth
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
1
(page)
* Step1
When an error happens in the nth page of the Block ’A’during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’by creating an ’invalid Block’table or other appropriate scheme.
11
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
Pointer Operation of K9F6408U0B
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’area(0~255byte), ’01h’command sets the pointer to ’B’area(256~511byte), and ’50h’command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’or ’50h’is sustained until another address pointer command is inputted. ’01h’command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’command is written. A complete read operation prior to ’80h’command is not necessary. To program data starting from ’B’
area, ’01h’command must be inputted right before ’80h’command is written.
Table 1. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 2. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’area(0~255), and sustained
Address / Data input
Address / Data input
00h
80h
10h
00h
’A’,’B’,’C’area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’area(256~512), and will be reset to
’A’area after every program operation is executed.
Address / Data input
Address / Data input
01h
80h
10h
01h
’B’, ’C’area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’area can be programmed.
80h
’50h’command can be omitted.
12
10h
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
WE
ALE
I/O0~7
80h
Start Add.(3Cycle)
Data Input
Data Input
(Min. 10ns)
10h
(Max. 45ns)
tCS
tCH
tCEA
CE
CE
tREA
RE
tWP
WE
I/O0~7
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
out
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 4. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
≈
CE
RE
ALE
tR
R/B
WE
I/O0~7
00h
Data Output(sequential)
Start Add.(3Cycle)
13
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
* Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/O0~7
* Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
CE
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tALH
ALE
tDS
I/O0~7
tDH
tDS
tDH
A9~A16
A0~A7
14
tDS
tDH
A17~A22
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
tWP
tWP
≈
ALE
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/O0~7
DIN 511
DIN 1
≈
DIN 0
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tREH
≈
tREA
tREA
tCHZ*
tREA
RE
tRHZ*
Dout
I/O0~7
Dout
≈
tRHZ*
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
15
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
* Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCSTO
tCHZ*
tWHR
RE
tDS
I/O0~7
tDH
tIR
tRSTO
tRHZ*
Status Output
70h
READ1 OPERATION(READ ONE PAGE)
CLE
tCEH
CE
tCHZ
tWC
WE
tWB
tCRY
tAR2
ALE
tRHZ
tRC
tR
≈
RE
I/O0~7
00h or 01h A0 ~ A7
A9 ~ A16
Column
Address
R/B
A17 ~ A22
Dout N
Page(Row)
Address
Busy
16
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout 527
tRB
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
READ1 OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tAR2
ALE
tRC
tR
RE
tRR
I/O0~7
A9 ~ A16
00h or 01h A0 ~ A7
Column
Address
A17 ~ A22
Dout N
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Busy
R/B
READ2 OPERATION(READ ONE PAGE)
CLE
CE
WE
tR
tWB
tAR2
ALE
≈
tRR
I/O0~7
50h
A0 ~ A7
Dout
511+M
A9 ~ A16 A17 ~ A22
R/B
Dout
511+M+1
≈
RE
Dout 527
Selected
Row
M Address
A0~A3 : Valid Address
A4~A7 : Don′t care
512
16
Start
address M
17
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
SEQUENTIAL ROW READ OPERATION
CLE
CE
WE
Dout
N
A0 ~ A7 A9 ~ A16 A17 ~ A22
Dout
N+1
Dout
N+2
≈
00h
Dout
527
Dout
0
R/B
Dout
2
Dout
527
≈
Ready
Busy
Dout
1
≈
≈
RE
I/O0~7
≈
ALE
Busy
M
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
tWB
tPROG
ALE
I/O0~7
80h
A0 ~ A7 A9 ~ A16 A17 ~ A22
Sequential Data Column
Input Command Address
Page(Row)
Address
Din
N
Din
N+1
≈≈
RE
1 up to 528 Byte Data
Serial Input
10h
70h
Program
Command
Read Status
Command
≈
R/B
Din
527
18
I/O0
I/O0=0 Successful Program
I/O0=1 Error in Program
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
BLOCK ERASE OPERATION(ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/O0~7
60h
A9 ~ A16 A17 ~ A22
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
≈
Page(Row)
Address
Erase Command
Read Status
Command
MANUFACTURE & DEVICE ID READ OPERATION
tCLR
CLE
CE
WE
tAR1
ALE
RE
tREADID
I/O 0 ~ 7
90h
Read ID Command
00h
ECh
Address. 1cycle
Maker Code
19
E6h
Device Code
I/O0=0 Successful Erase
I/O0=1 Error in Erase
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10µs(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output
of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE.
High to low transitions of the RE clock output the data stating from the selected column address up to the last column address(column 511 or 527 depending on the state of GND input pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10µs again allows reading the selected page.The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A0 to A3 set the starting
address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically
incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The
Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 3 through 6 show typical sequence and timings for each read operation.
Figure 3. Read1 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0 ~ 7
00h
01h
Data Output(Sequential)
Start Add.(3Cycle)
A0 ~ A7 & A9 ~ A22
(00h Command)
1st half array
(01h Command)*
2nd half array
Data Field
Spare Field
1st half array
2nd half array
Data Field
Spare Field
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
20
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
Figure 4. Read2 Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/O0 ~ 7
50h
Start Add.(3Cycle)
Data Output(Sequential)
A0 ~ A3 & A9 ~ A22
(A4 ~ A7 :
Don't Care)
Spare Field
1st half array
2nd half array
Data Field
Spare Field
≈
Figure 5. Sequential Row Read1 Operation
tR
tR
tR
R/B
I/O0 ~ 7
00h
Start Add.(3Cycle)
Data Output
Data Output
1st
01h
Data Output
2nd
(528 Byte)
A0 ~ A7 & A9 ~ A22
Nth
(528 Byte)
(GND Input=L, 00h Command)
(GND Input=L, 01h Command)
(GND Input=H, 00h Command)
1st half array
1st half array
1st half array
2nd half array
Data Field
2nd half array
2nd half array
1st
2nd
1st
2nd
1st
2nd
Nth
Nth
Nth
Spare Field
Data Field
21
Spare Field
Data Field
Spare Field
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
tR
≈
Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low)
tR
tR
R/B
I/O0 ~ 7
50h
Start Add.(3Cycle)
Data Output
Data Output
Data Output
1st
2nd
(16 Byte)
Nth
(16 Byte)
A0 ~ A3 & A9 ~ A22
(A4 ~ A7 :
Don′t Care)
1st half array
2nd half array
1st
2nd
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done
in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be
loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the
attached technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered, with
RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B output, or
the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 7). The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command
mode until another valid command is written to the command register.
Figure 7. Program & Read Status Operation
tPROG
R/B
I/O0 ~ 7
80h
Address & Data Input
10h
70h
A0 ~ A7 & A9 ~ A22
528 Byte Data
I/O0
Fail
22
Pass
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A13 to A22 is valid while A9 to A12 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked.
Figure 8 details the sequence.
Figure 8. Block Erase Operation
tBERS
R/B
I/O0 ~ 7
60h
Address Input(2Cycle)
I/O0
70h
D0h
Pass
Block Add. : A9 ~ A22
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table2. Read Status Register Definition
I/O #
Status
Definition
I/O0
Program / Erase
"0" : Successful Program / Erase
"1" : Error in Program / Erase
I/O1
I/O2
I/O3
"0"
Reserved for Future
Use
"0"
"0"
I/O4
"0"
I/O5
"0"
I/O6
Device Operation
I/O7
Write Protect
23
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (E6h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence.
Figure 9. Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR1
ALE
RE
I/O0 ~ 7
90h
tREADID
00h
ECh
Address. 1 cycle
Maker code
E6h
Device code
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to
"1"s. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is
high. Refer to table 3 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is
not necessary for normal operation. Refer to Figure 10 below.
Figure 10. RESET Operation
tRST
R/B
I/O0 ~ 7
FFh
Table3. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
24
K9F6408U0B-TCB0, K9F6408U0B-TIB0
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 11). Its value can
be determined by the following guidance.
Rp
ibusy
VCC
Ready Vcc
R/B
open drain output
2.0V
0.8V
Busy
tf
tr
GND
Device
Fig 12 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
200n
290
3m
1.65
189
1.1
2m
4.2
4.2
4.2
2K
3K
Rp(ohm)
4K
tr
96
100n
0.825
4.2
tf
1K
Rp value guidance
Rp(min) =
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
25
1m
Ibusy [A]
381
3.3
Package Dimensions
FLASH MEMORY
DATA PROTECTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down and recovery time of minimum 1µs is required before internal circuit gets ready for any command
sequences as shown in Figure 12. The two step command sequence for program/erase provides additional software protection.
≈
Figure 12. AC Waveforms for Power up sequence
~ 2.5V
~ 2.5V
High
≈
VCC
≈
WP
10µs
≈
WE
26
Package Dimensions
FLASH MEMORY
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
44(40) - TSOP2 - 400F
Unit :mm/Inch
0~8°
0.25
TYP
0.010
#23(21)
#1
10.16
0.400
11.76±0.20
0.463±0.008
0.45~0.75
0.018~0.030
#44(40)
0.50
0.020
#22(20)
+0.10
0.15 -0.05
1.00±0.10
0.039±0.004
18.81
Max.
0.741
18.41±0.10
0.725±0.004
1.20
Max.
0.047
+0.004
0.006 -0.002
(
0.805
)
0.032
0.35±0.10
0.014±0.004
0.05
Min.
0.002
0.10
MAX
0.004
0.80
0.0315
27