PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
INTRODUCTION
The KB8821/22/23 are high performance dual frequency synthesizers with integrated prescalers designed for RF operation
up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The KB8821/22/23 contain dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or
64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or
a 16/17 prescaler.
Using a proprietary digital phase-locked-loop technique, the
KB8821/22/23 have linear phase detector characteristic and
can be used for very stable, low noise local oscillator signal.
Supply voltage can range from 2.7V to 4.0V. The KB8821/22/
23 are now available in a 20-TSSOP/24-QFN package.
20-TSSOP-225
ORDERING INFORMATION
FEATURES
Device
• Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA)
KB8821/22/23
• Operating voltage range : 2.7 ~ 4.0V
KB8821/22/23
• Selectable power saving mode(Icc=1uA typical @3V)
Package
Tem. Range
20-TSSOP-225 -40 ~ +85°C
24-QFN*
-40 ~ +85°C
* QFN : Quad Flat Non-leaded(see Addendum).
• Dual modulus prescaler :
KB8821/22
KB8823
KB8821/22/23
APPLICATIONS
(RF) 64/65 or 128/129
(RF) 32/33 or 64/65
(IF) 8/9 or 16/17
• Cellular telephone systems : KB8821
• Portable wireless communications : KB8822
(PCS/PCN, cordless)
• Programmability via serial bus interface
• No dead-zone PFD
• Variable charge pump output current
• Wireless Local Area Networks (W-LANs)
: KB8823
• High speed lock mode
• Other wireless communication systems
BLOCK DIAGRAM
finRF
finRF
+
-
RF
Prescaler
RF
N Counter
RF
Phase
Detector
RF
Charge
Pump
CPoRF
RF
LD
CLOCK
LE
DATA
Serial Data Control
foLD
Data Out
Multiplexer
RF
R Counter
foLD
OSCin
IF
R Counter
finIF
finIF
+
-
IF
Prescaler
IF
LD
IF
N Counter
IF
Phase
Detector
IF
Charge
Pump
CPoIF
Figure 1. BLOCK DIAGRAM
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
BLOCK DIAGRAM- Continued
VDD1 1
foLD
Data Out
Multiplexer
RF
LD
VP1 2
RF
Charge
Pump
IF
LD
RF
Phase
Detector
20 VDD2
IF
Phase
Detector
19 VP2
IF
Charge
Pump
18 CPoIF
CPoRF 3
RF Prescaler
IF Prescaler
GND 4
17 GND
+
finRF 5
–
Prescaler
Control
RF
Programmable
Counter
IF
Programmable
Counter
Prescaler
Control
–
+
16 finIF
15 finIF
finRF 6
RF N-Latch
GND 7
IF N-Latch
20-bit Shift Register
OSCin 8
RF R-Latch
GND 9
RF Reference
Counter
IF R-Latch
IF Reference
Counter
foLD 10
2-bit
Control
14 GND
13 LE
12 DATA
11 CLOCK
Figure 2. Detailed block diagram
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
PIN CONFIGURATION
VDD1 1
20 VDD2
Vp1 2
19 Vp2
CPoRF 3
18 CPoIF
GND 4
(Digital)
17 GND
(Digital)
KB8821
finRF 5
16 finIF
KB8822
finRF 6
15 finIF
KB8823
GND 7
(Analog)
OSCin 8
Top View
GND 9
(Digital)
14 GND
(Analog)
13 LE
12 DATA
foLD 10
11 CLOCK
20-TSSOP
20-Lead(0.173 Wide) Thin Shrink Small
Outline Package(20-TSSOP)
1. pin #9 = pin #17(internally connected).
2. Do not tie up Vp and VDD
: Vp is the source of digital noises. The power
for analog part is supplied by VDD. If Vp and
VDD are tied together, noisy Vp corrupts the
power source for the analog part.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
PIN DESCRIPTION
Pin No
Symbol
I/O
Description
1
VDD1
-
Power supply voltage input for the RF PLL part. VDD1 must equal VDD2. In
order to reject supply noise, bypass capacitors must be placed as close as
possible to this pin and be connected directly to the ground plane.
2
Vp1
-
Power supply voltage input for RF charge pump(≥ VDD1).
3
CPoRF
O
Internal RF charge pump output for connection to an external loop filter whose
filtered output drives an external VCO.
4
GND
-
Ground for RF digital blocks.
5
finRF
I
RF prescaler input. The signal comes from the external VCO.
6
finRF
I
The complementary input of the RF prescaler. A bypass capacitor must be
placed as close as possible to this pin and be connected directly to the ground
plane. The bypass capacitor is optional with some loss of sensitivity.
7
GND
-
Ground for RF analog blocks.
8
OSCin
I
Reference counter input. TCXO is connected via a coupling capacitor.
9
GND
-
Ground for IF digital blocks.
10
foLD
O
Multiplexed output of the RF/IF programmable counters, the reference
counters, the lock detect signals and the shift registers. The output level is
CMOS level. (see fout Programmable Truth Table)
11
CLOCK
I
CMOS clock input. Serial data for the various counters is transfered into the
22-bit shift register on the rising edge of the clock signal.
12
DATA
I
Binary serial data input. The MSB of CMOS input data is entered first. The
control bits are on the last two bits. CMOS input.
13
LE
I
Load enable CMOS input. When LE becomes high, the data in the shift
register is loaded into one of the four latches(by the control bits).
14
GND
-
Ground for IF analog blocks.
15
finIF
I
The complementary input of the IF prescaler. A bypass capacitor must be
placed as close as possible to this pin and be connected directly to the ground
plane. The bypass capacitor is optional with some loss of sensitivity.
16
finIF
I
IF prescaler input. The signal comes from the external VCO.
17
GND
-
Ground for IF digital blocks.
18
CPoIF
O
Internal IF charge pump output for connection to an external loop filter whose
filtered output drives an external VCO.
19
Vp2
-
Power supply voltage input for IF charge pump(≥ VDD2)
20
VDD2
-
Power supply voltage input for the IF PLL part. VDD1 must equal VDD2. In
order to reject supply noise, bypass capacitors must be placed as close as
possible to this pin and be connected directly to the ground plane.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
EQUIVALENT CIRCUIT DIAGRAM
♦ CLOCK, DATA, LE
♦ foLD
♦ OSCin
♦ CPoRF, CPoIF
♦ finRF, finRF, finIF, finIF
finRF,
finIF
finRF,
finIF
Vbias
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Power Supply Voltage
VDD
5.5
V
Power Dissipation
PD
600
mW
Operating Temperature
Ta
-40°C ~ +85oC
°C
Storage Temperature
TSTG
-65°C ~ +150oC
°C
ELECTROSTATIC CHARACTERISTICS
Characteristic
Pin No.
ESD level
Unit
Human Body Model
All
< ±2000
V
Machine Model
All
< ±300
V
Charged Device Model
All
< ±800
V
** These devices are ESD sensitive. These devices must be handled in the ESD protected environment.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40οC≤Ta≤85οC
Characteristic
Symbol
Test Conditions
Unless otherwise specified)
Min.
Typ.
Max.
VDD
2.7
3.0
4.0
VP
VDD
3.0
4.0
Power Supply Voltage
Power Supply
Current
V
KB8823 RF + IF
5.5
KB8823 RF Only
4.0
KB8822 RF + IF
4.5
KB8822 RF Only
IDD
VDD=2.7V to 4.0V
3.0
KB8821 RF + IF
3.5
KB8821 RF Only
2.0
KB882x IF Only
1.5
Power down Current
Unit
IPWDN
VDD=3.0V
1.0
mA
10
µA
Digital inputs : CLOCK, DATA and LE
High-Level Input Voltage
VIH
VDD=2.7V to 4.0V
Low-Level Input Voltage
VIL
VDD=2.7V to 4.0V
High-Level Input Current
IIH
VIH= VDD=4.0V
Low-Level Input Current
IIL
VIL=0V, VDD=4.0V
0.7VDD
V
0.3VDD
V
-1.0
+1.0
µA
-1.0
+1.0
µA
+100
µA
Reference Divider Input : OSCin
IIHR
VIH= VDD=4.0V
IILR
VIL=0V, VDD=4.0V
Input Current
-100
µA
VDD-0.4
V
Digital Output : foLD
High Level Output Voltage
VOH
Iout = -500µA
Low Level Output Voltage
VOL
Iout = +500µA
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0.4
V
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40οC≤Ta≤85οC
Characteristic
Symbol
Test Conditions
Unless otherwise specified)- Continued
Min.
Typ.
Max.
Unit
Charge Pump Outputs : CPoRF, CPoIF
ICP-SRC
VCP=VP/2, ICPo=Low
-1.125
ICP-SINK
VCP=VP/2, ICPo=Low
+1.125
ICP-SRC
VCP=VP/2, ICPo=High
-4.5
ICP-SINK
VCP=VP/2, ICPo=High
+4.5
Charge Pump Leakage Current
ICPL
0.5V ≤ VCP ≤ VP-0.5V
ICP-SINK
vs
ICP-SRC
VCP=VP/2
Output Current Sink vs. Source
Mismatch*
Ta=25oC
3
Output Current Magnitude Variation
vs. Temperature**
ICP vs T
VCP=VP/2
10
Output Current Magnitude Variation
vs. Voltage***
ICP vs
VCP
Charge Pump Output Current
-2.5
mA
+2.5
nA
10
%
%
0.5V ≤ VCP ≤ VP-0.5V
10
Ta=25oC
15
%
Programmable Divider
KB8823
Operating
Frequency
KB8822
finRF
0.5
2.5
0.2
2.0
0.1
1.2
VDD=3.0V
45
520
VDD=3.0V
-15
0
VDD=4.0V
-10
0
VDD=2.7V to 4.0V
-10
0
dBm
10
MHz
40
MHz
VDD=2.7V to 4.0V
KB8821
Operating Frequency
RF Input Sensitivity
IF Input Sensitivity
Phase Detector Frequency
finIF
PfinRF
PfinIF
GHz
MHz
dBm
fPD
Reference Divider
Operating Frequency
OSCin
5
Input Sensitivity
VOSCin
0.5
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VPP
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40οC≤Ta≤85οC
Characteristic
Symbol
Test Conditions
Unless otherwise specified)- Continued
Min.
Typ.
Max.
Unit
10
MHz
Serial Data Control
CLOCK Frequency
fCLOCK
CLOCK Pulse Width High
tCWH
50
ns
CLOCK Pulse Width Low
tCWL
50
ns
DATA Set Up Time to CLOCK
Risng Edge
tDS
50
ns
DATA Hold Time after CLOCK
Rising Edge
tDH
10
ns
LE Pulse Width
tLEW
50
ns
CLOCK Rising Edge to LE Rising
Edge
tCLE
50
ns
<For Charge Pump items>
Ia=Charge pump sink current at Vcp=Vp-∆V,
Ib=Charge pump sink current at Vcp=Vp/2,
Ic=Charge pump sink current at Vcp=∆V
Id=Charge pump source current at Vcp=Vp-∆V, Ie=Charge pump source current at Vcp=Vp/2, If=Charge pump source current at Vcp=∆V
∆V=Voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents bec
ome flat.
* Output Current Sink vs. Source Mismatch = [| Ib|-|Ie|] / [0.5 * {| Ib|+|Ie|}] * 100 (%)
** Output Current Magnitude Variation vs. Temperature =
[| Ib @any temp.| - |Ib @ 25οC|] / | Ib @ 25οC| * 100 (%) and [|Ie @any temp.| - |Ie @ 25οC|] / |Ie @ 25οC| * 100 (%)
*** Output Current Magnitude Variation vs. Voltage =
[0.5 * {|Ia|-|Ic|}] / [0.5 * {|Ia|+|Ic|}] * 100 (%) and [0.5 * {|Id|-|If|}] / [0.5 * {|Id|+|If|}] * 100 (%)
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
FUNCTIONAL DESCRIPTION
The Samsung KB882x are dual PLL frequency synthesizer ICs. KB882x combined with external LPFs andexternal VCOs form PLL frequency synthesizers. They include serial data control, R counter, N counter, prescaler,
phase detector, charge pump, and etc.(Figure 1).
Serial data is moved into 20-bit shift register on the rising edge of the clock(Figure 2). These data enters MSB
first. When LE becomes HIGH, data in the shift register is moved into one of the 4 latches(by the 2-bit control).
The divide ratios of the prescaler and the counters are determined by the data stored in the latches. The external
VCO output signal is divided by the prescaler and the N counter. External reference signal is divided by the R
counter. These two signals are the two input signals to the phase detector. The phase detector drives the charge
pump by comparing frequencies and phases of the above two signals.The charge pump and the external LPF
make the control voltage for the external VCO and finally the VCO generates the appropriate frequency signal.
Serial Data Input Timing
MSB
DATA N20(R20)
LSB
N19(R19)
N10(R10)
N9(R9)
C2
C1
CLOCK
tCWL
tDS
tLEW
tCWH
LE
tCLE
tDH
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
FUNCTIONAL DESCRIPTION- Continued
Control Bits
Control Bits
DATA Location
C1
C2
0
0
IF R Counter
0
1
RF R Counter
1
0
IF N Counter
1
1
RF N Counter
Programmable Reference Counter(IF / RF R Counter)
If the Control Bits are 00(IF) or 01(RF), data is moved from the 20-bit shift register into the R-latch which sets
the reference counter. Serial data format is shown in the table below.
MSB
LSB
C1
C2
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Division Ratio of the R Counter, R
Program Mo
des
Control Bits
♦ 15-Bit Programmable Reference Counter Ratio
Division
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Ratio
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Division ratio : 3 to 32767
Data are shifted in MSB first
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
FUNCTIONAL DESCRIPTION- Continued
Programmable Counter(N Counter)
If the Control Bits are 10(IF) or 11(RF), data is transferred from the 20-bit shift register into the N-latch. N Counter
consists of 7-bit swallow counter(A counter) and 11-bit main counter(B counter). Serial data format is shown
below.
LSB
C1
C2
MSB
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Division Ratio of the N Counter, N
Program
Modes
Control Bits
♦ 7-Bit Swallow Counter Division Ratio(A Counter)
RF
IF
Division
N
N
N
N
N
N
N
Division
N
N
N
N
N
N
N
Ratio(A)
7
6
5
4
3
2
1
Ratio(A)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
1
0
0
0
0
0
0
1
1
X
X
X
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
15
X
X
X
1
1
1
1
Division ratio : 0 to 127
B≥ A
Division ratio : 0 to 15
B≥ A
X = DON’T CARE condition
♦ 11-Bit Main Counter Division Ratio(B Counter)
Division
N
N
N
N
N
N
N
N
N
N
N
Ratio
18
17
16
15
14
13
12
11
10
9
8
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Division ratio : 3 to 2047
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
FUNCTIONAL DESCRIPTION- Continued
Pulse Swallow Function
fVCO=[ ( P X B ) + A ] x fOSCin / R
fVCO : External VCO output frequency
P : Preset modulus of dual modulus prescaler
(for KB8821/22 RF:P=64 or 128,
for KB8823 RF:P=32 or 64,
for IF: P=8 or 16)
B : 11-bit main counter division ratio (3 ≤ B ≤ 2047)
A : 7-bit swallow counter division ratio
(for RF: 0 ≤ Α ≤ 127,
for IF: 0 ≤ Α ≤ 15, Α ≤ B)
fOSCin : External reference frequency(from external oscillator)
R : 15-bit reference counter division ratio (3 ≤ R ≤ 32767)
Program Mode
C1
C2
R16
R17
R18
R19
R20
0
0
IF Phase
Detector Polarity
IF ICPo
IF CPoIF
High Impedance
IF
LD
IF
Fo
0
1
RF Phase
Detector Polarity
RF ICPo
RF CPoIF
High Impedance
RF
LD
RF
Fo
C1
C2
N19
N20
1
0
IF Prescaler
Pwdn IF
1
1
RF Prescaler
Pwdn RF
♦ Mode Select Truth Table
RF Prescaler
KB8821/22
(KB8823)
Phase Detector Polarity
CPoIF High Impedance
ICPo
IF Prescaler
Pwdn
0
Negative
Normal Operation
Low
8/9
64/65
(32/33)
Pwr Up
1
Positive
High Impedance
High
16/17
128/129
(64/65)
Pwr Dn
* The charge pump output current of ICPo LOW = 1/4 × ICPo HIGH.
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
FUNCTIONAL DESCRIPTION- Continued
VCO Output Frequency
♦ Phase Detector Polarity
Depending on VCO characteristics, R16 bit should be set
as follows :
VCO characteristics are positive like (1) : R16 HIGH
VCO characteristics are negative like (2) : R16 LOW
VCO Characteristics
(1)
(2)
VCO Input Voltage
♦ foLD (Pin10) Output Truth Table
RF R19
(RF LD)
IF R19
(IF LD)
RF R20
(RF fo)
IF R20
(IF fo)
foLD Output State
0
0
0
0
Disabled (default LOW)
0
1
0
0
IF Lock Detect
1
0
0
0
RF Lock Detect
1
1
0
0
RF and IF Lock Detect
0
0
0
1
IF Reference Divider Output
0
0
1
0
RF Reference Divider Output
0
1
0
1
IF Programmable Divider Output
0
1
1
0
RF Programmable Divider Output
0
0
1
1
High Speed Lock mode
0
1
1
1
IF Counter Reset
1
0
1
1
RF Counter Reset
1
1
1
1
RF and IF Counter Reset
- When the PLL is locked and a lock detect mode is selected, the foLD output is HIGH, with narrow pulses
LOW.
- Counter Reset mode resets R & N counters.
- The high speed lock mode sets the foLD output pin to be connected to ground with a low impedance
(≤110Ω).
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
FUNCTIONAL DESCRIPTION- Continued
♦ Powerdown mode operation
There are synchronous and asynchronous powerdown modes for KB8821/22/23.
Synchronous powerdown mode occurs if R18 bit is LOW, N20 bit is HIGH and charge pump output is in high
impedance state. In the synchronous power down mode, the powerdown function is activated by the charge
pump to diminish unwanted frequency jumps. Asynchronous powerdown mode occurs if R18 bit is HIGH and
N20 bit is HIGH.
When the PLL goes to either synchronous or asynchronous powerdown mode, preamp becomes debiased, R &
N counters keeps their load conditions and the charge pump becomes high impedance state. The oscillator circuitry function becomes disabled only when both IF and RF powerdown bits are activated, i.e. N20 HIGH.
The PLL returns to an active powerup mode when N20 bit becomes LOW(either in synchronous or asynchronous
modes).
R18
N20
Powerdown mode status
0
0
PLL active
1
0
PLL active, only charge pump high impedance
0
1
Synchronous powerdown
1
1
Asynchronous powerdown
Phase Detector and Charge pump Characteristics
Phase difference detection range : -2π ~ +2π
When R16 = HIGH
fr
fp
LD
CPo
fr>fp
fr=fp
fr<fp
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fr<fp
fr<fp
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PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
RF SENSITIVITY MEASUREMENT CIRCUIT
2.7V ~ 4.0V
RF
Signal
Generator
50Ω
Microstrip
100pF
VDD
fin
VP
10dB ATTN
100pF
51Ω
fin
100pF 2.2µF
100pF
2.2µF
OSCin
LE
foLD
Frequency
Counter
DATA
CLOCK
12kΩ
PC
Parallel
Port
39kΩ
** N=10,000 R=50 P=64
** Sensitivity limit is determined when the error of the divided RF output( foLD) becomes
≥1 Hz.
99-06-15
16
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
TYPICAL APPLICATION CIRCUIT
VP
VCO
0.01µF
100pF
1000pF
Reference
Input
R1
RF out
10pF
51Ω
100pF
VDD
C2
0.01µF
C1
100pF
foLD
Rin
100pF
18Ω
0.01µF
10
9
8
7
6
5
4
3
2
1
foLD
GND
OSCin
GND
finRF
finRF
GND
CPoRF
VP1
VDD1
KB882x 20-TSSOP
CLOCK DATA
11
12
LE
GND
finIF
finIF
GND
CPoIF
VP2
VDD2
13
14
15
16
17
18
19
20
From
Controller
IF out
10pF
0.01µF
Rin
100pF
18Ω
VDD
100pF
VCO
0.01µF
100pF
Vp
R2
C4
C3
100pF
0.01µF
** The role of Rin : Rin makes VCO output power go to the load rather than the PLL.
The value of Rin depends on the VCO power level.
99-06-15
17
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
PACKAGE DIMENSIONS
#11
4.40 ¡¾ 0.20
0.173 ¡¾ 0.008
0.15 x +0.10
-0.05
0.006 x +0.004
-0.002
5.72
0.225
0 ~ 8o
6.40 ± 0.30
0.252 ± 0.012
#20
0.50 ¡¾ 0.20
0.020 ¡¾ 0.008
#10
0.90 ± 0.20
0.059 ± 0.008
6.90
MAX
0.272
6.40 ¡¾ 0.20
0.252 ¡¾ 0.008
1.10
0.073 MAX
#1
0.30
0.012
0.65
0.026
0.05
0.002 MIN
0.10MAX
0.004MAX
0.22 ¡¾ 0.10
0.009 ¡¾ 0.004
20-Lead TSSOP Package
(Samsung 20-TSSOP-225)
99-06-15
18
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
Addendum(for 24-QFN package)
PIN CONFIGURATION(24-QFN, not to scale)
VDD1 VDD2 Vp2
N/C
1
Vp1
24
23
22
21
N/C
2
20
CPoIF
CPoRF
3
19
GND
(Digital)
GND
(Digital)
4
finRF
5
finRF
6
KB8821
KB8822
KB8823
Top View
18
finIF
17
finIF
16
GND
(Analog)
GND 7
(Analog)
15
LE
OSCin
8
14
DATA
N/C
9
13
N/C
10
11
12
GND foLD CLOCK
(Digital)
* N/C pins must be connected
to GND(to Analog GND if
possible).
24-QFN
24 PIN Quad Flat Non-leaded
(24-QFN) Package
1. pin #10 = pin #19(internally connected).
2. Do not tie up Vp and VDD
: Vp is the source of digital noises. The power
for analog part is supplied by VDD. If Vp and
VDD are tied together, noisy Vp corrupts the
power source for the analog part.
TEL-97-D003
99-06-15
19
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
PIN DESCRIPTION(24-QFN)
Pin No
( 20TSSOP)
Pin No
(24QFN)
Symbol
1
24
VDD1
2
3
1
2
3
Vp1
CPoRF
N/C
O
4
5
4
5
GND
finRF
I
6
6
finRF
I
7
8
7
8
GND
OSCin
I
9
9
10
GND
N/C
-
10
11
foLD
O
11
12
CLOCK
I
12
13
14
DATA
N/C
I
13
15
LE
I
14
16
GND
-
15
17
finIF
I
16
17
18
18
19
20
finIF
GND
CPoIF
I
O
19
21
22
Vp2
N/C
-
I/O
Description
-
Power supply voltage input for the RF PLL part. VDD1 must equal
VDD2. In order to reject supply noise, bypass capacitors must be
placed as close as possible to this pin and be connected directly to
the ground plane.
No connection.
Power supply voltage input for RF charge pump(≥ VDD1).
Internal RF charge pump output for connection to an external loop
filter whose filtered output drives an external VCO.
Ground for RF digital blocks.
RF prescaler input. The signal comes from the external VCO.
The complementary input of the RF prescaler. A bypass capacitor
must be placed as close as possible to this pin and be connected
directly to the ground plane. The bypass capacitor is optional with
some loss of sensitivity.
Ground for RF analog blocks.
Reference counter input. TCXO is connected via a coupling
capacitor.
No connection.
Ground for IF digital blocks.
Multiplexed output of the RF/IF programmable counters, the
reference counters, the lock detect signals and the shift registers.
The output level is CMOS level. (see fout Programmable Truth
Table)
CMOS clock input. Serial data for the various counters is transfered
into the 22-bit shift register on the rising edge of the clock signal.
No connection.
Binary serial data input. The MSB of CMOS input data is entered
first. The control bits are on the last two bits. CMOS input.
Load enable CMOS input. When LE becomes high, the data in the
shift register is loaded into one of the four latches(by the control
bits).
Ground for IF analog blocks.
The complementary input of the IF prescaler. A bypass capacitor
must be placed as close as possible to this pin and be connected
directly to the ground plane. The bypass capacitor is optional with
some loss of sensitivity.
IF prescaler input. The signal comes from the external VCO.
Ground for IF digital blocks.
Internal IF charge pump output for connection to an external loop
filter whose filtered output drives an external VCO.
No connection.
Power supply voltage input for IF charge pump( ≥ VDD2)
TEL-97-D003
99-06-15
20
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
20
23
VDD2
-
KB8821/22/23
Power supply voltage input for the IF PLL part. VDD1 must equal
VDD2. In order to reject supply noise, bypass capacitors must be
placed as close as possible to this pin and be connected directly to
the ground plane.
99-06-15
21