KM23V32005BG CMOS MASK ROM 32M-Bit (4Mx8 /2Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization 4,194,304x8(byte mode) 2,097,152x16(word mode) • Fast access time Random Access Time : 100ns(Max.) Page Access Time : 30ns(Max.) • 8 words / 16 bytes page access • Supply voltage : single +3.3V • Current consumption Operating : 60mA(Max.) Standby : 30µA(Max.) • Fully static operation • All inputs and outputs TTL compatible • Three state outputs • Package KM23V32005BG : 44-SOP-600 The KM23V32005BG is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 4,194,304x8 bit(byte mode) or as 2,097,152x16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 8 words(or 16 bytes) of data to read fast in the same page, CE and A3 ~ A20 should not be changed. This device operates with a 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V32005BG is packaged in a 44-SOP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A20 . . . . . . . . A3 A0~A2 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (2,097,152x16/ 4,194,304x8) Y BUFFERS AND DECODER SENSE AMP. DATA OUT BUFFERS . . . CE Q0/Q8 CONTROL LOGIC OE BHE Pin Name Pin Function A0 - A2 Page Address Inputs A3 - A20 Address Inputs Q0 - Q14 Data Outputs Q15 /A-1 Output 15(Word mode)/ LSB Address(Byte mode) BHE Word/Byte selection CE Chip Enable OE Output Enable VCC Power (3.3V) VSS Ground N.C No Connection Q7/Q15 N.C 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 34 A16 11 CE 12 VSS 13 SOP 33 BHE 32 VSS OE 14 31 Q15/A-1 Q0 15 30 Q7 Q8 16 29 Q14 Q1 17 Q9 18 28 Q6 Q2 19 26 Q5 Q10 20 25 Q12 27 Q13 Q3 21 24 Q4 Q11 22 23 VCC KM23V32005BG KM23V32005BG CMOS MASK ROM ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to V SS Temperature Under Bias Storage Temperature Symbol Rating Unit VIN -0.3 to +4.5 V TBIAS -10 to +85 °C TStg -55 to +150 °C NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should berestricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C) Symbol Min Typ Max Unit Supply Voltage Item VCC 3.0 3.3 3.6 V Supply Voltage VSS 0 0 0 V DC CHARACTERISTICS Parameter Symbol Operating Current Test Conditions CE=OE=VIL, all outputs open ICC Min Max Unit - 60 mA Standby Current(TTL) ISB1 CE=VIH, all outputs open 500 µA Standby Current(CMOS) ISB2 CE=VCC, all outputs open 30 µA Input Leakage Current ILI VIN=0 to VCC - 10 µA Output Leakage Current ILO VOUT=0 to VCC - 10 µA Input High Voltage, All Inputs VIH 2.0 VCC+0.3 V Input Low Voltage, All Inputs VIL -0.3 0.6 V Output High Voltage Level VOH IOH=-400µA 2.4 - V Output Low Voltage Level VOL IOL=2.1mA - 0.4 V NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to V CC+2.0V for periods <20ns. MODE SELECTION CE OE BHE Q15/A-1 Mode Data Power H X X X Standby High-Z Standby L H L L X X Operating High-Z Active H Output Operating Q0~Q15 : Dout Active L Input Operating Q0~Q7 : Dout Q8~Q14 : Hi-Z Active CAPACITANCE(TA=25°C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol Test Conditions Min Max Unit COUT VOUT=0V - 12 pF CIN VIN=0V - 12 pF NOTE : Capacitance is periodically sampled and not 100% tested. KM23V32005BG CMOS MASK ROM AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V±0.3V, unless otherwise noted.) TEST CONDITIONS Item Value Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10ns Input and Output timing Levels 1.5V Output Loads 1 TTL Gate and C L=100pF READ CYCLE Item Symbol KM23V32005BG-10 Min Max Min Max Min Max Chip Enable Access Time tACE 100 120 150 ns Address Access Time tAA 100 120 150 ns Page Address Access Time tPA 30 50 70 ns Output Enable Access Time tOE 30 50 70 ns Output or Chip Disable to Output High-Z tDF 20 20 30 ns Output Hold from Address Change tOH 0 150 Unit tRC 0 120 KM23V32005BG-15 Read Cycle Time NOTE : Page Address is determined as below. Word mode(BHE=VIH) ; A0 , A1 , A2 Byte mode(BHE=VIL) ; A -1, A0 , A1 , A2 100 KM23V32005BG-12 0 ns ns KM23V32005BG CMOS MASK ROM TIMING DIAGRAM READ ADD A0~A20 A-1(*1) ADD1 ADD2 tRC tDF(*3) tACE CE tOE tAA OE tOH DOUT D0~D7 D8~D15(*2) VALID DATA VALID DATA PAGE READ ≈ CE tDF(*3) ≈ ≈ OE ≈ ≈ ADD A3~A20 ADD A0,A1,A2 A -1(*1) 1 st tAA ≈ tPA VALID DATA VALID DATA VALID DATA VALID DATA ≈ DOUT D0~D7 D8~D15(*2) 3 rd ≈ 2 nd NOTES : *1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level. KM23V32005BG CMOS MASK ROM PACKAGE DIMENSIONS (Unit : mm/inch) 44-SOP-600 0~8° #23 15.24 0.600 #44 16.04±0.30 12.60±0.20 0.631±0.012 0.496±0.008 #1 #22 +0.10 -0.05 0.008+0.004 -0.002 0.20 2.80±0.20 0.110±0.008 3.10 0.122 MAX 28.95 MAX 1.140 28.50±0.20 1.122±0.008 0.10 MAX 0.004 MAX ( 0.915 ) 0.036 +0.100 -0.050 +0.004 0.016 -0.002 0.40 1.27 0.050 0.05 MIN 0.002 0.80±0.20 0.031±0.008