SAMSUNG KM4132G271B

KM4132G271B
CMOS SGRAM
8Mbit SGRAM
128K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 2.4
May 1998
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Revision History
Revision 2.4 (May 1998)
• Added KM4132G271B-7 product(143MHz @ CL =3).
Revision 2.3 (March 1998)
• Added Reverse Type Package in ODERING INFORMATION and PIN CONFIGURATION.
• Removed KM4132G271B-H/12 product(-H : 100MHz @ CL =2, -12 : 83MHz @ CL=3).
• Changed the Current values of ICC1, ICC3N, ICC4, ICC5, ICC6, ICC7 in DC CHARACTERISTICS.
• Changed tSAC from 6 to 6.5 @ 125MHz, tSS from 2 to 2.5 @ 125MHz in AC PARAMETER .
• Delete a page including FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
Revision 2.1 (November 1997)
• Changed the Height of TQFP Package from 1.4mmMAX to 1.2mmMax in
PACKAGE DIMENSIONS.
Revision 2.0 (October 1997)
• Added -H binning(100MHz @ CL =2 ).
• Changed some values in DC CHARACTERISTICS.
• Changed some values in AC PARAMETER (tSAC / tOH / tSHZ / tRP / tRC / tBPL / tBWC etc.).
• Removed a AC Parameter, tBAL(Block write data-in to Active command period) in
AC PARAMETER .
• Changed some values in FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE.
• Added the Package Type description(PQFP, TQFP) in
PACKAGE DIMENSIONS.
-2-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
128K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The KM4132G271B is 8,388,608 bits synchronous high data
rate Dynamic RAM organized as 2 x 131,072 words by 32 bits,
fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.
•
•
•
•
•
•
•
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual bank / Pulse RAS
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
16ms refresh period (1K cycle)
100 Pin PQFP, TQFP (14 x 20 mm)
Reverse Type Package offers the best signal routing
ORDERING INFORMATION
Part NO.
Graphics Features
• SMRS cycle.
-. Load mask register
-. Load color register
• Write Per Bit(Old Mask)
• Block Write(8 Columns)
Max Freq.
KM4132G271BQ(R)-7
143MHz
KM4132G271BQ(R)-8
125MHz
KM4132G271BQ(R)-10
100MHz
KM4132G271BTQ(R)-7
143MHz
KM4132G271BTQ(R)-8
125MHz
KM4132G271BTQ(R)-10
100MHz
Interface
Package
LVTTL
100 PQFP
LVTTL
100 TQFP
* ~G271BQR# / ~G271BTQR# : Reverse Type Package
MASK
REGISTER
DQMi
CLK
•
CKE
COLUMN
MASK
MASK
BLOCK
WRITE
CONTROL
LOGIC
WRITE
CONTROL
MUX
COLOR
REGISTER
LOGIC
INPUT BUFFER
FUNCTIONAL BLOCK DIAGRAM
DQMi
DQi
(i=0~31)
SENSE
AMPLIFIER
COLUMN
DECORDER
128Kx32
CELL
ARRAY
DSF
128Kx32
CELL
ARRAY
OUTPUT BUFFER
WE
•
LATENCY &
BURST LENGTH
CAS
PROGRAMING
REGISTER
RAS
TIMING REGISTER
CS
ROW DECORDER
BANK SELECTION
DQMi
•
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK ADDRESS(A 0 ~A 9)
-3-
Rev. 2.4 (May 1998)
DQ2
V SSQ
DQ1
DQ0
VDD
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V SS
DQ31
DQ30
V SSQ
DQ29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ3
V DDQ
DQ4
DQ5
V SSQ
DQ6
DQ7
V DDQ
DQ16
DQ17
V SSQ
DQ18
DQ19
V DDQ
V DD
V SS
DQ20
DQ21
V SSQ
DQ22
DQ23
V DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A 9 )
N.C
DQ3
V DDQ
DQ4
DQ5
V SSQ
DQ6
DQ7
V DDQ
DQ16
DQ17
V SSQ
DQ18
DQ19
V DDQ
V DD
VSS
DQ20
DQ21
V SSQ
DQ22
DQ23
V DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A9 )
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ29
V SSQ
DQ30
DQ31
V SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V DD
DQ0
DQ1
V SSQ
DQ2
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
V DDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
V DDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
V DDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A8
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C
DQM3
DQM1
CLK
CKE
DSF
N.C
A8
KM4132G271B
CMOS SGRAM
PIN CONFIGURATION (TOP VIEW)
Forward Type
100 Pin QFP
Forward Type
20 x 14 §±
0.65§® pin Pitch
Reverse Type
100 Pin QFP
Reverse Type
20 x 14 §±
0.65§® pin Pitch
-4-
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
VSS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
VDD
A3
A2
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A0
A1
A2
A3
V DD
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V SS
A4
A5
A6
A7
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
PIN CONFIGURATION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock +tSS prior to new command.
Disable input buffers for power down in standby.
A 0 ~ A8
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA8 , Column address : CA0 ~ CA7
A 9 (BA)
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
DQMi
Data Input/Output Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
DQi
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
Enables write per bit, block write and special mode register set.
V DD /VSS
Power Supply /Ground
Power Supply : +3.3V±0.3V/Ground
V DDQ /VSSQ
Data Output Power /Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
N.C
No Connection
-5-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
ABSOLUTE MAXIMUM RATINGS (Voltage referenced to VSS )
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V IN , VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
V DD , VDDQ
-1.0 ~ 4.6
V
T STG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
Note
VDD , VDDQ
3.0
3.3
3.6
V
Input high voltage
V IH
2.0
3.0
V DD +0.3
V
Input low voltage
V IL
-0.3
0
0.8
V
Note 1
Output high voltage
V OH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
IIL
-5
-
5
uA
Note 2
Output leakage current
IOL
-5
-
5
uA
Note 3
Output Loading Condition
see figure 1
Note : 1. VIL (min) = -1.5V AC(pulse width ≤ 5ns).
2. Any input 0V ≤ V IN ≤ V DD + 0.3V, all other pins are not under test = 0V.
3. Dout is disabled, 0V ≤ V OUT ≤ VDD.
CAPACITANCE
(VDD /VDDQ = 3.3V, TA = 25°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A9 )
CIN1
-
4
pF
Input capacitance
(CLK, CKE, CS, RAS, CAS, WE, DSF & DQM)
CIN2
-
4
pF
Data input/output capacitance (DQ0 ~ DQ31 )
C OUT
-
5
pF
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
CDC1
0.1 + 0.01
uF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
uF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
-6-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C VIH(min) /VIL(max) =2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
CAS
Latency
Speed
-7
-8
-10
180
160
150
ICC1
Burst Length =1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL = 0 mA
ICC2 P
CKE ≤ V IL (max), tCC = 15ns
2
ICC2 PS
CKE ≤ V IL (max), CLK ≤ V IL (max), tCC = ∞
2
ICC2 N
CKE ≥ V IH (min), CS ≥ VIH (min), tCC = 15ns
Input signals are changed one time during 30ns
35
ICC2 NS
CKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞
Input signals are stable
15
Active Standby Current
in power-down mode
ICC3 P
CKE ≤ V IL (max), tCC = 15ns
3
ICC3 PS
CKE ≤ V IL (max), CLK ≤ V IL (max), tCC = ∞
3
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3 N
CKE ≥ V IH (min), CS ≥ VIH (min), tCC = 15ns
Input signals are changed one time during 30ns
50
ICC3 NS
CKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞
Input signals are stable
Operating Current
(Burst Mode)
ICC4
IOL = 0 mA, Page Burst
All bank Activated, tCCD = tCCD (min)
Refresh Current
ICC5
tRC ≥ tRC (min)
Self Refresh Current
ICC6
CKE ≤ 0.2V
Operating Current
(One Bank Block Write)
ICC7
tCC ≥ tCC (min), IOL =0mA, tBWC (min)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Unit
Note
mA
1
mA
mA
mA
mA
25
3
300
280
210
2
180
180
160
90
90
90
2
210
mA
1
mA
2
mA
190
150
mA
Note : 1. Measured with outputs open. Addresses are changed only one time during tcc(min).
2. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
-7-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
AC OPERATING TEST CONDITIONS
(VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Value
AC input levels
V ih /Vil = 2.4V / 0.4V
Input timing measurement reference level
1.4V
tR/t F=1ns/ 1ns
Input rise and fall time(See note 3)
Output timing measurement reference level
1.4V
Output load condition
See Fig. 2
V tt = 1.4V
3.3V
1200Ω
•
Output
50Ω
V OH (DC) = 2.4V, IOH = -2mA
V OL (DC) = 0.4V, IOL = 2mA
•
Output
Z0=50Ω
•
30pF
870Ω
30pF
•
(Fig. 1) DC Output Load Circuit
AC CHARACTERISTICS
(Fig. 2) AC Output Load Circuit
(AC operating conditions unless otherwise noted)
Parameter
-7
Symbol
Min
CLK cycle time
CAS Latency=3
CAS Latency=2
CLK to valid
output delay
CAS Latency=3
7
tCC
-8
Max
1000
12
tSAC
CAS Latency=2
Min
8
-10
Max
1000
12
Min
10
Unit
Note
ns
1
ns
1, 2
Max
1000
13
-
6
-
6.5
-
7
-
8
-
8
-
9
Output data hold time
tOH
2.5
2.5
2.5
ns
2
CLK high pulse width
tCH
2.5
3
3.5
ns
3
CLK low pulse width
tCL
2.5
3
3.5
ns
3
Input setup time
tSS
2
2.5
2.5
ns
3
Input hold time
tSH
1
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
CAS latency=2
-
6
-
6.5
-
7
-
8
-
8
-
9
ns
* All AC parameters are measured from half to half.
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
-8-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-7
-8
-10
Unit
Note
Row active to row active delay
tRRD(min)
14
16
20
ns
1
RAS to CAS delay
tRCD(min)
16
16
20
ns
1
Row precharge time
tRP(min)
21
20
20
ns
1
tRAS(min)
49
48
50
ns
1
Row active time
tRAS(max)
Row cycle time
tRC(min)
Last data in to new col. address delay
tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
100
ns
1
1
CLK
2
1
CLK
2
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Block write data-in to PRE command delay
tBPL(min)
1
CLK
Block write cycle time
tBWC(min)
1
CLK
1, 3
CLK
4
Number of valid output data
70
70
us
CAS latency=3
2
CAS latency=2
1
70
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
-9-
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
H
CS
X
RAS CAS
L
L
L
WE
L
Special Mode Register Set
Refresh
Auto Refresh
H
Bank Active
& Row Addr.
Exit
Write Per Bit Disable
X
L
H
OP CODE
L
L
L
H
L
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
Block Write &
Column Addr.
H
X
3
H
X
L
H
H
H
H
X
X
X
L
L
H
H
X
X
Entry
X
L
X
V
Row Address
L
H
L
H
L
X
L
H
L
L
L
X
V
L
Column
Address
X
V
L
Column
Address
H
X
L
H
L
L
H
X
V
L
Column
Address
H
H
X
L
H
H
L
L
X
H
X
L
L
H
L
L
X
H
L
L
H
Entry
H
L
Precharge Power Down Mode
L
DQM
H
No Operation Command
H
H
L
H
H
H
H
X
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
V
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
V
L
X
H
4
4, 6
4, 5
4,5,6,9
4, 5
4,5,6,9
7
X
X
X
X
X
X
X
X
X
X
4, 5
4,5,9
H
Exit
Exit
3
X
3
Both Banks
Clock Suspend or
Active Power Down
1, 2
3
X
Auto Precharge Enable
Bank Selection
Note
1,2,7
H
H
Burst Stop
A7~ A0
L
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
Precharge
H
Write Per Bit Enable
Auto Precharge Disable
L
A8
H
Entry
Self
Refresh
DSF DQM A9
X
X
V
X
X
X
8
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code
A0 ~ A9 : Program keys. (@MRS)
A5 , A6 : LMR or LCR select. (@SMRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ′s are idle.
A new command can be issued at the next clock of MRS/SMRS.
- 10
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both precharge state.
4. A9 : Bank select address.
If "Low" at read, (block) write, Row active and precharge, bank A is selected.
If "High" at read, (block) write, Row active and precharge, bank B is selected.
If A8 is "High" at Row precharge, A9 is ignored and both banks are selected.
5. It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit =I/O mask
(Block) Write with write per bit mode=Masked(Block) Write
6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.
Another bank read/(block) write command can be issued at t RP after the end of burst.
7. Burst stop command is valid only at full page burst length.
8. DQM sampled at positive going edge of a CLK.
masks the data-in at the very CLK(Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
9. Graphic features added to SDRAM′s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 8M SDRAM with 32 DQ′s.
SGRAM vs SDRAM
Function
DSF
SGRAM
Function
MRS
L
MRS
Bank Active
Write
H
L
H
L
H
SMRS
Bank Active
with
Write per bit
Disable
Bank Active
with
Write per bit
Enable
Normal
Write
Block
Write
If DSF is low, SGRAM functionality is identical to SDRAM functionality .
SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory
- 11
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A9
A8
W.B.L
A7
A6
A5
TM
A4
CAS Latency
A3
A2
BT
A1
A0
Burst Length
(Note 1)
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
Reserved
0
1
0
0
1
-
1
Interleave
0
0
1
2
Reserved
1
0
Vendor
Use
Only
0
1
0
2
0
1
0
4
4
1
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
1
A9
(Note 2)
Special Mode Register Programmed with SMRS
Address
Function
A9
A8
A7
X
A6
A5
LC
LM
Load Color
A4
A3
A2
A1
A0
X
Load Mask
A6
Function
A5
Function
0
Disable
0
Disable
1
Enable
1
Enable
(Note 3)
POWER UP SEQUENCE
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. The full column burst(256bit) is available only at Sequential mode of burst type.
3. If LC and LM both high(1), data of mask and color register will be unknown.
- 12
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
PIXEL to DQ MAPPING(at BLOCK WRITE)
Column address
3 Byte
2 Byte
1 Byte
0 Byte
A2
A1
A0
I/O31 - I/O24
I/O23 - I/O16
I/O15 - I/O8
I/O7 - I/O0
0
0
0
DQ 24
DQ16
DQ8
DQ 0
0
0
1
DQ 25
DQ17
DQ9
DQ 1
0
1
0
DQ 26
DQ18
DQ 10
DQ 2
0
1
1
DQ 27
DQ19
DQ 11
DQ 3
1
0
0
DQ 28
DQ20
DQ 12
DQ 4
1
0
1
DQ 29
DQ21
DQ 13
DQ 5
1
1
0
DQ 30
DQ22
DQ 14
DQ 6
1
1
1
DQ 31
DQ23
DQ 15
DQ 7
- 13
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
V IL and VIH . During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock for proper
functionality and ICC specifications.
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to pull
them high and other pins are NOP condition at the inputs
before or along with VDD (and VDDQ ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause of
200 microseconds is required with inputs in NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the CAS
latency, burst length and burst type as the default value of
mode register is undefined.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the outputs will be in high impedance state. The high impedance of
outputs is not guaranteed in any other power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SGRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When both banks
are in the idle state and CKE goes low synchronously with clock,
the SGRAM enters the power down mode from the next clock
cycle. The SGRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "tSS + 1CLOCK " before the high going
edge of the clock, then the SGRAM becomes active from the
same clock edge accepting all the input commands.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
BANK SELECT (A9)
operating modes of SGRAM. It programs the CAS latency,
This SGRAM is organized as two independent banks of 131,072
words x 32 bits memory arrays. The A9 inputs is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. When A9 is asserted low, bank A is selected.
When A9 is asserted high, bank B is selected. The bank select
A 9 is latched at bank activate, read, write mode register set and
precharge operations.
addressing mode, burst length, test mode and various vendor
specific options to make SGRAM useful for variety of different
applications. The default value of the mode register is not
defined, therefore the mode register must be written after power
up to operate the SGRAM. The mode register is written by
asserting low on CS, RAS, CAS, WE and DSF (The SGRAM
should be in active mode with CKE already high prior to writing
ADDRESS INPUT (A0 ~ A8)
the mode register). The state of address pins A0 ~ A 8 and A9 in
The 17 address bits required to decode the 131,072 word locations are multiplexed into 9 address input pins(A0~A 8). The 9 bit
row address is latched along with RAS and A9 during bank activate command. The 8 bit column address is latched along with
CAS, WE and A9 during read or write command.
the same cycle as CS, RAS, CAS, WE and DSF going low is the
data written in the mode register. One clock cycle is required to
complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle
requirements during operation as long as both banks are in the
NOP and DEVICE DESELECT
idle state. The mode register is divided into various fields
When RAS, CAS and WE are high, the SGRAM performs no
depending on functionality. The burst length field uses A0 ~ A2 ,
operation (NOP). NOP does not initiate any new operation, but
burst type uses A3 , addressing mode uses A4 ~ A 6 , A7 ~ A 8 are
is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc.
used for vendor specific options or test mode. And the write
The device deselect is also a NOP and is entered by asserting
for normal SGRAM operation. Refer to table for specific codes
CS high. CS high disables the command decoder so that RAS,
CAS, WE, DSF and all the address inputs are ignored.
for various burst length, addressing modes and CAS latencies.
burst length is programmed using A9. A7 ~ A8 must be set to low
- 14
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
DEVICE OPERATIONS
BANK ACTIVATE
cycles in adjacent addresses depending on burst length and
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank addresses, a row access is initiated. The read or write
operation can occur after a time delay of tRCD (min) from the time
of bank activation. tRCD (min) is an internal timing parameter of
SGRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD (min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SGRAM has two
internal banks on the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of both banks immediately. Also the noise generated during
sensing of each bank of SGRAM is high requiring some time for
power supplies to recover before the other bank can be sensed
reliably. tRRD (min) specifies the minimum time required between
activating different banks. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be
active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS (min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS (max). The number of cycles for both tRAS (min) and
tRAS (max) can be calculated similar to tRCD specification.
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing may not
have been completed yet. The writing can not complete to burst
length. The burst write can be terminated by issuing a burst
read and DQM for blocking data inputs or burst write in the same
or the other active bank. The burst stop command is valid only at
full page burst length where the writing continues at the end of
burst and the burst is wrapped around. The write burst can also
be terminated by using DQM for blocking data and precharging
the bank " tRDL " after the last data input to be written into the
active row. See DQM OPERATION also.
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock,
therefore the masking occurs for a complete cycle. The DQM
signal is important during burst interrupts of write with read or
precharge in the SGRAM. Due to asynchronous nature of the
internal write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is not required.
DQM is also used for device selection, byte selection and bus
control in a memory system. DQM0 controls DQ0 to DQ7,
DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. DQM masks the DQ′s by a byte
regardless that the corresponding DQ′s are in a state of WPB
masking or Pixel masking. Please refer to DQM timing diagram
also.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD (min) before the burst read command is issued. The first output appears CAS latency number of
clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid only at full page burst length
where the output does not go into high impedance at the end of
burst and the burst is wrapped around..
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A8 with valid A9 of the bank
to be precharged. The precharge command can be asserted
anytime after tRAS (min) is satisfied from the bank activate command in the desired bank. "tRP " is defined as the minimum time
required to precharge a bank. The minimum number of clock
cycles required to complete row precharge is calculated by
dividing "tRP " with clock cycle time and rounding up to the next
higher integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can
be active is specified by tRAS (max). Therefore, each bank has to
be precharged within tRAS (max) from the bank activate command. At the end of precharge, the bank enters the idle state
and is ready to be activated again.
BURST WRITE
The burst write command is similar to burst read command, and
is used to write data into the SGRAM on consecutive clock
- 15
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
DEVICE OPERATIONS (Continued)
Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc. is possible only when both banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SGRAM internally generates the timing to satisfy
tRAS (min) and "tRP " for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A8 . If burst
read or burst write command is issued with low on A8 , the bank
is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with
high on A8 after both banks have satisfied tRAS (min) require-
SELF REFRESH
The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SGRAM. In self refresh
mode, the SGRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP′s
for a minimum time of "tRC " before the SGRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to use burst
1024 auto refresh cycles immediately after exiting self refresh.
DEFINE SPECIAL FUNCTION(DSF)
ment, performs precharge on both banks. At the end of tRP after
performing precharge all, both banks are in idle state.
AUTO REFRESH
The storage cells of SGRAM need to be refreshed every 16ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,RAS
The DSF controls the graphic applications of SGRAM. If DSF is
tied to low, SGRAM functions as 128K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate
DSF command. All the graphic function modes can be entered
only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands. SDRAM functions
such as RAS Active, Write, and WCBR change to SGRAM functions such as RAS Active with WPB, Block Write and SWCBR
respectively. See the section below for the graphic functions that
DSF controls.
and CAS with high on CKE and WE. The auto refresh command
can only be asserted with both banks being in idle state and the
device is not in power down mode (CKE is high in the previous
cycle). The time required to complete the auto refresh operation
is specified by "tRC (min)". The minimum number of clock cycles
required can be calculated by driving "tRC " with clock cycle time
and them rounding up to the next higher integer. The auto
refresh command must be followed by NOP′s until the auto
refresh operation i s completed. Both banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 1024 auto refresh cycles once in
16ms.
- 16
SPECIAL MODE REGISTER SET(SMRS)
There are two kinds of special mode registers in SGRAM.One is
color register and the other is mask register. Those usage will be
explained in the "WRITE PER BIT" and "BLOCK WRITE" sections. When A5 and DSF goes high in the same cycle as CS,
RAS, CAS and WE going low, Load Mask Register(LMR) process is executed and the mask registers are filled with the
masks for associated DQ′s through DQ pins. And when A6 and
DSF goes high in the same cycle as CS, RAS, CAS and WE
going low, Load Color Register(LCR) process is executed and
the color register is filled with color data for associated DQ′s
through the DQ pins. If both A5 and A6 are high at SMRS, data
of mask and color cycle are required to complete the write in the
mask register and the color register at LMR and LCR respectively. A new command can be issued in the next clock of LMR
or LCR. SMRS, compared with MRS, can be issued at the active
state under the condition that DQ′s are idle. As in write operation, SMRS accepts the data needed through DQ pins. Therefore bus contention must be avoided. The more detailed
materials can be obtained by referring corresponding timing diagram.
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
DEVICE OPERATIONS (Continued)
Timing Diagram to lllustrate tBWC
WRITE PER BIT
Write per bit(i.e. I/O mask mode) for SGRAM is a function that
selectively masks bits of data being written to the devices. The
mask is stored in an internal register and applied to each bit of
data written when the mask is enabled. Bank active command
with DSF=High enables write per bit for associated bank. Bank
active command with DSF=Low disables write per bit for the
associated bank. The mask used for write per bit operations is
stored in the mask register accessed by SWCBR(Special Mode
Register Set Command). When a mask bit=1, the associated
data bit is written when a write command is executed and write
per bit has been enabled for the bank being written. When a
mask bit=0, the associated data bit is unaltered when a write
command is executed and the write per bit has been enabled for
the bank being written. No additional timing conditions are
required for write per bit operations. Write per bit writes can be
either single write, burst writes or block writes. DQM masking is
the same for write per bit and non-WPB write.
0
1
2
CLOCK
CKE
HIGH
CS
RAS
CAS
WE
DSF
1 CLK BW
BLOCK WRITE
Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during a single access cycle. During block write the data to be written comes
from an internal "color" register and DQ I/O pins are used for
independent column selection. The block of column to be written
is aligned on 8 column boundaries and is defined by the column
address with the 3 LSB′s ignored. Write command with DSF=1
enables block write for the associated bank. A write command
with DSF=0 enables normal write for the associated bank. The
block width is 8 column where column="n" bits for by "n" part.
The color register is the same width as the data port of the
chip.It is written via a SWCBR where data present on the DQ pin
is to be coupled into the internal color register. The color register
provides the data masked by the DQ column select, WPB
mask(If enabled), and DQM byte mask. Column data masking(Pixel masking) is provided on an individual column basis for
each byte of data. The column mask is driven on the DQ pins
during a block write command. The DQ column mask function is
segmented on a per bit basis(i.e. DQ[0:7] provides the column
mask for data bits[0:7], DQ[8:15] provides the column mask for
data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data bits [8:15], etc). Block writes are
always non-burst, independent of the burst length that has been
programmed into the mode register. Back to back block writes
are allowed provided that the specified block write cycle
time(t BWC ) is satisfied. If write per bit was enabled by the bank
active command with DSF=1, then write per bit masking of the
color register data is enabled.
If write per bit was disabled by a bank active command with
DSF=0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking
during block write exactly the same as it does during normal
write operations, except that the control is extended to the consecutive 8 columns of the block write.
- 17
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
SUMMARY OF 1M Byte SGRAM BASIC FEATURES AND BENEFITS
Features
Interface
Bank
Page Depth / 1 Row
Total Page Depth
Burst Length(Read)
128K x 32 x 2 SGRAM
Synchronous
2 ea
High speed vertical and horizontal drawing.
1024 bytes
High speed vertical and horizontal drawing.
1, 2, 4, 8 Full Page
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
1, 2, 4, 8 Full Page
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
BRSW
CAS Latency
Block Write
Color Register
Mask Register
Sequential & Interleave
2, 3
8 Columns
Switch to burst length of 1 at write without MRS.
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.
1 ea.
A and B bank share.
1 ea.
Write-per-bit capability(bit plane masking). A and B banks share.
DQM0-3
Mask function
Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.
256 bit
Burst Length(Write)
Burst Type
Benefits
Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Write per bit
Pixel Mask at Block Write
Byte masking(pixel masking for 8bpp system) for data-out/in
Each bit of the mask register directly controls a corresponding bit plane.
Byte masking(pixel masking for 8bpp system) for color by DQi
- 18
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
2) Clock Suspended During Read (BL=4)
1) Clock Suspended During Write (BL=4)
CLK
CMD
WR
RD
CKE
Masked by CKE
Masked by CKE
Internal
CLK
DQ(CL2)
D0
D1
D2
D3
DQ(CL3)
D0
D1
D2
D3
Q0
D
Q01
Q2
Q3
Q0
Q1
Q2
Not Written
Q3
Suspended Dout
Note : CKE to CLK disable/enable=1 clock
2. DQM Operation
2) Read Mask (BL=4)
1) Write Mask (BL=4)
CLK
CMD
WR
RD
DQMi
Note 1
Masked by DQM
DQ(CL2)
D0
DQ(CL3)
D0
D1
Q0
D3
D1
Masked by DQM
Hi-Z
Hi-Z
D3
DQM to Data-in Mask = 0CLK
3) DQM with Clock Suspended (Full Page Read)
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2CLK
Note 2
CLK
CMD
RD
CKE
DQM
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Hi-Z
Q2
Hi-Z
Q1
Q4
Q3
Hi-Z
Hi-Z
Q6
Q7
Q8
Q5
Q6
Q7
*Note : 1. There are 4 DQMi(i=0~3).
Each DQMi masks 8 DQi ′ s.(1 Byte, 1 Pixel for 8 bpp)
2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE " L".
- 19
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4) Note 1
CLK
CMD
RD
RD
ADD
A
B
DQ(CL2)
QA 0
DQ(CL3)
QB 0
QB 1
QB2
QB 3
QA 0
QB 0
QB1
QB 2
QB 3
tCCD
Note 2
2) Write interrupted by(Block) Write (BL=2)
3) Write interrupted by Read (BL=2)
CLK
CMD
WR
WR
tCCD
ADD
WR
tCCD
Note 2
A
B
DA 0
DB 0
WR
BW
tCCD
Note 2
C
D
DC 0
Pixel
RD
A
Note 2
B
Note 4
DQ
DB 1
tCDL
tCDL
Note 3
Note 3
DQ(CL2)
DA 0
DQ(CL3)
DA 0
QB 0
QB 1
QB 0
QB 1
tCDL
Note 3
4) Block Write to Block Write
CLK
CMD
BW
BW
ADD
A
B
Note 4
DQ
Pixel Pixel
tBWC
Note 5
*Note : 1. By " Interrupt ", It is possible to stop burst read/write by external command before the end of burst.
By "CAS Interrupt" , to stop burst read/write by CAS access ; read, write and block write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
4. Pixel :Pixel mask.
5. tBWC : Block write minimum cycle time.
- 20
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
RD
WR
DQM
DQ
ii) CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii) CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv) CMD
D0
RD
WR
DQM
Q0
DQ
Hi-Z
Note 1
D0
D3
(2) CL=3, BL=4
CLK
i) CMD
RD
WR
DQM
DQ
ii) CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
DQ
iii) CMD
D0
RD
WR
DQM
DQ
iv) CMD
D0
RD
WR
DQM
Hi-Z
DQ
v) CMD
D0
RD
WR
DQM
DQ
Q0
Hi-Z
Note 2
D0
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
- 21
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMD
WR
PRE
Note 1
DQM
DQ
D0
D1
D2
D3
Masked by DQM
*Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
DQ
D0
CMD
PRE
D1
D2
BW
DQ
D3
PRE
Pixel
tRDL
tBPL
Note 1
Note 1
3) Read (BL=4)
CLK
CMD
PRE
RD
DQ(CL2)
Q0
DQ(CL3)
Note 2
Q1
Q2
Q3
Q0
Q1
Q2
1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
DQ
D0
CMD
D1
D2
DQ
(CL 2, 3)
D3
BW
Pixel
Note 3
Auto Precharge Starts
3) Read (BL=4)
tBPL
tRP
Note 3
Auto Precharge Starts
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Note 3
Auto Precharge Starts
*Note : 1. t BPL : Block write data-in to PRE command delay
2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.
3. The row active command of the precharge bank can be issued after t RP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
- 22
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4)
2) Write Burst Stop (Full Page Only)
CLK
CLK
CMD
WR
PRE
CMD
WR
DQ
D0
STOP
DQM
DQ
D0
D1
D2
tRDL
D3
D2
tBDL
Note 1
3) Read Interrupted by Precharge (BL=4)
4) Read Burst Stop (Full Page Only)
CLK
CMD
D1
CLK
RD
CMD
PRE
RD
STOP
Note 3
Note 3
1
DQ(CL2)
Q0
DQ(CL3)
DQ(CL2)
Q1
Q0
Q1
2
Q0
Q1
1
2
DQ(CL3)
Q0
Q1
9. MRS & SMRS
1) Mode Register Set
2) Special Mode Register Set
CLK
CLK
Note 4
CMD
PRE
MRS ACT
tRP
CMD
1CLK
SMRS ACT SMRS SMRS BW
1CLK
1CLK
1CLK
1CLK
*Note : 1. t RDL : 1 CLK, Last Data in to Row Precharge.
2. t BDL : 1 CLK, Last Data in to Burst Stop Delay.
3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at all bank precharge state.
- 23
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CLK
CKE
Internal
CLK
tSS
CKE
tSS
Internal
CLK
Note 1
CMD
Note 2
CMD
RD
NOP ACT
11. Auto Refresh & Self Refresh
1) Auto Refresh Note 3
CLK
¡ó
Note 4
CMD
Note 5
PRE
AR
CMD
¡ó
CKE
¡ó
¡ó
tRP
tRC
2) Self Refresh Note 6
¡ó
CLK
¡ó
Note 4
CMD
PRE
SR
CMD
¡ó
CKE
¡ó
¡ó
¡ó
tRP
tRC
*Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don ′t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (1K cycles) is recommended.
- 24
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
12. About Burst Type Control
Sequential Counting
At MRS A 3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page wrap around.
Interleave Counting
At MRS A 3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Basic
MODE
PseudoDecrement Sequential
Counting
PseudoMODE
PseudoBinary Counting
Random
MODE
Random column Access
tCCD = 1 CLK
At MRS A 3 = "1".(See to Interleave Counting Mode)
Starting Address LSB 3 bits A 0-2 should be "000" or "111".@BL=8.
-- if LSB="000" : Increment Counting.
-- if LSB="111" : Decrement Counting.
For Example,(Assume Addresses except LSB 3 bits are all 0, BL=8)
-- @ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7
-- @ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at Interleave Counting mode,
by confining starting address to some values, Pseudo-Decrement Counting Mode can be
realized. See the BURST SEQUENCE TABLE carefully.
At MRS A 3 = "0".(See to Sequential Counting Mode)
A 0-2 = "111".(See to Full Page Mode)
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized.
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3(BL=8)
-- @ Pseudo-Binary Counting,
Accessed Column in order 3-4-5-6-7-8-9-10(Burst Stop command)
Note. The next column address of 256 is 0.
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A 2,1,0 = "000".
At auto precharge, t RAS should not be violated.
2
At MRS A 2,1,0 = "001".
At auto precharge, t RAS should not be violated.
4
At MRS A 2,1,0 = "010".
8
At MRS A 2,1,0 = "011".
Full Page
BRSW
Special
MODE
Block Write
Random
MODE
Burst Stop
RAS Interrupt
(Interrupted by Precharge)
Interrupt
MODE
CAS Interrupt
At MRS A 2,1,0 = "111".
Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.
At MRS A 9 = "1".
Read burst =1, 2, 4, 8, full page/write Burst =1
At auto precharge of write, t RAS should not be violated.
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.
tBWC should not be violated.
At auto precharge, t RAS should not be violated.
tBDL = 1, Valid DQ after burst stop is 1, 2 for CL=2, 3 respectively
Using burst stop command, it is possible only at full page burst length.
Before the end of burst, Row precharge command of the same bank
stops read/write burst with Row precharge.
t RDL = 1 with DQM, valid DQ after burst stop is 1, 2 for CL= 2, 3 respectively
During read/write burst with auto precharge, RAS interrupt cannot be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
During read/write burst with auto precharge, CAS interrupt can not be issued.
- 25
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
14. Mask Functions
1) Normal Write
I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
If bit plane 0, 3, 7, 9, 15, 22, 24, and 31 keep the original value.
i) STEP
¨ç SMRS(LMR) :Load mask[31-0]="0111, 1110, 1011, 1111, 0111, 1101, 0111, 0110"
¨è Row Active with DSF "H" :Write Per Bit Mode Enable
¨é Perform Normal Write.
i) ILLUSTRATION
I/O(=DQ)
31
External Data-in
24
11111111
23
16
11111111
15
8
00000000
7
0
00000000
DQMi
DQM 3=0
DQM 2=0
DQM 1 =0
DQM 0 =1
Mask Register
01111110
10111111
01111101
01110110
Before Write
00000000
00000000
11111111
11111111
After Write
01111110
10111111
10000010
11111111
Note 1
2) Block Write
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
If Pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color.
Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011"
i) STEP
¨ç SMRS(LCR) :Load color(for 8bpp, through x32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011, 1110, 0001, 0000, 1111, 1010, 0011"
¨è Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable
¨é Block write with DQ[31-0] = "0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110"
i) ILLUSTRATION
I/O(=DQ)
31
DQMi
Color Register
Before
Block
Write
&
DQ
(Pixel
data)
After
Block
Write
24
DQM 3 =0
23
16
15
8
DQM 2 =0
DQM 1 =0
7
0
DQM0 =1
Color3=Blue
Color2=Green
Color1=Yellow
Color0=Red
000
White DQ 24 =H
White DQ 16 =H
White DQ 8=H
White DQ 0 =L
001
White DQ 25 =H
White DQ 17 =H
White DQ 9 =L
White DQ 1 =H
010
White DQ 26 =H
White DQ 18 =L
White DQ 10 =H
White DQ 2 =H
011
White DQ 27 =L
White DQ 19 =H
White DQ 11 =H
White DQ 3 =H
100
White DQ 28 =H
White DQ 20 =H
White DQ 12 =H
White DQ 4 =L
101
White DQ 29 =H
White DQ 21 =H
White DQ 13 =L
White DQ 5 =H
110
White DQ 30 =H
White DQ 22 =L
White DQ 14 =H
White DQ 6 =H
111
White DQ 31 =L
White DQ 23 =H
White DQ 15 =H
White DQ 7 =H
000
Blue
Green
Yellow
White
001
Blue
Green
White
White
010
Blue
White
Yellow
White
011
White
Green
Yellow
White
100
Blue
Green
Yellow
White
101
Blue
Green
White
White
110
Blue
White
Yellow
White
111
White
Green
Yellow
White
Note 2
*Note :1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A 2-0 (000-111).
At block write, instead of ignored address A 2-0 , DQ0-31 control each pixel.
- 26
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
(Continued)
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.
By Pixel Data issued through DQ pin, the selected pixels keep the original data.
See PIXEL TO DQ MAPPING TABLE.
Assume 8bpp,
White = "0000,0000", Red="1010,0011", Green ="1110,0001", Yellow ="0000,1111", Blue ="1100,0011"
i) STEP
¨ç SMRS(LCR) : Load color(for 8bpp, through x 32 DQ color0-3 are loaded into color registers)
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)
= "1100,0011,1110,0001,0000,1111,1010,0011"
¨è SMRS(LMR ): Load mask. Mask[31-0] ="1111,1111,1101,1101, 0100,0010,0111,0110"
--> Byte 3 : No I/O Masking ; Byte 2 : I/O Masking ; Byte 1 : I/O and Pixel Masking ; Byte 0 : DQM Byte Maskin g
¨é Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable
¨ê Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110"
(Pixel Mask)
i) ILLUSTRATION
I/O(=DQ)
31
Color Register
24
Blue
11000011
23
16
Green
11100001
15
8
Yellow
00001111
7
0
Red
10100011
DQMi
DQM 3=0
DQM 2=0
DQM 1 =0
DQM 0 =1
Mask Register
11111111
11011101
01000010
01110110
Before Write
Yellow
00001111
Yellow
00001111
Green
11100001
White
00000000
After Write
Blue
11000011
Blue
11000011
Red
10100011
White
00000000
31
23
15
7
Note 1
I/O(=DQ)
DQMi
DQM 3 =0
Color Register
Before
Block
Write
&
DQ
(Pixel
data)
After
Block
Write
24
16
8
DQM 2 =0
DQM 1 =0
0
DQM0 =1
Color3=Blue
Color2=Green
Color1=Yellow
Color0=Red
000
Yellow DQ 24 =H
Yellow DQ 16 =H
Green DQ 8=H
White DQ 0 =L
001
Yellow DQ 25 =H
Yellow DQ 17 =H
Green DQ 9 =L
White DQ 1 =H
010
Yellow DQ 26 =H
Yellow DQ 18 =H
Green DQ 10 =H
White DQ 2 =H
011
Yellow DQ 27 =L
Yellow DQ 19 =H
Green DQ 11 =L
White DQ 3 =H
100
Yellow DQ 28 =H
Yellow DQ 20 =H
Green DQ 12 =H
White DQ 4 =L
101
Yellow DQ 29 =H
Yellow DQ 21 =H
Green DQ 13 =L
White DQ 5 =H
110
Yellow DQ 30 =H
Yellow DQ 22 =H
Green DQ 14 =H
White DQ 6 =H
111
Yellow DQ 31 =L
Yellow DQ 23 =H
Green DQ 15 =L
White DQ 7 =H
000
Blue
Blue
Red
White
001
Blue
Blue
Green
White
010
Blue
Blue
Red
White
011
Yellow
Blue
Green
White
100
Blue
Blue
Red
White
101
Blue
Blue
Green
White
110
Blue
Blue
Red
White
111
Yellow
Blue
Green
Note 2
White
Note 1
PIXEL MASK
I/O MASK
PIXEL & I/O MASK
BYTE MASK
*Note :1. DQM byte masking.
2. At normal write, ONE column is selected among columns decorded by A 2-0 (000-111).
At block write, instead of ignored address A 2-0 , DQ0-31 control each pixel.
- 27
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Power On Sequence & Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High level is necessary
¡ó
¡ó
CS
tRP
tRC
RAS
CAS
ADDR
A 9 /BA
A 8 /AP
WE
DSF
DQM
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
KEY
Ra
KEY
BS
KEY
Ra
High level is necessary
High-Z
DQ
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Register Set
Row Active
(Write per Bit
Enable or Disable)
: Don ′t care
- 28
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
t CH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
t CL
tCC
HIGH
CKE
tRAS
t RC
*Note 1
tSH
CS
tRCD
tRP
tSS
t SH
RAS
t CCD
t SS
tSH
CAS
tSS
tSH
ADDR
Ra
t SS
Ca
Cb
t SS
*Note 2
A9
BS
A8
Ra
Cc
Rb
t SH
*Note 2,3
*Note 2,3
*Note 4
*Note 2
BS
BS
BS
BS
*Note 3
*Note 3
*Note 4
BS
*Note 3
*Note 2,3
Rb
t SH
WE
t SS
*Note 5
*Note 6
DSF
*Note 5
*Note 3
tSS
tSH
t SS
t SH
DQM
t RAC
tSH
t SAC
Qa
DQ
tSLZ
Db
Qc
tSS
tOH
t SHZ
Row Active
(Write per Bit
Enable or Disable)
Read
Write
or
Block Write
Read
Precharge
Row Active
(Write per Bit
Enable or
Disable)
: Don′t care
- 29
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
*Note : 1. All input can be don't care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by A 9 .
A9
Active & Read/Write
0
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A 8 in read/write command.
A8
A9
0
1
Operation
0
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4. A8 and A 9 control bank precharge when precharge command is asserted.
A8
A9
Precharge
0
0
Bank A
0
1
Bank B
1
X
Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A9
0
1
DSF
Operation
L
Bank A row active, disable write per bit function for bank A
H
Bank A row active, enable write per bit function for bank A
L
Bank B row active, disable write per bit function for bank B
H
Bank B row active, enable write per bit function for bank B
6. Block write/normal write is controlled by DSF.
DSF
Operation
Minimum cycle time
L
Normal write
H
Block write
tCCD
t BWC
- 30
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
t RC
CS
tRCD
RAS
*Note 2
CAS
ADDR
Ra
Ca0
Cb0
Rb
A9
A8
Ra
Rb
WE
DSF
DQM
tOH
DQ
(CL=2)
Qa0
t RAC
*Note 3
Qa1
Qa2
Qa3
t SAC
Db0
tSHZ
Db1
Db2
Db3
tRDL
*Note 4
tOH
DQ
(CL=3)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
tRAC
*Note 3
Row Active
(A-Bank)
Read
(A-Bank)
t SAC
t SHZ
Precharge
(A-Bank)
tRDL
*Note 4
Row Active
(A-Bank)
Db3
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after t SHZ from the clcok.
3. Access time from Row address. t CC *( tRCD + CAS latency - 1) + t SAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8)
At Full page bit burst, burst is wrap-around.
- 31
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
tRCD
RAS
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
A9
A8
Ra
tRDL
tCDL
WE
*Note 2
DSF
*Note 3
*Note 1
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Row Active
(A-Bank)
Read
(A-Bank)
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
- 32
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Block Write cycle(with Auto Precharge)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
*Note 2
ADDR
RAa
CAa
CAb
RBa
CBa
CBb
Pixel
Mask
Pixel
Mask
A9
A8
RAa
RBa
WE
DSF
t BWC
DQM
*Note 1
Pixel
Mask
DQ
Row Active with
Write-per-Bit
Enable
(A-Bank)
Pixel
Mask
Masked
Block Write
(A-Bank)
Row Active
(B-Bank)
Block Write with
Auto Precharge
(B-Bank)
Block Write
(B-Bank)
Masked
Block Write with
Auto Precharge
(A-Bank)
: Don′t care
*Note : 1. Column Mask(DQi=L : Mask, DQi=H :Non Mask)
2. At Block Write, CA 0~2 are ignored.
- 33
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
SMRS and Block/Normal Write @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note 1
RBa
CBa
CAa
RBa
CBa
RAa
CAa
RBa
CBa
A6
RAa
CAa
RBa
CBa
A8
RAa
A 0-2
RAa
A3,4,7
RAa
A5
RBa
A9
WE
DSF
DQM
DQ
Color
I/O
Mask
Load Color
Register
Load Mask
Register
Row Active
with WPB*
Enable
(A-Bank)
Pixel
Mask
Masked
Block Write
(A-Bank)
I/O
Mask
Row Active
with WPB*
Enable
(B-Bank)
Color
DBa0 DBa1 DBa2 DBa3
Load Color
Register
Load Mask Register
Masked Write
with Auto
Precharge
(B-Bank)
WPB* : Write-Per-Bit
: Don′t care
*Note :
1. At the next clock of special mode set command, new command is possible.
- 34
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Page Read Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note 1
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A9
A8
RAa
RBb
WE
LOW
DSF
DQM
QAa0
DQ
(CL=2)
DQ
(CL=3)
Row Active
(A-Bank)
Row Active
(B-Bank)
QAa1
QAa2
QAa3
QBb0
QBb1 QBb2
QAa0
QAa1
QAa2
QAa3
QBb0
Read
(B-Bank)
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
QBb1 QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
QAe1
Precharge
(A-Bank)
Read
(A-Bank)
: Don′t care
*Note :
1. CS can be don ′t care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
- 35
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
Key
CAa
RBb
CBb
CBd
CAc
A9
A8
RAa
RBb
t CDL
WE
DSF
DQM
DQ
Mask
Load Mask
Register
Row Active with
Write-Per-Bit
enable
(A-Bank)
DAa0
DAa1
DAa2
Row Active
(B-Bank)
DAa3
DBb0
DBb1
Write
(B-Bank)
DBb2
DBb3
DAc0
DAc1
Masked Write
with auto
precharge
(A-Bank)
Masked Write
(A-Bank)
DAc2
DAc3
DBd0
DBd1
DBd2
DBd3
Write with auto
Precharge
(B-Bank)
: Don′t care
- 36
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
A9
A8
RAa
RAc
RBb
tCDL
*Note 1
WE
DSF
DQM
DQ
(CL=2)
QAa0
DQ
(CL=3)
Row Active
(A-Bank)
QAa1
QAa2
QAa3
QAa0
QAa1
QAa2
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
QAa3
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
Write
(B-Bank)
QAc0
QAc1
QAc2
QAc0
QAc1
Read
(A-Bank)
Row Active
(A-Bank)
: Don ′t care
*Note :
1. t CDL should be met to complete write.
- 37
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read & Write Cycle with Auto Precharge I @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
A9
A8
WE
DSF
DQMi
DQ
(CL=2)
QAa0
DQ
(CL=3)
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
QAa1
QAa2
QAa3
QAa0
QAa1
QAa2
QAa3
Auto Precharge
Start Point
(A-Bank)
DBb0
DBb1
DBb2
DBb3
DBb0
DBb1
DBb2
DBb3
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
Row Active
(B-Bank)
: Don′t care
*Note : 1. tRCD should be controlled to meet minimum t RAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
- 38
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read & Write Cycle with Auto Precharge II @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Ra
Cb
Ca
A9
A8
Ra
WE
DSF
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Row Active
(A-Bank)
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
Qa1
Qb0
Qb1
Qb2
Qb3
Qa0
Qa1
Qb0
Qb1
Qb2
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank) *Note 1
Precharge
(B-Bank)
Qb3
Row Active
(A-Bank)
Da0
Da1
Da0
Da1
Write with
Auto Precharge
(A-Bank)
: Don′ t care
*Note:
1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
- 39
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read & Write Cycle with Auto Precharge III @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Rb
A9
A8
Ra
Rb
WE
DSF
DQM
DQ
(CL=2)
Qa0
DQ
(CL=3)
Qa1
Qa2
Qa3
Qa0
Qa1
Qa2
Qb0
Qa3
Qb1
Qb0
Qb2
Qb1
Qb3
Qb2
Qb3
*Note 1
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don ′t care
*Note :
1. Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
- 40
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note 1
*Note 1
A9
A8
RAa
WE
DSF
DQM
1
*Note 2
DQ
(CL=2)
QAa0
QAa1
QAa2
QAa3
1
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAb0
QAb1
QAb2
QAb3
QAb4
2
DQ
(CL=3)
QAa0
Row Active
(A-Bank)
Read
(A-Bank)
QAa1
QAa2
QAa3
Burst Stop
QAa4
2
Read
(A-Bank)
QAb5
Precharge
(A-Bank)
: Don′t care
*Note :
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ ′s after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at full page mode.
- 41
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full page Only)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
*Note 1
*Note 1
A9
A8
RAa
tBDL
tRDL
WE
DSF
*Note 3
DQM
*Note 2
DAa0
DQ
Row Active
(A-Bank)
DAa1
DAa2
Write
(A-Bank)
DAa3
DAa4
DAb0
Burst Stop
DAb1
DAb2
DAb3
DAb4
DAb5
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note :
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of burst stop command cannot be written into the corresponding memory cell.
It is defined by AC parameter of t BDL (=1CLK).
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of
t RDL (=1CLK).
DQM at write interrupted by precharge command is needed to ensure t RDL of 1CLK.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
4. Burst stop is valid only at full page burst length.
- 42
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Burst Read Single bit Write Cycle @Burst Length=2, BRSW
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note 1
HIGH
CKE
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
A9
A8
RAa
RBb
RAc
WE
DSF
DQM
DQ
(CL=2)
DAa0
DQ
(CL=3)
DAa0
Row Active
(A-Bank)
QAb0
QAb1
QAb0
Row Active
(B-Bank)
Write
(A-Bank)
QAd0
DBc0
QAb1
QAd0
DBc0
Row Active
(A-Bank)
QAd1
Read
(A-Bank)
QAd1
Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
: Don′t care
*Note :
1. BRSW mode is enabled by setting A 9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that t RAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
3. WPB function is also possible at BRSW mode.
- 43
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Clock suspension & DQM operation cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A9
A8
Ra
WE
DSF
*Note 1
DQM
DQ
Qa0
Qa1
Qa2
Qb0
Qa3
tSH Z
Row Active
Read
Clock
Suspension
Read
Qb1
Dc0
Dc2
tSH Z
Write
DQM
Read DQM
Write
Clock
Suspension
: Don′t care
*Note :
1. DQM needed to prevent bus contention.
- 44
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
¡ó
CLOCK
¡ó
tSS
¡ó
*Note 2
tSS
t SS
t SS
*Note 1
CKE
¡ó
*Note 3
¡ó
¡ó
CS
¡ó
RAS
CAS
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
ADDR
¡ó
A9
WE
DSF
DQM
DQ
Precharge
Power-down
Entry
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
A8
¡ó
Ra
¡ó
Ra
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
Precharge
Power-down
Exit
Row Active
Qa0
Read
Active
Power-down
Entry
*Note :
Ca
Active
Power-down
Exit
Qa1
Qa2
Precharge
: Don′t care
1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least "1CLK + t SS " prior to Row active command.
3. Cannot violate minimum refresh specification. (16ms)
- 45
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
CLOCK
¡ó
7
8
9
¡ó
10
11
12
13
16
17
18
19
t RC min.
tSS
*Note 1
*Note 3
CKE
15
¡ó
*Note 4
*Note 2
14
¡ó
*Note 6
¡ó
tSS
¡ó
¡ó
CS
*Note 5
¡ó
RAS
*Note 7
CAS
ADDR
A9
A8
WE
DSF
DQM
DQ
Hi-Z
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
Hi-Z
Self Refresh Entry
*Note :
*Note 7
¡ó
Self Refresh Exit
Auto Refresh
: Don′t care
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don ′ t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 1K cycle of burst auto refresh is required before self refresh entry and after self refresh exit
- 46
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
Mode Register Set Cycle
0
1
2
3
4
5
Auto Refresh Cycle
6
7
8
9
10
11
12
13
14
CLOCK
15
16
17
18
19
¡ó
HIGH
CKE
¡ó
HIGH
¡ó
CS
*Note 2
tRC
RAS
¡ó
¡ó
¡ó
*Note 1
¡ó
CAS
¡ó
*Note 3
ADDR
Key
¡ó
Ra
¡ó
¡ó
WE
¡ó
¡ó
DSF
¡ó
¡ó
DQM
¡ó
DQ
Hi-Z
Hi-Z
MRS New
Command
¡ó
Auto Refresh
New Command
: Don′t care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note :
1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal
mode register.
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
- 47
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
FUNCTION TRUTH TABLE(TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
CS
RAS
CAS
WE
DSF
BA
(A 9 )
ADDR
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
2
L
H
L
X
X
BA
CA
ILLEGAL
2
L
L
H
H
L
BA
RA
Row Active ; Latch Row Address ; Non-IO Mask
L
L
H
H
H
BA
RA
Row Active ; Latch Row Address ; IO Mask
L
L
H
L
L
BA
PA
NOP
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
L
X
X
Auto Refresh or Self Refresh
L
L
L
H
H
X
X
ILLEGAL
L
L
L
L
L
OP Code
Mode Register Access
5
L
L
L
L
H
OP Code
Special Mode Register Access
6
H
X
X
X
X
X
X
NOP
L
H
H
H
X
X
X
NOP
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Begin Write ;Latch CA ; Determine AP
L
H
L
L
H
BA
CA,AP
Block Write ;Latch CA ; Determine AP
L
L
H
H
X
BA
RA
ILLEGAL
L
L
H
L
L
BA
PA
Precharge
L
L
H
L
H
X
X
ILLEGAL
L
L
L
H
X
X
X
ILLEGAL
L
L
L
L
L
X
X
ILLEGAL
L
L
L
L
H
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
L
L
X
X
Term burst --> Row active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Term burst ; Begin Write ; Latch CA ; Determine AP
3
L
H
L
L
H
BA
CA.AP
Term burst ; Block Write ; Latch CA ; Determine AP
3
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst ; Precharge timing for Reads
3
L
L
H
L
H
X
X
ILLEGAL
OP Code
ACTION
NOTE
4
5
2
Begin Read ; Latch CA ; Determine AP
ILLEGAL
2
Special Mode Register Access
6
Term burst ; Begin Read ; Latch CA ; Determine AP
3
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Row Active)
L
H
H
L
L
X
X
Term burst --> Row active
L
H
H
L
H
X
X
ILLEGAL
L
H
L
H
L
BA
CA,AP
L
H
L
H
H
X
X
L
H
L
L
L
BA
CA,AP
Term burst ; Begin Write ; Latch CA ; Determine AP
3
L
H
L
L
H
BA
CA,AP
Term burst ; Block Write ; Latch CA ; Determine AP
3
- 48
Term burst ; Begin Read ; Latch CA ; Determine AP
3
ILLEGAL
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
FUNCTION TRUTH TABLE(TABLE 1, Continued)
Current
State
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Precharging
Block
Write
Recovering
Row
Activating
Refreshing
CS
RAS
CAS
WE
DSF
BA
(A 9)
ADDR
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
L
BA
PA
Term Burst : Precharge timing for Writes
3
L
L
H
L
H
X
X
ILLEGAL
ACTION
NOTE
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP(Continue Burst to End --> Precharge)
2
L
H
H
H
X
X
X
NOP(Continue Burst to End --> Precharge)
L
H
H
L
X
X
X
ILLEGAL
L
H
L
H
X
BA
CA,AP
ILLEGAL
2
L
H
L
L
X
BA
CA,AP
ILLEGAL
2
L
L
H
X
X
BA
RA,PA
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP --> Idle after t RP
L
H
H
H
X
X
X
NOP --> Idle after t RP
L
H
H
L
X
X
X
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
NOP --> Idle after t RP
2
L
L
L
X
X
X
X
ILLEGAL
H
X
X
X
X
X
X
NOP --> Row Active after
L
H
H
H
X
X
X
NOP --> Row Active after
L
H
H
L
X
X
X
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
Term Block Write : Precharge timing for Block Write
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP --> Row Active after
L
H
H
H
X
X
X
NOP --> Row Active after
L
H
H
L
X
X
X
ILLEGAL
L
H
L
X
X
BA
CA,AP
ILLEGAL
2
L
L
H
H
X
BA
RA
ILLEGAL
2
L
L
H
L
X
BA
PA
ILLEGAL
2
L
L
L
X
X
X
X
ILLEGAL
2
H
X
X
X
X
X
X
NOP --> Idle after t RC
L
H
H
X
X
X
X
L
H
L
X
X
X
X
NOP --> Idle after t RC
ILLEGAL
L
L
H
X
X
X
X
ILLEGAL
L
L
L
X
X
X
X
ILLEGAL
- 49
2
4
t BWC
t BWC
t RCD
t RCD
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
FUNCTION TRUTH TABLE (TABLE 1, Continued)
ABBREVIATIONS
RA = Row Address(A 0 ~A 9)
NOP = No Operation Command
BA = Bank Address(A 10 )
CA = Column Address(A 0 ~A7 )
PA = Precharge All(A 9)
AP = Auto Precharge(A 9)
*Note : 1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).
5. Illegal if any banks is not idle.
6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE(TABLE 2)
Current
State
Self
Refresh
Both
Bank
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
Above
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DSF
ADDR
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Exit Self Refresh --> ABI after tRC
7
L
H
L
H
H
H
X
X
Exit Self Refresh --> ABI after tRC
7
L
H
L
H
H
L
X
X
ILLEGAL
L
H
L
H
L
X
X
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Self Refresh)
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Exit Power Down --> ABI
8
L
H
L
H
H
H
X
X
Exit Power Down --> ABI
8
L
H
L
H
H
L
X
X
ILLEGAL
L
H
L
H
L
X
X
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Power Down Mode)
H
H
X
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
X
Enter Power Down
9
H
L
L
H
H
H
X
X
Enter Power Down
9
H
L
L
H
H
L
X
X
ILLEGAL
H
L
L
H
L
X
X
X
ILLEGAL
H
L
L
L
H
H
L
RA
H
L
L
L
L
H
L
X
H
L
L
L
L
L
L
OP Code
Mode Register Access
H
L
L
L
L
L
H
OP Code
Special Mode Register Access
L
L
X
X
X
X
X
X
NOP
H
H
X
X
X
X
X
X
Refer to Operations in Table 1
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
10
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
10
L
L
X
X
X
X
X
X
Maintain clock Suspend
ACTION
NOTE
Row (& Bank) Active
Enter Self Refresh
9
ABBREVIATIONS : ABI = All Banks Idle
*Note : 7. After CKE ′s low to high transition to exist self refresh mode. And a time of tRC (min) has to be elapse after CKE ′ s low to high
transition to issue a new command.
8. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time " tSS + one clock" must be satisfied before any command other than exit.
9. Power-down and self refresh can be entered only from the all banks idle state.
10. Must be a legal command.
- 50
Rev. 2.4 (May 1998)
KM4132G271B
CMOS SGRAM
PACKAGE DIMENSIONS (TQFP)
Dimensions in Millimeters
0 ~ 7°
17.20 ±
0.20
14.00 ±
0.10
#100
#1
0.20
20.00 ±
0.10
0.575
23.20 ±
0.825
0.30 ±
0.08
0.09~0.20
0.65
0.13 MAX
1.00 ±
0.10
1.20 MAX *
0.10 MAX
0.05 MIN
0.80 ±
0.20
* All Package Dimensions of PQFP & TQFP are same except Height.
- PQFP (Height = 3.0mmMAX)
- TQFP (Height = 1.2mmMAX)
- 51
Rev. 2.4 (May 1998)