KM416V4004B, KM416V4104B CMOS DRAM 4M x 16bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. • Extended Data Out Mode operation FEATURES • 2 CAS Byte/Word Read/Write operation • Part Identification • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability - KM416V4004B/B-L(3.3V, 8K Ref.) - KM416V4104B/B-L(3.3V, 4K Ref.) • Fast parallel test mode capability • Self-refresh capability (L-ver only) • LVTTL(3.3V) compatible inputs and outputs • Active Power Dissipation • Early Write or output enable controlled write Unit : mW 8K 4K -45 360 468 -5 324 432 -6 288 396 • JEDEC Standard pinout • Available in Plastic TSOP(II) packages • +3.3V±0.3V power supply • Refresh Cycles Part NO. Refresh cycle KM416V4004B* 8K KM416V4104B FUNCTIONAL BLOCK DIAGRAM Refresh time Normal L-ver 64ms 128ms 4K RAS UCAS LCAS W * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) Control Clocks Refresh Timer Refresh Counter Speed tRAC tCAC tRC tHPC -45 50ns 12ns 74ns 17ns -5 50ns 13ns 84ns 20ns -6 60ns 15ns 104ns 25ns A0~A12 (A0~A11)*1 Row Address Buffer A0~A8 (A0~A9)*1 Col. Address Buffer Lower Data in Buffer Row Decoder Refresh Control • Performance Range Vcc Vss VBB Generator Memory Array 4,194,304 x 16 Cells Column Decoder Note) *1 : 4K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O Speed Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer DQ0 to DQ7 OE DQ8 to DQ15 KM416V4004B, KM416V4104B CMOS DRAM PIN CONFIGURATION (Top Views) •KM416V40(1)04BS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 ¡Û 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product Pin Name Pin function A0 - A12 Address Inputs(8K Product) A0 - A11 Address Inputs(4K Product) DQ0 - 15 Data In/Out VSS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+3.3V) N.C No Connection KM416V4004B, KM416V4104B CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Units VIN,VOUT -0.5 to +6.5 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V Storage Temperature Tstg -55 to +150 °C Power Dissipation PD 1 W Short Circuit Output Current IOS 50 mA Voltage on any pin relative to VSS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Symbol Min Typ Max Units Supply Voltage VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 - +5.5*1 V Input Low Voltage VIL -0.3*2 - 0.8 V *1 : 6.5V at pulse width≤15ns which is measured at VCC *2 : -1.3 at pulse width≤15ns which is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V KM416V4004B, KM416V4104B CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Max Speed Units KM416V4004B KM416V4104B ICC1 Don′t care -45 -5 -6 100 90 80 130 120 110 mA mA mA ICC2 Normal L Don′t care 2 2 2 2 mA mA ICC3 Don′t care -45 -5 -6 100 90 80 130 120 110 mA mA mA ICC4 Don′t care -45 -5 -6 110 100 90 120 110 100 mA mA mA ICC5 Normal L Don′t care 500 300 500 300 uA uA ICC6 Don′t care -45 -5 -6 100 90 80 130 120 110 mA mA mA ICC7 L Don′t care 400 400 uA ICCS L Don′t care 400 400 uA ICC1 * : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3 * : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4 * : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC =min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one EDO mode cycle time, tHPC . KM416V4004B, KM416V4104B CMOS DRAM CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A12] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter -45 Symbol Min -5 Max Min -6 Max Min Units Note Max Random read or write cycle time tRC 74 84 104 ns Read-modify-write cycle time tRWC 101 113 138 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 12 13 15 ns 3,4,5 Access time from column address tAA 23 25 30 ns 3,10 CAS to output in Low-Z tCLZ 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 ns 6,21 OE to output in Low-Z tOLZ 3 ns 3 Transition time (rise and fall) tT 1 ns 2 RAS precharge time tRP 25 RAS pulse width tRAS 45 RAS hold time tRSH 8 8 10 ns CAS hold time tCSH 35 38 40 ns CAS pulse width tCAS 7 5K 8 10K 10 10K ns RAS to CAS delay time tRCD 11 33 11 37 14 45 ns 4 RAS to column address delay time tRAD 9 22 9 25 12 30 ns 10 CAS to RAS precharge time tCRP 5 3 13 3 3 13 3 50 1 50 5 13 3 50 30 10K 3 1 50 40 10K 60 5 ns 10K ns ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 7 7 10 ns Column address set-up time tASC 0 0 0 ns 13 Column address hold time tCAH 7 7 10 ns 13 Column address to RAS lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 7 7 10 ns Write command pulse width tWP 6 7 10 ns Write command to RAS lead time tRWL 8 8 10 ns Write command to CAS lead time tCWL 7 7 10 ns 16 Data set-up time tDS 0 0 0 ns 9,19 KM416V4004B, KM416V4104B CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -45 Symbol Min Data hold time tDH Refresh period (Normal) tREF Refresh period (L-ver) tREF Write command set-up time -5 Max 7 Min -6 Max 7 64 Min 10 64 128 128 Units Note ns 9,19 Max 64 ms 128 ms tWCS 0 0 0 ns 7 CAS to W delay time tCWD 24 27 32 ns 7,15 RAS to W delay time tRWD 57 64 77 ns 7 Column address to W delay time tAWD 35 39 47 ns 7 CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 5 ns 17 CAS hold time (CAS -before-RAS refresh) 18 tCHR 10 10 10 ns RAS to CAS precharge time tRPC 5 5 5 ns Access time from CAS precharge tCPA Hyper Page cycle time tHPC 17 20 Hyper Page read-modify-write cycle time tHPRWC 47 CAS precharge time (Hyper page cycle) tCP 6.5 RAS pulse width (Hyper page cycle) 24 200K 28 ns 3 25 ns 20 47 56 ns 20 7 10 ns 14 50 200 35 tRASP 45 RAS hold time from CAS precharge tRHCP 24 OE access time tOEA OE to data delay tOED 8 10 13 ns CAS precharge to W delay time tCPWD 36 41 52 ns Output buffer turn off delay time from OE tOEZ 3 OE command hold time tOEH 5 5 5 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns 11 Write command hold time (Test mode in) tWTH 10 10 10 ns 11 W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns Output data hold time tDOH 4 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 13 30 12 11 60 13 3 200 35 13 3 13 3 13 ns 15 3 ns 13 ns ns 6 3 13 ns 6,21 3 13 ns 6 Output buffer turn off delay from W tWEZ 3 W to data delay tWED 8 15 15 ns OE to CAS hold time tOCH 5 5 5 ns CAS hold time to OE tCHO 5 5 5 ns OE precharge time tOEP 5 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 5 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 22,23,24 RAS precharge time (C-B-R self refresh) tRPS 74 90 110 ns 22,23,24 CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 22,23,24 KM416V4004B, KM416V4104B CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -45 Symbol Min -5 Max Min -6 Ma Min Units Note Ma Random read or write cycle time tRC 79 89 Read-modify-write cycle time tRWC 110 121 Access time from RAS tRAC 50 55 65 ns 3,4,10,12 Access time from CAS tCAC 17 18 20 ns 3,4,5,12 Access time from column address tAA 28 30 35 ns 3,10,12 RAS pulse width tRAS 50 10K 55 10 65 10 ns CAS pulse width tCAS 12 10K 13 10 15 10 ns RAS hold time tRSH 18 18 20 ns CAS hold time tCSH 39 43 50 ns Column Address to RAS lead time tRAL 28 30 35 ns CAS to W delay time tCWD 29 35 39 ns 7 RAS to W delay time tRWD 62 72 84 ns 7 Column Address to W delay time tAWD 40 47 54 ns 7 Hyper Page cycle time tHPC 22 25 30 ns 20 Hyper Page read-modify-write cycle time tHPRWC 52 53 61 ns 20 RAS pulse width (Hyper page cycle) tRASP 50 Access time from CAS precharge tCPA 29 OE access time tOEA 17 OE to data delay tOED 13 18 20 ns OE command hold time tOEH 13 18 20 ns 200K 55 ns 145 200 65 ns 200 ns 33 40 ns 18 20 ns 3 KM416V4004B, KM416V4104B CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min) and tAWD ≥tAWD (min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tASC , tCAH are referenced to the earlier CAS falling edge. 14. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. KM416V40(1)04B Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - KM416V4004B, KM416V4104B CMOS DRAM 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to the earlier CAS falling edge before RAS transition low. 18. tCHR is referenced to the later CAS rising edge after RAS transition low. RAS LCAS UCAS tCSR tCHR 19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle. LCAS UCAS tDS DQ0 ~ DQ15 tDH Din 20. tASC ≥6ns, Assume tT = 2.0ns 21. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 22. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 23. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 24. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM416V4004B, KM416V4104B CMOS DRAM WORD READ CYCLE tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCRP tRSH VIH - tCAS VIL - tCSH tCRP LCAS tRP VIH - tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tAA tOLZ OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH VOL - tRAC tCAC tCLZ OPEN tCEZ tOEZ DATA-OUT tCAC DQ8 ~ DQ15 VOH VOL - tRAC OPEN tCLZ tCEZ tOEZ DATA-OUT Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM LOWER BYTE READ CYCLE NOTE : DIN = OPEN tRC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCSH tCRP LCAS tRSH tCAS VIH VIL - tRAD tASR A tRCD VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCH tRCS W tRRH VIH VIL - tCEZ tAA OE VIH - tOEA VIL - DQ0 ~ DQ7 VOH VOL - tOEZ tRAC tCAC tCLZ OPEN DATA-OUT tOLZ DQ8 ~ DQ15 VOH VOL - OPEN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM UPPER BYTE READ CYCLE NOTE : DIN = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD tCAS VIL - tRPC tCRP LCAS tCRP tRSH VIH - VIH VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ DQ0 ~ DQ7 VOH - OPEN VOL DQ8 ~ DQ15 VOH VOL - tCAC tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCAS tCSH tRCD tRSH VIL - VIH VIL - OE tCRP tCAS VIH - tRAD tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tWCS W tCRP VIL - tASR A tRSH VIH - tCRP LCAS tRP VIH - VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tDS DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH DATA-IN VIL - Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCRP UCAS VIH VIL - tCSH tCRP LCAS tRCD tRSH tCRP tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD tRSH VIH - tCRP tCAS VIL - tCRP LCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W OE VIH - tWCH tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRCD tCRP tCAS VIL - tCSH tRCD tRSH VIL - VIH VIL - tCRP tCAS VIH - tRAD tASR A tRSH VIH - tCRP LCAS tRP VIH - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ7 VIH - tOEH tOED tDS DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH DATA-IN VIL - Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCSH tCRP LCAS tRCD tRSH tCRP tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - DQ0 ~ DQ7 VIH VIL - tOEH tOED tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP UCAS tRP VIH - tRCD VIL - tCRP LCAS W OE tCRP VIH VIL - tRAD tASR A tCRP tRSH tCAS VIH - VIH VIL - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL VIH - tWP VIL - VIH VIL - tOEH tOED DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM WORD READ - MODIFY - WRITE CYCLE tRWC tRAS RAS UCAS LCAS tRP VIH VIL - tCRP tRCD tRSH tCAS tCRP tRCD tRSH VIH VIL - tCAS VIH VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH COLUMN ADDRESS tAWD tRWL tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH - tOED tOEZ tRAC VALID DATA-OUT VI/OL - tDS tDH VALID DATA-IN tOLZ tCLZ tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM LOWER-BYTE READ - MODIFY - WRITE CYCLE tRWC tRAS RAS tRP VIH VIL - tRPC tCRP UCAS VIH VIL - tCRP LCAS tRCD tRSH VIH - tCAS VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR. tASC tCAH COLUMN ADDRESS tAWD tRWL tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VOH VOL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN OPEN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM UPPER-BYTE READ - MODIFY - WRITE CYCLE tRWC tRAS RAS VIL - tCRP UCAS tRP VIH - tRCD tRSH VIH - tCAS VIL - tRPC tCRP LCAS VIH VIL - tRAD tCSH tASR A VIH VIL - tRAH ROW ADDR tASC tCAH COLUMN ADDRESS tAWD tRWL tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - DQ0 ~ DQ7 VOH - OPEN VOL - tOLZ tCLZ tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE WORD READ CYCLE tRASP RAS tRP VIH VIL - tCSH tCRP UCAS tRCD tCP tHPC tCP tCAS tCP tCAS tCAS VIL - tCP tRCD VIL - VIH VIL - tRAD tRAH tASC ROW ADDR tCP tCAS VIH - tASR A tHPC tCAS VIH - tCRP LCAS tRHCP tHPC tCAS tCAH tASC COLUMN ADDRESS tCAH tREZ tCP tCAS tASC COLUMN ADDRESS tCAH COLUMN ADDR tCAS tASC tCAH COLUMN ADDRESS tRAL tRCS W VIH VIL - tAA tAA tCPA tOCH tOEA VIH - tCHO tOEP tOEA VIL - tCAC DQ0 ~ DQ7 VOH - tCPA tCAC tAA tCAC tCPA tCAC OE tRRH tRCH tOEP tDOH tRAC VALID DATA-OUT VOL - tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ tCAC DQ8 ~ DQ15 VOH - tRAC tOEP tDOH VALID DATA-OUT VOL - tOEZ tOEZ tOLZ tCLZ Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE LOWER BYTE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tRPC tCRP UCAS VIH - tCSH VIL - tRHCP tHPC tCP tRCD LCAS tCP tCAS VIH - tCAS tHPC tREZ tCP tCAS tCAS tCAH tASC tCAH VIL - tASR A tHPC VIH VIL - tRAD tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tASC tCAH tASC COLUMN ADDRESS COLUMN ADDR COLUMN ADDRESS tRAL tRCS W VIH VIL - tAA tCPA tAA OE tRRH tRCH tAA tCPA tCAC tOCH tOEA VIH - tCAC tRAC VOL - tOEP tDOH VALID DATA-OUT VOL - DQ8 ~ DQ15 VOH - tCHO tOEP tOEA VIL - DQ0 ~ DQ7 VOH - tCPA tCAC tAA tCAC tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ OPEN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE UPPER BYTE READ CYCLE tRASP RAS tRP VIH VIL - ¡ó tCSH tCRP UCAS tRHCP tHPC tRCD tCP tCAS VIH - tHPC tHPC tCP tCAS tCP tRPC tCAS tCAS VIL - tCRP LCAS VIL - tASR A tRPC VIH - VIH VIL - tRAD tRAH tASC ROW ADDR. tCAH tASC tCAH tASC COLUMN ADDRESS COLUMN ADDRESS tCAH COLUMN ADDR. tASC tCAH tREZ COLUMN ADDRESS tRAL tRCS W VIH VIL - tAA tCPA tOCH tOEA VIH - tCHO tOEP tOEA VIL - DQ0 ~ DQ7 VOH - OPEN VOL - tCAC DQ8 ~ DQ15 VOH - tCPA tCAC tAA tCAC tAA tCPA tCAC OE tRRH tRCH tRAC tOEP tDOH VALID DATA-OUT VOL - tOEZ tOEZ tOEZ VALID VALID VALID VALID DATA-OUT DATA-OUT DATA-OUT DATA-OUT tOLZ tCLZ Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRHCP VIL - ¡ó tHPC tCRP UCAS tHPC tCP tRCD VIH - tRSH tCP tCAS tCRP tCAS VIL - tCAS ¡ó tHPC tCRP LCAS tRP VIH - tHPC tCP tRCD VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRAD tRAL tCSH tASR A VIH VIL - tRAH tASC tCAH OE tCAH tASC tCAH ¡ó ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W tASC tWCH tWCS tWP VIH - ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIH VIL - DQ0 ~ DQ7 VIH - ¡ó tDS VIL - tDS tDH tDS tDH ¡ó VALID DATA-IN VIL - DQ8 ~ DQ15 VIH - tDH tDS tDH VALID DATA-IN tDS ¡ó tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRP VIH - tRHCP VIL - ¡ó tRPC tCRP UCAS VIH VIL - tHPC tCRP LCAS tRCD tHPC tCP VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRAD tRAL tCSH tASR A VIH VIL - tRAH tCAH tASC OE VIH - tASC tCAH tCAH ¡ó ROW ADDR COLUMN ADDRESS tWCS W tASC tWCH COLUMN ADDRESS tWCS tWP ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIH VIL - DQ0 ~ DQ7 VIH VIL - ¡ó tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRASP RAS tRHCP VIL - ¡ó tHPC tCRP UCAS tRP VIH - tRCD tHPC tCP VIH - tRSH tCP tCAS tCAS VIL - tCAS ¡ó tRPC tCRP LCAS VIH VIL - tRAD tRAL tCSH tASR A VIH VIL - tRAH tASC tCAH OE VIH - tCAH tASC tCAH ¡ó ROW ADDR COLUMN ADDRESS tWCS W tASC tWCH COLUMN ADDRESS tWCS tWP ¡ó tWCH tWP COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - ¡ó VIH VIL - ¡ó DQ0 ~ DQ7 VIH - ¡ó VIL - DQ8 ~ DQ15 VIH VIL - ¡ó tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tCRP UCAS tRSH tRCD tCRP tCP VIH - tCAS tCAS VIL - tCRP LCAS tHPRWC VIL - tRCD tCRP tCP VIH - tCAS tCAS VIL - tRAD tRAH tASR A VIH VIL - tRAL tCAH tASC tASC ROW ADDR COL. ADDR COL. ADDR tRCS W tCAH tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRWL tCWL tRCS VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL - tDH tCAC tAA tDS tOEZ tDH tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT tOED tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tDS tOEZ tDH tOEZ tOED tCAC tAA tDS VALID DATA-IN tDH tOEZ tDS tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tHPRWC VIL - tRPC tCRP UCAS VIH VIL - tCRP LCAS tRSH tCP tRCD VIH - tCAS tCAS VIL - tRAD tRAH tASR A VIH VIL - ROW ADDR tCAH tASC tCAH tASC COL. ADDR tRWL tCWL tRCS tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tCPWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCRP VIH - tOEA tOEA VIL - tOED tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL - tOEZ tRAC VI/OL - tDH tAA tDH tDS tDS tCLZ tOEZ tCLZ tOLZ DQ8 ~ DQ15 VI/OH - tOED tCAC VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN OPEN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH tCRP UCAS tHPRWC VIL - tRSH tCP tRCD VIH - tCAS tCRP tCAS VIL - tRPC tCRP LCAS VIH VIL - tRAD tRAH tASR A VIH VIL - ROW ADDR tCAH tASC COL. ADDR tRWL tCWL tRCS tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCAH tASC VIH - tCPWD tOEA tOEA VIL - DQ0 ~ DQ7 VI/OH - OPEN VI/OL - tOLZ tOLZ tOED tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tCAC tCAC tOEZ tDS tCLZ tDH tAA tDH tDS tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC ) READ(tCPA ) tHPC VIH VIL - tCP tCP tCAS tRCD tCAS tHPC tHPC VIH - tCP VIL - tASR A VIH VIL - tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tCAH tASC tCP tASC COLUMN ADDRESS tCAH COL. ADDR tHPC tCAS tCAS tCAS tCAS tRAD tCAS tCAS tCP LCAS tRHCP tHPC tHPC tCP UCAS READ(tAA ) WRITE VIL - tASC tCAH COL. ADDR tRAL tRCS W tRCH tRCS tRCH tWCH tRCH tWCS VIH VIL - tWPE tCLZ tCPA OE tWED VIH VIL - DQ0 ~ DQ7 VI/OH - tOEA tCAC tAA VI/OL - tWEZ tDH tDS tAA tREZ tRAC VALID DATA-OUT VI/OL - DQ8 ~ DQ15 VI/OH - tWEZ tOEA tCAC tAA tWEZ VALID DATA-OUT tWEZ VALID DATA-IN tDH tDS VALID DATA-OUT tAA tREZ tRAC VALID DATA-OUT VALID DATA-OUT VALID DATA-IN VALID DATA-OUT Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRC VIH - RAS tRP tRAS VIL - tRPC tCRP VIH - UCAS VIL - tCRP VIH - LCAS VIL - tASR VIH - A VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIL - tRP tRAS VIH - tRPC tRPC tCP UCAS tCSR VIH - tCHR VIL - tCP LCAS tCSR VIH - tCHR VIL - DQ0 ~ DQ7 VOH - tCEZ OPEN VOL DQ8 ~ DQ15 VOH VOL - W OPEN tWRP tWRH VIH VIL Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRSH tCHR tRCD tRSH tCHR VIL - VIH VIL - tRAD tASR A tRCD VIH - tCRP LCAS VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tWRH tRCS W tRP tRAS VIL - tCRP UCAS tRC tRP VIH VIL - tRAL tAA OE VIH - tOEA VIL - tCEZ tREZ tCAC tCLZ DQ0 ~ DQ7 VOH VOL - DQ8 ~ DQ15 VOH VOL - tRAC tWEZ tOLZ tOEZ OPEN DATA-OUT OPEN DATA-IN DATA-OUT Don′t care Undefined * In Hidden refresh cycle of 64Mb A-die & B-die, when CAS signal transits from Low to High, the valid data may be cut off. KM416V4004B, KM416V4104B CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS tRAS VIH - tRSH tCHR tRCD tRSH tCHR VIL - VIH VIL - tRAD tASR A tRCD VIH - tCRP LCAS tRP tRAS VIL - tCRP UCAS tRC tRP VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQ0 ~ DQ7 VIH - DATA-IN VIL - tDS DQ8 ~ DQ15 VIH VIL - tDH tDH DATA-IN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care tRP tRASS tRPS VIH - RAS VIL - tRPC tRPC tCP UCAS VIH - tCHS tCSR tCHS VIL - tCP LCAS tCSR VIH VIL - DQ0 ~ DQ7 VOH - tCEZ OPEN VOL DQ8 ~ DQ15 VOH - OPEN VOL - tWRP tWRH VIH - W VIL - TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRP VIH - RAS VIL - tRP tRAS tRPC tRPC tCP UCAS tCSR VIH - tCP LCAS W tCHR VIL - tCSR VIH - tCHR VIL - VIL - tWTS tWTH VIH - DQ0 ~ DQ15 VOH VOL - tCEZ OPEN Don′t care Undefined KM416V4004B, KM416V4104B CMOS DRAM PACKAGE DIMENSION 50 TSOP(II) 400mil 0.400 (10.16) 0.455 (11.56) 0.471 (11.96) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.034 (0.875) 0.0315 (0.80) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O