KM44C1000D, KM44V1000D CMOS DRAM 1M x 4Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 1,048,576 x 4bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, self-refresh operation is available in 3.3V Low power version. This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high performance microprocessor systems. • Fast Page Mode operation FEATURES • CAS-before-RAS refresh capability • Part Identification • RAS-only and Hidden refresh capability • Self-refresh capability (3.3V, L-ver only) - KM44C1000D/D-L(5V, 1K Ref.) - KM44V1000D/D-L(3.3V, 1K Ref.) • Fast parallel test mode capability • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early write or output enable controlled write • JEDEC Standard pinout • Active Power Dissipation Unit : mW • Available in 26(20)-pin SOJ 300mil and TSOP(II) 300mil packages Speed 3.3V 5V -5 - 470 • Single +5V±10% power supply(5V product) -6 220 415 • Single +3.3V±0.3V power supply(3.3V product) -7 200 360 FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles KM44C1000D Refresh cycle Normal Refresh Period L-ver 1K 16ms 128ms RAS CAS W KM44V1000D Control Clocks Refresh Timer Row Decoder Refresh Control • Performance Range Refresh Counter Speed tRAC tCAC tRC tPC Remark -5 50ns 15ns 90ns 35ns 5V only -6 60ns 15ns 110n 40ns 5V/3.3V -7 70ns 20ns 130n 45ns 5V/3.3V Memory Array 1,048,576 x4 Cells Row Address Buffer A0~A9 Col. Address Buffer Vcc Vss VBB Generator Column Decoder SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O Part NO. Data in Buffer DQ0 to DQ3 Data out Buffer OE KM44C1000D, KM44V1000D CMOS DRAM PIN CONFIGURATION (Top Views) •KM44C/V1000DT •KM44C/V1000DJ DQ0 DQ1 W RAS A9 1 2 3 4 5 20 19 18 17 16 VSS DQ3 DQ2 CAS OE DQ0 DQ1 W RAS A9 1 2 3 4 5 20 19 18 17 16 VSS DQ3 DQ2 CAS OE A0 A1 A2 A3 VCC 6 7 8 9 10 15 14 13 12 11 A8 A7 A6 A5 A4 A0 A1 A2 A3 VCC 6 7 8 9 10 15 14 13 12 11 A8 A7 A6 A5 A4 ( SOJ ) ( TSOP-II ) Pin Name Pin function A0 - A9 Address Inputs DQ0 - 3 Data In/out VSS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5V) Power(+3.3V) KM44C1000D, KM44V1000D CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Units 3.3V 5V VIN, VOUT -0.5 to +4.6 -1 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation PD 600 600 mW Short Circuit Output Current IOS 50 50 mA Voltage on any pin relative to VSS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter 3.3V Symbol 5V Units Min Typ Max Min Typ Max Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*1 2.4 - VCC+1.0*1 V Input Low Voltage VIL -0.3*2 - 0.8 -0.1*2 - 0.8 V *1 : VCC +1.3V/15ns(3.3V), VCC +2.0V/20ns(5V), Pulse width is measured at VCC *2 : - 1.3V/15ns(3.3V), - 2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter 3.3V 5V Symbol Min Max Units Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V Input Leakage Current (Any input 0≤VIN≤VCC+0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V KM44C1000D, KM44V1000D CMOS DRAM DC AND OPERATING CHARACTERISTICS (Recommend operating conditions unless otherwise noted.) Symbol Power Max Speed Units KM44V1000D KM44C1000D ICC1 Don′t Care -5 -6 -7 60 55 85 75 65 mA mA mA ICC2 Don′t Care Don′t Care 1 2 mA ICC3 Don′t Care -5 -6 -7 60 55 85 75 65 mA mA mA ICC4 Don′t Care -5 -6 -7 45 40 65 55 45 mA mA mA ICC5 Normal L Don′t Care 0.5 100 1 200 mA uA ICC6 Don′t Care -5 -6 -7 60 55 85 75 65 mA mA mA ICC7 L Don′t Care 200 300 uA ICCS L Don′t Care 150 - uA ICC1 * : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 * : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.) ICC4 * : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Don′t Care, TRC=125us(L-ver.), TRAS =TRAS min~300ns ICCS : Self refresh current RAS=CAS=VIL, W=OE =A0 ~ A9=VCC- 0.2V or 0.2V DQ0 ~ DQ3=VCC- 0.2V, 0.2V or OPEN *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one fast page mode cycle time, tPC. KM44C1000D, KM44V1000D CMOS DRAM CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A9] CIN1 - 5 pF Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ3] CDQ - 7 pF AC CHARACTERISTICS (0°C≤T≤70°C, See note 1,2) Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter -6 -5*1 Symbol Min Random read or write cycle time tRC 90 Read-modify-write cycle time tRWC 132 Max Min 7 Max 110 Min Units 130 152 Notes Max ns 177 ns tRAC 50 60 70 ns 3,4,10 Access time from CAS tCAC 15 15 20 ns 3,4,5 Access time from column address tAA 25 30 35 ns 3,10 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay tOFF 0 12 0 12 0 17 ns 6 Transition time (rise and fall) tT 3 50 3 50 3 50 ns 2 RAS precharge time tRP 30 RAS pulse width tRAS 50 RAS hold time tRSH 15 CAS hold time Access time from RAS 0 0 40 10K 60 50 10K 15 70 ns 10K 20 ns ns tCSH 50 CAS pulse width tCAS 15 10K 15 10K 20 10K ns RAS to CAS delay time tRCD 20 35 20 45 20 50 ns 4 RAS to column address delay time tRAD 15 25 15 30 15 35 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 10 10 10 ns Column address set-up time tASC 0 0 0 ns Column address hold time tCAH 10 10 15 ns Column address to RAS lead time tRAL 25 30 35 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns Read command hold time referenced to RAS tRRH 0 0 0 ns Write command hold time tWCH 10 10 15 ns Write command pulse width tWP 10 10 15 ns Write command to RAS lead time tRWL 15 15 15 ns Write command to CAS lead time tCWL 13 15 15 ns Note) *1 : 5V only 60 70 ns 8 KM44C1000D, KM44V1000D CMOS DRAM AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2) Parameter -6 -5*1 Symbol Min Max Min -7 Max Min Units Notes Max Data set-up time tDS 0 0 0 ns 9 Data hold time tDH 10 10 15 ns 9 Refresh period (Normal) tREF 16 16 16 ms Refresh period (L-ver) tREF 128 128 128 ms Write command set-up time tWCS 0 0 0 ns 7 CAS to W delay time tCWD 37 37 47 ns 7 RAS to W delay time tRWD 72 82 97 ns 7 Column address to W delay time tAWD 47 52 62 ns 7 CAS precharge to W delay time tCPWD 52 57 67 ns 7 CAS set-up time (CAS-before-RAS refresh) tCSR 10 10 10 ns CAS hold time (CAS-before-RAS refresh) tCHR 10 10 15 ns RAS to CAS precharge time tRPC 5 5 5 ns CAS precharge time (C-B-R counter test cycle) tCPT 20 20 25 ns Access time from CAS precharge tCPA Fast Page mode cycle time tPC 35 40 45 ns Fast Page read-modify-write cycle time tPRWC 77 82 97 ns CAS precharge time (Fast Page cycle) tCP 10 RAS pulse width (Fast Page cycle) tRASP 50 RAS hold time from CAS precharge tRHCP 30 OE access time tOEA OE to data delay tOED Out put buffer turn off delay time from OE 30 35 10 200K 60 10 200K 35 15 12 40 70 12 3 ns 200K 40 15 ns ns ns 20 17 ns ns tOEZ 0 OE command hold time tOEH 15 15 20 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns Write command hold time (Test mode in) tWTH 10 10 10 ns W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 14,15,16 RAS precharge time (C-B-R self refresh) tRPS 90 110 130 ns 14,15,16 CAS Hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 14,15,16 Note) *1 : 5V only 12 0 12 0 17 ns 6 KM44C1000D, KM44V1000D CMOS DRAM TEST MODE CYCLE Parameter ( Note 11 ) -6 -5*1 Symbol Min Max Min -7 Max Min Units Notes Max Random read or write cycle time tRC 95 115 135 ns Read-modify-write cycle time tRWC 138 160 190 ns Access time from RAS tRAC 55 65 75 ns 3,4,10 Access time from CAS tCAC 18 20 25 ns 3,4,5 Access time from column address tAA 30 35 40 ns 3,10 RAS pulse width tRAS 55 10K 65 10K 75 10K ns CAS pulse width tCAS 18 10K 20 10K 25 10K ns RAS hold time tRSH 18 20 25 ns CAS hold time tCSH 55 65 75 ns Column Address to RAS lead time tRAL 30 35 40 ns CAS to W delay time tCWD 41 45 55 ns 7 RAS to W delay time tRWD 78 90 105 ns 7 Column Address to W delay time tAWD 53 60 70 ns 7 Fast Page mode cycle time tPC 40 45 50 ns Fast Page mode read-modify-write cycle tPRWC 81 90 105 ns RAS pulse width (Fast Page cycle) tRASP 55 Access time from CAS precharge tCPA OE access time tOEA OE to data delay tOED 18 20 25 ns OE command hold time tOEH 18 20 25 ns Note) *1 : 5V only 200K 65 35 200K 75 40 20 20 200K ns 45 ns 25 ns 3 KM44C1000D, KM44V1000D CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. These specifiecations are applied in the test mode. 12. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tOFF(MAX) defines the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 14. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 15. For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within 16ms before and after self refresh, in order to meet refresh specification. 16. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM44C1000D, KM44V1000D CMOS DRAM READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEZ tOEA VIL - tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE tWCH VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS VIL - tRSH tCAS VIH VIL - tCRP tRAD tASR A tRCD VIH - tRAH tRAL tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tOED tOEH tDS tDH DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM READ - MODIFY - WRTIE CYCLE tRWC tRP tRAS RAS VIH VIL - tCRP CAS tRCD tRSH tCAS VIH VIL - tASR tRAD tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC DQ0 ~ DQ3(7) VI/OH VI/OL - tAA tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM FAST PAGE READ CYCLE tRP tRASP RAS VIH - tRHCP VIL - ¡ó tCRP CAS tRCD VIH - tRAD tASC VIL - VIH VIL - tCSH tRAH tCAH ROW ADDR tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRCH tRCS VIH - tASC ¡ó tCAH COLUMN ADDRESS ¡ó tRAL tRCS ¡ó tRRH tRCH VIL - tCAC tOEA tCAC tOEA OE tRSH tCAS ¡ó tRCS W tCP tCAS tCAS tASR A tPC tCP VIH - ¡ó VIL - ¡ó tAA DQ0 ~ DQ3(7) VOH VOL - tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tCAC tOEA tAA tOFF tCLZ tOFF tOEZ VALID DATA-OUT Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS tRHCP VIH VIL - ¡ó tPC tCRP CAS tRAD tASC VIL - VIL - tRAL tCSH tCAH tRAH tASC COLUMN ADDRESS ROW ADDR VIH - tWCH tCAH tASC ¡ó COLUMN ADDRESS tWCS ¡ó tWCH tCAH COLUMN ADDRESS tWCS tWCH ¡ó tWP tWP tWP VIL - tCWL OE tRSH tCAS ¡ó tWCS W tCP tCAS tCAS tASR A tRCD VIH - VIH - tPC tCP ¡ó VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tCWL tRWL tCWL ¡ó tDS tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM FAST PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tRSH tRCD CAS tCP VIH - tCRP tCAS tCAS VIL - tRAD tPRWC tRAH tASR A VIH VIL - ROW ADDR tCAH tASC COL. ADDR COL. ADDR tRWL tRCS W tRAL tCAH tASC tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD OE tAWD tCPWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA DQ0 ~ DQ3(7) VI/OH VI/OL - tRAC tOEZ tDH tDH tAA tDS tCLZ tOED tDS tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - DQ0 ~ DQ3(7) VOH - tOFF OPEN VOL Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CAS tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRAL tRCS W VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRC tRP tRAS VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRAL tWRH tWRP W OE VIH - tWCS tWCH tWP VIL - VIH VIL - tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP VIH - RAS tRAS VIL VIH - CAS tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC VIH - A VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH - W VIL - OE VIH VIL - tOEA tCLZ VOH - DQ0 ~ DQ3(7) tCAH COLUMN ADDRESS tOEZ DATA-OUT VOL - WRITE CYCLE W tOFF tWRP tRWL tWRH tCWL tWCS VIH - tWCH VIL - tWP OE VIH VIL - tDS DQ0 ~ DQ3(7) tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ0 ~ DQ3(7) tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CAS tCHS VIH - tCSR VIL - DQ0 ~ DQ3(7) VOH - tOFF OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined KM44C1000D, KM44V1000D CMOS DRAM PACKAGE DIMENSION 26(20) SOJ 300mil Units : Inches (millimeters) 0.280 (7.11) 0.260 (6.61) 0.330 (8.39) 0.340 (8.63) 0.300 (7.62) #26(20) 0.006 (0.15) 0.012 (0.30) 0.148 (3.76) MAX 0.027 (0.69) MIN 0.691 (17.55) MAX 0.670 (17.03) 0.680 (17.27) 0.0375 (0.95) 0.050 (1.27) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 26(20) TSOP(II) 300mil 0.300 (7.62) 0.355 (9.02) 0.371 (9.42) Units : Inches (millimeters) 0.004 (0.10) 0.010 (0.25) 0.691 (17.54) MAX 0.671 (17.04) 0.679 (17.24) 0.037 (0.95) 0.050 (1.27) 0.047 (1.20) MAX 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O