KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. FEATURES ¡Ü Part Identification - KM48C2000B/B-L (5V, 4K Ref.) - KM48C2100B/B-L (5V, 2K Ref.) - KM48V2000B/B-L (3.3V, 4K Ref.) - KM48V2100B/B-L (3.3V, 2K Ref.) ¡Ü ¡Ü Fast Page Mode operation ¡Ü Byte/Word Read/Write operation ¡Ü CAS-before-RAS refresh capability ¡Ü RAS-only and Hidden refresh capability ¡Ü Self-refresh capability (L-ver only) ¡Ü Fast parallel test mode capability ¡Ü TTL(5V)/LVTTL(3.3V) compatible inputs and outputs ¡Ü Early Write or output enable controlled write ¡Ü JEDEC Standard pinout ¡Ü Available in Plastic SOJ and TSOP(II) packages ¡Ü Single +5V¡¾10% power supply (5V product) ¡Ü Single +3.3V¡¾0.3V power supply (3.3V product) Active Power Dissipation Unit : mW 3.3V Speed 4K -5 5V 2K 324 4K 396 495 2K 605 -6 288 360 440 550 -7 252 324 385 495 FUNCTIONAL BLOCK DIAGRAM Refresh Cycles Part NO. VCC C2000B 5V V2000B 3.3V C2100B 5V V2100B 3.3V Refresh cycle Refresh period Normal 4K 64ms L-ver RAS CAS W Refresh Timer 32ms Performance Range Speed tRAC tCAC tRC tPC Remark -5 50ns 13ns 90ns 35ns 5V/3.3V -6 60ns 15ns 110ns 40ns 5V/3.3V -7 70ns 20ns 130ns 45ns 5V/3.3V A0-A11 (A0 - A10)*1 A0 - A8 (A0 - A9)*1 Memory Array 2,097,152 x 8 Cells Row Address Buffer Col. Address Buffer Buffer Row Decoder Refresh Control Refresh Counter ¡Ü Vcc Vss VBB Generator Data in 128ms 2K Control Clocks Column Decoder Note) *1 : 2K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Sense Amps & I/O ¡Ü DQ0 to DQ7 Data out Buffer OE KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM PIN CONFIGURATION (Top Views) KM48C/V20(1)00BK ¡Ü VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC 1 ¡Û 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ¡Ü VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS KM48C/V20(1)00BS VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC 1 ¡Û 2 3 4 5 6 7 8 9 10 11 12 13 14 *A11 is N.C for KM48C/V2100B(5V/3.3V, 2K Ref. product) K : 300mil 28 SOJ S : 300mil 28 TSOP II Pin Name Pin Function A0 - A11 Address Inputs (4K Product) A0 - A10 Address Inputs (2K Product) DQ0 - 7 Data In/Out VSS Ground RAS Row Address Strobe CAS Column Address Strobe W Read/Write Input OE Data Output Enable VCC Power(+5V) Power(+3.3V) N.C No Connection (2K Ref. product) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Units 3.3V 5V VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 ¡É Power Dissipation PD 1 1 W Short Circuit Output Current IOS 50 50 mA Voltage on any pin relative to VSS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70¡É) Parameter 3.3V Symbol 5V Units Min Typ Max Min Typ Max Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*1 2.4 - VCC+1.0*1 V Input Low Voltage VIL -0.3*2 - 0.8 -1.0*2 - 0.8 V *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max 3.3V 5V Parameter Symbol Min Max Units Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.3V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V¡ÂVOUT¡ÂVCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V¡ÂVOUT¡ÂVCC) IO(L) -5 5 uA Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Max Speed Units KM48V2000B KM48V2100B KM48C2000B KM48C2100B ICC1 Don't care -5 -6 -7 90 80 70 110 100 90 90 80 70 110 100 90 mA mA mA ICC2 Normal L Don't care 1 1 1 1 2 1 2 1 mA mA ICC3 Don't care -5 -6 -7 90 80 70 110 100 90 90 80 70 110 100 90 mA mA mA ICC4 Don't care -5 -6 -7 80 70 60 90 80 70 80 70 60 90 80 70 mA mA mA ICC5 Normal L Don't care 0.5 0.3 0.5 0.3 1 0.3 1 0.3 mA uA ICC6 Don't care -5 -6 -7 90 80 70 110 100 90 90 80 70 110 100 90 mA mA mA ICC7 L Don't care 450 400 450 400 uA ICCS L Don't care 250 250 300 300 uA ICC1* : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, Din=Don't care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=CAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open *Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC. KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM CAPACITANCE (TA=25¡É, VCC=5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A11] CIN1 - 5 pF Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ7] CDQ - 7 pF AC CHARACTERISTICS (0¡É¡Â TA¡Â70¡É, See note 1,2) Test condition (5V device) : VCC=5.0V¡¾10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (3.3V device) : VCC=3.3V¡¾0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V Parameter -5 Symbol Min -6 Max Min -7 Max Min Units Notes Max Random read or write cycle time tRC 90 110 130 ns Read-modify-write cycle time tRWC 133 155 185 ns Access time from RAS tRAC 50 60 70 ns 3,4,9 Access time from CAS tCAC 13 15 20 ns 3,4 Access time from column address tAA 25 30 35 ns 3,9 CAS to output in Low-Z tCLZ 0 ns 3 Output buffer turn-off delay tOFF 0 13 0 15 0 20 ns 5 Transition time (rise and fall) tT 3 50 3 50 3 50 ns 2 RAS precharge time tRP 30 RAS pulse width tRAS 50 RAS hold time tRSH 13 15 20 ns CAS hold time tCSH 50 60 70 ns CAS pulse width tCAS 13 10K 15 10K 20 10K ns RAS to CAS delay time tRCD 20 37 20 45 20 50 ns 4 RAS to column address delay time tRAD 15 25 15 30 15 35 ns 9 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 10 10 10 ns Column address set-up time tASC 0 0 0 ns Column address hold time tCAH 10 10 15 ns Column address to RAS lead time tRAL 25 30 35 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 7 Read command hold time referenced to RAS tRRH 0 0 0 ns 7 Write command hold time tWCH 10 10 15 ns Write command pulse width tWP 10 10 15 ns Write command to RAS lead time tRWL 13 15 20 ns Write command to CAS lead time tCWL 13 15 20 ns 0 0 40 10K 60 50 10K 70 ns 10K ns KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM AC CHARACTERISTICS (Continued) Parameter -5 Symbol Min -6 Max Min -7 Max Min Units Notes Max Data set-up time tDS 0 0 0 ns 8 Data hold time tDH 10 10 15 ns 8 Refresh period (2K, Normal) tREF Refresh period (4K, Normal) 32 32 32 ms tREF 64 64 64 ms Refresh period (L-ver) tREF 128 128 128 ms Write command set-up time tWCS 0 0 0 ns 6 CAS to W delay time tCWD 36 40 50 ns 6 RAS to W delay time tRWD 73 85 100 ns 6 Column address to W delay time tAWD 48 55 65 ns 6 CAS precharge to W delay time tCPWD 53 60 70 ns 6 CAS set-up time (CAS -before-RAS refresh) tCSR 5 5 5 ns CAS hlod time (CAS -before-RAS refresh) tCHR 10 10 15 ns RAS to CAS precharge time tRPC 5 5 5 ns CAS precharge time (CBR counter test tCPT 20 20 30 ns Access time from CAS precharge tCPA Fast Page mode cycle time Fast Page read-modify-write cycle time 30 35 40 ns tPC 35 40 45 ns tPRWC 76 85 100 ns CAS precharge time (Fast Page cycle) tCP 10 10 10 ns RAS pulse width (Fast Page cycle) tRASP 50 RAS hold time from CAS precharge tRHCP 30 OE access time tOEA 200K 60 200K 35 13 70 200K 40 15 3 ns ns 20 ns OE to data delay tOED 13 Output buffer turn off delay time from OE tOEZ 0 OE command hold time tOEH 13 15 20 ns Write command set-up time (Test mode in) tWTS 10 10 10 ns 10 Write command hold time (Test mode in) tWTH 10 10 10 ns 10 W to RAS precharge time(C-B-R refresh) 15 13 0 20 15 0 ns 20 ns 5 tWRP 10 10 10 ns W to RAS hold time(C-B-R refresh) tWRH 10 10 10 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 12 RAS precharge time (C-B-R self refresh) tRPS 90 110 130 ns 12 CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 12 KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM TEST MODE CYCLE Parameter ( Note 10, 11 ) -5 Symbol Min -6 Max Min -7 Max Min Units Notes Max Random read or write cycle time tRC 95 115 135 ns Read-modify-write cycle time tRWC 138 160 190 ns Access time from RAS tRAC 55 65 75 ms 3,4,9 Access time from CAS tCAC 18 20 25 ms 3,4 Access time from column address tAA 30 35 40 ms 3,9 RAS pulse width tRAS 55 10K 65 10K 75 10K ns CAS pulse width tCAS 18 10K 20 10K 25 10K ns RAS hold time tRSH 18 CAS hold time 20 25 ns tCSH 55 65 75 ns Column address to RAS lead time tRAL 30 35 40 ns CAS to W delay time tCWD 41 45 55 ns 6 RAS to W delay time tRWD 78 90 105 ns 6 Column address to W delay time tAWD 53 60 70 ns 6 CAS precharge to W delay timerefresh) tCPWD 58 65 75 ns 6 Fast Page mode cycle time tPC 40 45 50 ns Fast Page read-modify-write cycle time tPRWC 81 90 105 ns RAS pulse width (Fast Page cycle) tRASP 55 Access time from CAS precharge tCPA 35 OE access time tOEA 18 OE to data delay tOED 18 20 25 ns OE command hold time tOEH 18 20 25 ns 200K 65 200K 75 200K ns 40 45 ns 20 25 ns 3 KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CMOS DRAM NOTES 1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 6. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS¡ÃtWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD¡ÃtCWD(min), tRWD¡ÃtRWD(min), tAWD¡ÃtAWD(min) and tCPWD¡ÃtCPWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to the CAS falling edge in ealy write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 10. These specifications are applied in the test mode. 11. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet. 12. For all of the refresh modes except for distributed CAS -before- RAS refresh, 4096(4K Ref.)/2048(2K Ref.) cycles of burst refresh must be executed within 16ms before and after self-refresh in order to meet refresh specification.