PRELIMINARY KM681001B CMOS SRAM Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial and Industrial Temperature Range. Revision History Rev . No. History Draft Data Rev. 0.0 Initial release with Design Target. Feb. 1st, 1997 Design Target Rev. 1.0 Release to Preliminary Data Sheet. 1. Replace Design Target to Preliminary. Jun. 1st, 1997 Preliminary Rev. 2.0 Release to Final Data Sheet. 1. Delete Preliminary. 2. Delete 17ns, L-version and Industrial Temperature Part. 3. Delete Voh1=3.95V. 4. Delete Data Retention Characteristics and Wave form. 5. Relex operating current Speed Previous Now 15ns 130mA 125mA 17ns 120mA 20ns 110mA 123mA Feb. 6th. 1998 Final Remark The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM 128K x 8 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating KM681001B - 15 : 125mA(Max.) KM681001B - 20 : 123mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Standard Pin Configuration KM681001BJ : 32-SOJ-400 KM681001BSJ : 32-SOJ-300 The KM681001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681001B is packaged in a 400/300 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 Row Select Clk Gen. Pre-Charge Circuit Memory Array 512 Rows 256x8 Columns A8 I/O1 ~ I/O8 Data Cont. N.C 1 32 Vcc A0 2 31 A16 A1 3 30 CS2 A2 4 29 WE A3 5 28 A15 A4 6 27 A14 A5 7 26 A13 A6 8 A7 9 24 A8 10 23 A11 A9 11 22 CS1 A10 12 21 I/O8 I/O1 13 20 I/O7 I/O2 14 19 I/O6 I/O3 15 18 I/O5 Vss 17 I/O4 25 A12 SOJ 16 OE I/O Circuit Column Select CLK Gen. PIN FUNCTION A9 A10 A11 A12 A13 A14 A15 A16 Pin Name CS2 CS1 WE A0 - A16 WE CS1, CS2 OE OE I/O1 ~ I/O8 -2- Pin Function Address Inputs Write Enable Chip Selects Output Enable Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Rating Unit VIN, VOUT -0.5 to 7.0 V Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V Power Dissipation PD 1.0 W TSTG -65 to 150 °C TA 0 to 70 °C Voltage on Any Pin Relative to VSS Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC+0.5** V Input Low Voltage VIL -0.5* - 0.8 V NOTE: * VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Min Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VOUT = VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS1=VIL, CS2=VIH, VIN=VIH or VIL, IOUT=0mA 15ns - 125 mA 20ns - 123 Parameter Symbol Test Conditions ISB Min. Cycle, CS1=VIH or CS2=VIL - 20 ISB1 f=0MHz, CS1≥VCC-0.2V or CS2≤0.2V, VIN≥VCC-0.2V or VIN≤0.2V - 5 Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V Standby Current mA CAPACITANCE*(TA=25°C, f=1.0MHz) Item Symbol Test Conditions MIN Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V +5.0V 480Ω 480Ω DOUT 255Ω DOUT 255Ω 30pF* 5pF* * Including Scope and Jig Capacitance READ CYCLE Parameter Symbol KM681001B-15 KM681001B-20 Min Max Min Max Unit Read Cycle Time tRC 15 - 20 - ns Address Access Time tAA - 15 - 20 ns Chip Select to Output tCO* - 15 - 20 ns Output Enable to Valid Output tOE - 8 - 10 ns Chip Enable to Low-Z Output tLZ* 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - ns Chip Disable to High-Z Output tHZ* 0 6 0 8 ns Output Disable to High-Z Output tOHZ 0 6 0 8 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 15 - 20 ns NOTE : tCO =tCO1, tCO2 / tLZ=tLZ1, tLZ2 / tHZ=tHZ1, tHZ2 -4- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM WRITE CYCLE Parameter Symbol KM681001B-15 KM681001B-20 Min Max Min Max Unit Write Cycle Time tWC 15 - 20 - ns Chip Select to End of Write tCW 10 - 12 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 10 - 12 - ns Write Pulse Width(OE High) tWP 10 - 12 - ns Write Pulse Width(OE Low) tWP1 15 - 20 - ns Write Recovery Time tWR* 0 - 0 - ns Write to Output High-Z tWHZ 0 8 0 10 ns Data to Write Time Overlap tDW 7 - 9 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - ns NOTE : tWR = tWR1, tWR2 TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tOH Data Out tAA Valid Data Previous Valid Data -5- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tHZ(3,4,5) CS1 tCO CS2 tOHZ tOE OE tOH tOLZ tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS1=VIL and CS2=VIH. 7. Address valid prior to coincident with CS1 transition low and CS2 transition high. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS1 CS2 tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out -6- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS1 CS2 tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 = Controlled) tWC Address tAW tWR(5) tCW(3) CS1 tAS(4) CS2 tWP(2) WE tDW Data in High-Z Valid Data tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z -7- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(4) (CS2 = Controlled) tWC Address tAW tWR(5) tCW(3) CS1 tAS(4) CS2 tWP(2) WE tDH tDW Data in Valid Data tLZ tWHZ(6) High-Z Data out High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition CS1 going low, CS2 going high and WE going low ; A write ends at the earliest transition CS1 going high or CS2 going low or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS1 going low or CS2 going high to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high. tWR2 applied in case a write ends as CS2 going low. 6. If OE, CS1 , CS2 and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS1 goes low and CS2 goes high simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS1 is low and CS2 is high : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS1 CS2 WE OE Mode I/O Pin Supply Current H X X X* Not Select High-Z ISB, ISB1 X L X X Not Select High-Z ISB, ISB1 L H H H Output Disable High-Z ICC L H H L Read DOUT ICC L H L X Write DIN ICC * NOTE : X means Don′t Care. -8- Rev 2.0 February 1998 PRELIMINARY KM681001B CMOS SRAM PACKAGE DIMENSIONS Units:millimeters/Inches 32-SOJ-300 #17 7.62 0.300 #32 8.64 ±0.12 0.340 ±0.005 6.86 ±0.25 0.270 ±0.010 0.20 #1 +0.10 -0.05 0.008 +0.004 -0.002 #16 0.69 MIN 0.027 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 1.14 ) 0.045 1.32 ( ) 0.052 ( ( 0.43 0.95 ) 0.0375 +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 0.71 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 0.028+0.004 -0.002 32-SOJ-400 Units:millimeters/Inches #32 10.16 0.400 #17 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 0.69 0.027 MIN 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 ( 0.95 ) 0.0375 0.43 +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 +0.10 -0.05 0.008 +0.004 -0.002 #16 0.71 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 0.028 +0.004 -0.002 -9- Rev 2.0 February 1998