KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN, VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +125 18 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min Typ Max Unit VCC VSS VIH VIL 3.0 0 2.0 3.3 0 - 3.6 0 V V V V -0.3*2 VCC+0.3*1 0.8 *1 : VCC+1.3V/15ns, Pulse width is measured at VCC. *2 : -1.3V/15ns, Pulse width is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed ICC1 KMM372F400CK/CS KMM372F410CK/CS Unit Min Max Min Max -5 -6 - 1620 1440 - 1980 1800 mA mA ICC2 Don′t care - 100 - 100 mA ICC3 -5 -6 - 1620 1440 - 1980 1800 mA mA ICC4 -5 -6 - 1440 1260 - 1620 1440 mA mA ICC5 Don′t care - 30 - 30 mA ICC6 -5 -6 - 1620 1440 - 1980 1800 mA mA II(L) IO(L) Don′t care -45 -5 45 5 -45 -5 45 5 uA uA VOH VOL Don′t care 2.4 - 0.4 2.4 - 0.4 V V ICC1 * : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 * : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 * : EDO Mode Current * (RAS=VIL, CAS cycling : tHPC =min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6 * : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) II(L) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.3V, all other pins not under test=0 V) IO(L) : Output Leakage Current(Data Out is disabled, 0V≤VOUT ≤Vcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3 , address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one hyper page mode cycle,tHPC. KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE CAPACITANCE (TA = 25°C, Vcc=3.3V, f = 1MHz) Item Symbol Min Max Unit Input capacitance[A0-A11(A10), B0] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] CIN1 CIN2 CIN3 CIN4 CDQ1 - 20 20 80 20 20 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter -5 Symbol Min Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z OE to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period(4K Ref.) Refresh period(2K Ref.) Write command set-up time CAS to W dealy time tRC tRWC tRAC tCAC tAA tCLZ tOLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tREF tWCS tCWD -6 Max 90 Min Unit 110 131 Note Max ns 155 ns 50 60 ns 3,4,10 18 20 ns 3,4,5,14 35 ns 3,10,14 8 30 8 ns 3,14 8 8 ns 3,14 8 18 8 20 ns 6,11,12,14 2 50 2 50 ns 2 30 50 40 10K 18 60 ns 10K 20 36 43 ns ns 14 ns 14 8 10K 10 10K ns 13 18 32 18 40 ns 4,14 13 20 13 25 ns 10,14 10 10 ns 14 5 5 ns 14 8 8 ns 14 0 0 ns 8 10 ns 30 35 ns 0 0 ns 14 0 0 ns 8 -2 -2 ns 8,14 10 10 ns 10 10 ns 18 20 ns 8 10 ns 14 -2 -2 ns 9,14 13 15 ns 9,14 64 32 64 ms 32 ms 0 0 ns 7 36 40 ns 7 KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter -5 Symbol Min RAS to W dealy time Column address to W delay time CAS precharge time to W delay time CAS set-up time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time CAS precharge time (C-B-R counter test cycle) Access time from CAS precharge Hyper page cycle time Hyper page read-modify-write cycle time CAS precharge time(Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay time from RAS Output buffer turn off delay time from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width(Hyper page cycle) tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE -6 Max Min Unit Note Max 71 83 ns 7,14 48 55 ns 7 53 60 ns 5 5 ns 14 8 8 ns 14 3 3 ns 14 20 20 33 25 ns 40 30 ns 3,14 ns 12 12 68 77 ns 8 10 ns 50 200K 35 60 40 18 18 5 200K ns 14 20 ns 14 ns 14 20 ns 6,11,14 20 18 5 ns 13 15 ns 15 15 ns 14 8 8 ns 14 10 10 ns 14 3 13 3 15 ns 6.11.12 3 18 3 20 ns 6.11.14 14 20 20 ns 5 5 ns 5 5 ns 5 5 ns 5 5 ns Present Detect Read Cycle PDE to Valid PD bit PDE to PD bit Inactive tPD tPDOFF 10 2 7 2 10 ns 7 ns KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1TTL loads and 100pF. Voh=2.0V and Vol=0.8V. If tCWD ≥tCWD (min), tRWD ≥tRWD (min) and tAWD ≥tAWD (min), then the cycle is a read-write cycle and the data output will contain data read from the selected address. If neither of the above conditions are satisfied, the condition of the data out is indeterminated. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 5. Assumes that tRCD ≥tRCD (max). 11. tCEZ (max), tREZ (max), tWEZ (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS , tRWD , tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 12. If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes to high before RAS high going , the open circuit condition of the output is achieved by RAS high going. 13. tASC ≥tCP min 14. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE READ CYCLE tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tCRP tRSH VIH - tCAS VIL - tRAD tASR A VIH VIL - tRAH tRAL tASC tCAH ROW ADDRESS COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tWEZ tCEZ tAA OE VIH - tOEZ tOEA VIL - tOLZ tRAC DQ VOH VOL - OPEN tCAC tCLZ tREZ DATA-OUT Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRSH VIH VIL - tCRP tCAS VIL - tRAD tASR A tRCD VIH - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W OE VIH VIL - VIH VIL - tDS DQ tWCH tWP VIH VIL - tDH DATA-IN Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS VIL - tCSH tCRP CAS tRP VIH - tRCD tRSH tCAS VIH - tCRP VIL - tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL W OE tWP VIH VIL - VIH VIL - tOED tDS DQ VIH - tOEH tDH DATA-IN VIL - Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE READ - MODIFY - WRITE CYCLE tRAS RAS tRWC VIL - tCRP tRCD tRSH VIH - CAS tRP VIH - tCAS VIL - tRAD tASR tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tRWL tCWD W tCWL VIH - tWP VIL - tRWD OE tOEA VIH VIL - tOLZ tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE HYPER PAGE READ CYCLE tRP tRASP RAS VIH VIL - ¡ó tCSH tCRP CAS VIL - VIL - tHPC tCP tCAS tHPC tCP tCAS tCP tCAS tCAS tRAD tASR A tRCD VIH - VIH - tRHCP tHPC tRAH tASC ROW ADDR tCAH tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tASC tCAH COLUMN ADDR tASC tCAH tREZ COLUMN ADDRESS tRRH tRCS W tRCH VIH VIL - tCAC tAA tCPA tCAC tAA OE VIH - tCAC tAA tCPA tOCH tOEA tCHO tOEP tOEA VIL - tOEP tCAC tDOH tRAC DQ tCPA tCAC tAA VOH VOL - VALID DATA-OUT tOLZ tCLZ tOEZ tOEA tOEZ tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tHPC tCRP CAS tRCD tHPC tCP VIH - tCAS VIL - tRSH tCP tCAS tCAS tRAD ¡ó tCSH tASR A VIH VIL - tRAH tASC tCAH VIH - ROW ADDR. COLUMN ADDRESS tWCH COLUMN ADDRESS tWCS tWP tCAH ¡ó COLUMN ADDRESS tWCS ¡ó tWCH tWP VIL - tCWL VIL - VIH VIL - tCWL tRWL ¡ó VIH - ¡ó tDS DQ tASC tWCH tWP tCWL OE tCAH ¡ó tWCS W tASC tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE RAS tCSH tHPRWC tRCD tCAS VIL - VIH VIL - tCAS tRAD tRAH ROW ADDR tCAH tASC tCAH tASC COL. ADDR tRWL tCWL tCWL VIH - tWP VIL - tWP tCWD tCWD tAWD tRWD OE tRAL COL. ADDR tRCS W tCRP tCP VIH - tASR A tRSH VIL - tCRP CAS tRP tRASP VIH - VIH - tAWD tCPWD tOEA tOEA VIL - tOED tOED tCAC tAA tDH tOEZ tCAC tAA tDS tDH tOEZ tDS tRAC DQ VI/OH VI/OL - tCLZ tCLZ tOLZ VALID DATA-OUT VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE tRP tRASP RAS VIH - READ(tCAC ) READ(tCPA ) tHPC tHPC tCP tCP CAS VIH VIL - VIH VIL - tCAS tRAD tASR A tRAH tASC ROW ADDR tCAH COLUMN ADDRESS tRCS W READ(tAA) WRITE VIL - tCAS tCAH tASC COLUMN ADDRESS tRCH COL. ADDR tRCS tCAS tCAS tCAH tASC tHPC tCP tRCH tASC tCAH COL. ADDR tWCH tRCH tWCS VIH VIL - tWPE tCLZ tWED tCPA OE VIH VIL - tOEA tCAC tAA DQ VI/OH VI/OL - tWEZ tDH tWEZ tDS VALID VALID DATA-IN tREZ tAA tRAC VALID DATA-OUT DATA-OUT VALID DATA-OUT Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRC tRP RAS VIH VIL - tRPC tCP CAS tRAS VIH - tRPC tCSR tCHR VIL - tWRP W tRP tWRH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) tRC RAS tRAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCS W tRRH tWRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tCEZ tOLZ tCAC tREZ tWEZ tCLZ tRAC DQ VOH VOL - OPEN tOEZ DATA-OUT Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIH - tRP tRAS VIL - tCRP CAS tRC tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRP tWCS W OE VIH - tWCH tWP VIL - VIH VIL - tDS DQ tWRH VIH VIL - tDH DATA-IN Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP RAS CAS VIH - tRAS VIL VIH - tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC A VIH VIL - READ CYCLE W OE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH VIL VIH VIL - tOEA tCLZ VOH - DQ tCAH COLUMN ADDRESS tOEZ DATA-OUT VOL - WRITE CYCLE W tCEZ tREZ tWRP tRWL tWRH VIH - tCWL tWCS tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. Don′t care Undefined tWEZ KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS VIL - tRPS tRPC tRPC tCP VIH - CAS tRASS VIH - tCHS tCSR VIL - tCEZ VOH - DQ OPEN VOL - VIH - W VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRC tRP RAS tRP tRAS VIH VIL - tRPC tRPC tCP CAS tCSR VIH - tWTS W tCHR VIL - tWTH VIH VIL - tCEZ DQ VOH VOL - OPEN Don′t care Undefined KMM372F400CK/CS KMM372F410CK/CS DRAM MODULE PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) R 0.079 (R 2.000) 0.700 (17.780) 0.157±0.004 (4.000±0.100) 0.118 (3.000) B A .118DIA±.004 (3.000DIA±.100) 0.250 (6.350) 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.100Min (2.540Min) 1.000 (25.40) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) .150Max (3.81Max) TSOP .350Max (8.89Max) SOJ 0.200 Min (5.08 Min) ( Front view ) 0.050±0.0039 (1.270±0.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123±.005 (3.125±.125) 0.079±.004 (2.000±.100) Detail A 0.123±.005 (3.125±.125) 0.079±.004 (2.000±.100) Detail B Tolerances : ±.005(.13) unless otherwise specified The used device is 4Mx4 DRAM with Fast Page mode, SOJ or TSOP II. (Forward) DRAM Part No. : KMM372F400CK/CS - KM44V4004CK and KM44V4004CS. : KMM372F410CK/CS - KM44V4104CK and KM44V4104CS. Revision History Rev 0.0 : Aug. 1997 (2.540 Min) ( Back view ) 0.039±.002 (1.000±.050) 0.010Max (0.250 Max) 0.050 (1.270) Detail C