KMM372V404BS DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN, VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +125 6 50 V V °C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70°C) Item Symbol Min Typ Max Unit VCC VSS VIH VIL 3.0 0 2.0 3.3 0 - 3.6 0 V V V V Supply Voltage Ground Input High Voltage Input Low Voltage -0.3*2 VCC+0.3*1 0.8 *1 : VCC+1.3V at pulse width≤15ns, which is measured at VCC. *2 : -1.3V at pulse width≤15ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) KMM372V404BS Symbol Speed ICC1 Unit Min Max -5 -6 - 660 600 mA mA ICC2 Don′t care - 100 mA ICC3 -5 -6 - 660 600 mA mA ICC4 -5 -6 - 440 380 mA mA ICC5 Don′t care - 30 mA ICC6 -5 -6 - 660 600 mA mA II(L) IO(L) Don′'t care -10 -5 10 5 uA uA VOH VOL Don′t care 2.4 - 0.4 V V ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4* : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0≤VIN≤Vcc+0.3V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0V≤VOUT≤Vcc) VOH : Output High Voltage Level (IOH = -2mA) VOL : Output Low Voltage Level (IOL = 2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Fast Page mode cycle time, tPC. KMM372V404BS DRAM MODULE CAPACITANCE (TA = 25°C, f = 1MHz) Item Symbol Min Max Unit Input capacitance[A0, B0, A1 - A11] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0, CAS4] Input/Output capacitance[DQ0 - 71] CIN1 CIN2 CIN3 CIN4 CDQ - 20 20 31 20 17 pF pF pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referencde to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data in set-up time Data in hold time Refresh period Write command set-up time CAS to W delay time Column address to W delay time CAS prechange to W delay time Symbol tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tAWD tCPWD -5 Min -6 Max 90 Max 110 133 Unit Note ns 155 ns 50 60 ns 3,4,10 18 20 ns 3,4,5,11 30 35 ns 3,10,11 5 5 5 18 1 50 30 50 Min ns 3,11 5 20 ns 6,11 1 50 ns 2 40 10K 60 ns 10K ns 18 20 ns 11 48 58 ns 11 13 10K 15 10K ns 18 32 18 40 ns 4,11 13 20 13 25 ns 10,11 10 10 ns 11 5 5 ns 11 8 8 ns 11 0 0 ns 12 10 10 ns 12 30 35 ns 11 0 0 ns 0 0 ns 8 -2 -2 ns 8,11 10 10 ns 10 10 ns 20 20 ns 13 15 ns 15 -2 -2 ns 9,11 ns 9,11 15 15 64 64 11 ms 0 0 ns 7 36 40 ns 7,14 48 55 ns 7 53 60 ns 7 KMM372V404BS DRAM MODULE AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=3.3V±0.3V. See notes 1,2.) Parameter RAS ro W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast page mode cycle time Fast page mode read-modify-write cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Symbol tRWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH -5 Min -6 Max Min Max Unit 71 83 ns 7,11 10 10 ns 11,16 8 8 ns 11 3 3 35 40 ns 11 ns 3,11 35 40 ns 76 85 ns 10 50 10 200K 60 ns 200K PDE to PD bit Inactive tPD tPDOFF 13 ns 35 40 ns 11 15 15 ns 11 8 8 18 18 5 20 20 18 13 5 20 15 ns 11 ns 11 ns 11 ns 11 ns Present Detect Read Cycle PDE to Valid PD bit Note 10 2 7 2 10 ns 7 ns DRAM MODULE KMM372V404BS NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. 12. tASC, tCAH are referenced to the earlier CAS falling edge. 5. Assumes tha tRCD≥tRCD(max). 13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 14. tCWD is referenced to the later CAS falling edge at word readmodify-write cycle. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWD≥tRWD(min), tCWD≥tCWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 15. tCWL is specified from W falling edge to the earlier CAS rising edge. 16. tCSR is referenced to earlier CAS falling low before RAS transition low. KMM372V404BS DRAM MODULE READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEZ tOEA VIL - tCAC DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KMM372V404BS DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE tWP VIL - VIH VIL - tDS DQ tWCH VIH - VIH VIL - tDH DATA-IN Don′t care Undefined KMM372V404BS DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRP tRAS RAS VIH VIL - tCSH tCRP CAS VIL - tRSH tCAS VIH VIL - tCRP tRAD tASR A tRCD VIH - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - tOED tOEH tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined KMM372V404BS DRAM MODULE READ - MODIFY - WRTIE CYCLE tRWC tRP tRAS VIH - RAS VIL - tCRP tRCD tRSH tCAS VIH - CAS VIL - tASR tRAD tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KMM372V404BS DRAM MODULE FAST PAGE READ CYCLE NOTE : DOUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - ¡ó tCRP CAS VIH - VIH VIL - tCP tCAS tCAS tRAD tASC VIL - tASR A tPC tCP tRCD tRSH tCAS ¡ó tCSH tRAH tCAH ROW ADDR tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tASC ¡ó tCAH COLUMN ADDRESS ¡ó tRRH tRCS W tRCH tRCS VIH - tCAC tOEA VIH - ¡ó VIL - ¡ó tAA DQ ¡ó tRCH VIL - tCAC tOEA OE tRCS VOH VOL - tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tCAC tOEA tAA tOFF tCLZ tOFF tOEZ VALID DATA-OUT Don′t care Undefined KMM372V404BS DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS tRHCP VIH VIL - ¡ó tPC tCRP CAS VIH - VIH VIL - tCAS tCSH tCAH tRAH ROW ADDR tASC COLUMN ADDRESS tWCH tCAH tASC ¡ó tWCS ¡ó tWCH tCAH COLUMN ADDRESS tWCS tWCH ¡ó VIH - tWP tWP tWP VIL - ¡ó VIL - VIH VIL - tCWL tRWL tCWL VIH - ¡ó tDS DQ tCAS COLUMN ADDRESS tCWL OE tRSH ¡ó tWCS W tCP tCAS tRAD tASC VIL - tASR A tPC tCP tRCD tDH tDS tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KMM372V404BS DRAM MODULE FAST PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tRSH tRCD CAS tCP VIH - tCRP tCAS tCAS VIL - tRAD tPRWC tRAH tASR A VIH VIL - ROW ADDR tCAH tASC COL. ADDR COL. ADDR tRWL tRCS W tRAL tCAH tASC tCWL VIH - tCWL tWP VIL - tWP tCWD tCWD tAWD OE tAWD tCPWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA tRAC DQ tOEZ tDH tOED tDH tAA tDS tDS tOEZ VI/OH VI/OL - tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KMM372V404BS DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - tOFF DQ VOH VOL - OPEN Don′t care Undefined KMM372V404BS DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CAS tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRCS W tRRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC tRAC DQ VOH VOL - OPEN tCLZ tOEZ DATA-OUT Don′t care Undefined KMM372V404BS DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRC tRP tRAS VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP W OE VIH - tWCS tWCH tWP VIL - VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Don′t care Undefined KMM372V404BS DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP VIH - RAS tRAS VIL VIH - CAS tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC VIH - A VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH - W VIL VIH - OE VIL - tOEA tCLZ VOH - DQ tCAH COLUMN ADDRESS tOEZ DATA-OUT VOL - WRITE CYCLE W tOFF tWRP tRWL tWRH tCWL tWCS VIH - tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined KMM372V404BS DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care tRP RAS tRASS tRPS VIH - tRPC VIL - tRPC tCP CAS VIH - tCHS tCSR VIL - tOFF DQ VOH - OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - tOFF DQ VOH VOL - OPEN Don′t care Undefined KMM372V404BS DRAM MODULE PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) R 0.079 (R 2.000) 0.157±0.004 (4.000±0.100) 0.700 (17.780) 0.118 (3.000) B A .118DIA±.004 (3.000DIA±.100) 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.100Min (2.540Min) 1.000 (25.40) 0.118 (3.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) ( Front view ) (3.99 Min) 0.157 Min 0.100Max (2.54Max) 0.050±0.0039 (1.270±0.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.1230±.0050 (3.125±125) 0.039±.002 (1.000±.050) 0.1230±.0050 (3.125±125) 0.079±.0040 (2.000±.100) 0.079±.0040 (2.000±.100) Detail A (2.540 Min) ( Back view ) Detail B Tolerances : ±.005(.13) unless otherwise specified The used device is 4Mx16 & 4Mx4 DRAM with Fast Page mode, TSOP II. DRAM Part No. : KMM372V404BS -KM416V4100BS & KM44V4000CS 0.01Max (0.25 Max) 0.050 (1.270) Detail C