SAMSUNG KS0094

KS0094
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Nov.1999.
Ver. 0.4
Prepared by:
Won-Sik, Kang
[email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
KS0094 Specification Revision History
Version
0.0
Content
Original
Date
Apr.1999
CGROM font table added at table 5
COM data shift direction changed at table 9
0.1
Read data instruction separation according to RE bit at table 10
May.1999
Symbol register is changed to ICONRAM at table 12
IDD1 is changed at table 18, 19
0.2
IDD1 is changed at table 18, 19
Jun.1999
0.3
Pad location added at table 1 and 2
July.1999
0.4
VDD change (2.4V~5.5V -> 2.4V~3.6V)
Nov.1999
1
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION.......................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
BLOCK DIAGRAM ...................................................................................................................................... 3
PAD CONFIGURATION .............................................................................................................................. 4
PAD CENTER COORDINATES .................................................................................................................. 5
PIN DESCRIPTION...................................................................................................................................... 6
POWER SUPPLY ................................................................................................................................. 6
LCD DRIVER SUPPLY ......................................................................................................................... 6
SYSTEM CONTROL............................................................................................................................. 7
MPU INTERFACE ................................................................................................................................ 8
LCD DRIVER OUTPUTS ...................................................................................................................... 8
TEST .................................................................................................................................................... 8
FUNCTION DESCRIPTION.......................................................................................................................... 9
SYSTEM INTERFACE.......................................................................................................................... 9
ADDRESS COUNTER (AC)................................................................................................................ 13
DISPLAY DATA RAM (DDRAM) ......................................................................................................... 13
CHARACTER GENERATOR ROM (CGROM)..................................................................................... 13
CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 19
SEGMENT ICON RAM (ICONRAM).................................................................................................... 20
HIGH POWER MODE......................................................................................................................... 22
LOW POWER CONSUMPTION MODE .............................................................................................. 22
LCD DRIVER CIRCUIT....................................................................................................................... 23
INSTRUCTION DESCRIPTION.................................................................................................................. 24
INITIALIZING & POWER SAVE MODE SETUP......................................................................................... 35
HARDWARE RESET .......................................................................................................................... 35
INITIALIZING AND POWER SAVE SETUP......................................................................................... 37
LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 40
VOLTAGE CONVERTER.................................................................................................................... 40
VOLTAGE REGULATOR.................................................................................................................... 41
ELECTRONIC CONTRAST CONTROL (32 STEPS) ........................................................................... 42
VOLTAGE GENERATOR CIRCUIT .................................................................................................... 44
MPU INTERFACE...................................................................................................................................... 45
APPLICATION INFORMATION FOR LCD PANEL .................................................................................... 47
FRAME FREQUENCY ............................................................................................................................... 51
MAXIMUM ABSOLUTE RATINGS............................................................................................................. 52
ELECTRICAL CHARACTERISTICS .......................................................................................................... 53
DC CHARACTERISTICS .................................................................................................................... 53
AC CHARACTERISTICS .................................................................................................................... 54
2
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
INTRODUCTION
The KS0094 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can
display 2, 3 or 4 lines of 16 characters with 5 x 8 dots format. It is capable of interfacing various microprocessors,
supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. Voltage converter, oscillator,
voltage regulator, voltage follower and bias circuit are built in the IC. The double height character mode and line
vertical scroll functions are supported.
FEATURES
Driver Outputs
-
Common outputs: 34 common
Segment outputs: 80 segment
Applicable Panel Size
Font
5x8
Display
Duty
Contents of outputs
2-line x 16 characters
1 / 18
2 x 16 characters + 160 icons
3-line x 16 characters
1 / 26
3 x 16 characters + 160 icons
4-line x 16 characters
1 / 34
4 x 16 characters + 160 icons
Internal Memory
-
Character Generator ROM (CGROM): 21,760 bits (544 characters x 5 x 8 dots)
Character Generator RAM (CGRAM): 240 bits (6 characters x 5 x 8 dots)
Display Data RAM (DDRAM): 640 bits (16 characters x 5 lines )
Segment Icon RAM (ICONRAM): 160 bits (160 icons)
MPU Interface
-
No busy MPU interface (no busy check or no execution waiting time)
8-bit parallel interface mode: 68-series and 80-series are available
4-bit parallel interface mode: 68-series and 80-series are available
Serial interface mode: 4-pin clock synchronized serial interface
Function Set
-
Various instructions set: display control, power save, power control, etc.
COM / SEG bi-directional ( 4-type LCD application available)
H/W reset (RESETB)
Built-in Analog Circuit
-
Internal RC oscillator circuit or external clock
Electronic volume for contrast control (32 steps)
Voltage converter / voltage regulator / voltage follower & bias circuit
Low Power Operation
-
Sleep mode operation (5uA Max.)
Normal mode operation (TBD)
1
KS0094
PRELIMINARY SPEC. VER. 0.4
Operating Voltage Range
-
Power supply voltage (VDD): 2.2V – 3.6V
LCD driving voltage (VLCD = V0 - VSS): 7.0V Max.
Package Type
-
2
Gold bumped chip
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
BLOCK DIAGRAM
RESETB
CK
PS
Oscillator
IF
MI
CSB
RS
RW_WR
E_RD
Parallel
Interface
4 bit/8 bit
Instruction
Register
(IR)
8
Serial
Interface
Input Buffer
DB6
(SCL)
Instruction
Decoder
Address
Counter
DB7
(SI)
Data
Register
(DR)
8
DB5DB4
8
DB3DB0
COM1Common COM32
Driver
COM I1
COM I2
7
Data Output
Register
(OR)
Icon
RAM
160 bits
34 bits
Shift
Register
Display
Data RAM
(DDRAM)
640 bits
8
8
8
DUTY1
DUTY0
Timing Generator
80 bits
Shift
Register
80 bits
Latch
Circuit
SEG1Segment SEG80
Driver
8 8
Character
Generator
RAM
(CGRAM)
240 bits
5
Character
Generator
ROM
(CGROM)
21760 bits
Cursor
and
Blink
Controller
LCD
Driver
Voltage
Selector
5
VDD
Segment Data Conversion
GND
LCD Driving Power Circuit
Voltage Converter
CAP1+ CAP1- CAP2+ CAP2-
Voltage Regulator
Voltage Follower & Bias Resistor
VOUT V0
VR V1 V2 V3 V4
DIRS
Figure 1. Block Diagram
3
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CONFIGURATION (NOT FIXED)
82
163
............................
164
Y
183
X
...
...
..
(0,0)
81
62
...........................
61
1
DUMMY PAD
PAD
Figure 2. Pad Configuration
Table 1. KS0094 Pad Dimensions
Item
Pad No.
Chip size
-
Pad pitch
6320
1860
63~80,83~162,165~182
70
62,81,82,163,164,183
90
60
100
63~80
100
50
83~162
50
100
165~182
100
50
62,81
100
60
82,163
60
100
164,183
100
60
All pad
Unit
µm
1~61
COG Align Key Coordinate
17 (Typ.)
ILB Align Key Coordinate
42µm
30µm 30µm 30µm
42µm
108µm
(+3110, +880)
42µm
(-3110, +880)
108µm
42µm
108µm
108µm
60µm
(+2830, -830)
30µm 30µm 30µm
30µm
4
Y
90
Bumped pad height
(-2830, -835)
X
1 – 66
Bumped pad size
30µm 30µm 30µm
Size
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
PAD CENTER COORDINATES
[Unit: µm]
Table 2. Pad Center Coordinates
Pad
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Pad
Name
RS
VSS
RW_WR
VDD
E_RD
VSS
CSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDD
VDD
VSS
VSS
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
V0
V0
VR
VR
VSS
DUTY1
VDD
DUTY0
VSS
VOUT
VOUT
CAP2CAP2CAP2+
CAP2+
CAP1CAP1CAP1+
CAP1+
VSS
DIRS
VDD
CK
VSS
PS
VDD
IF
VSS
MI
VDD
RESETB
TEST
X
-2700
-2610
-2520
-2430
-2340
-2250
-2160
-2070
-1980
-1890
-1800
-1710
-1620
-1530
-1440
-1350
-1260
-1170
-1080
-990
-900
-810
-720
-630
-540
-450
-360
-270
-180
-90
0
90
180
270
360
450
540
630
720
810
900
990
1080
1170
1260
1350
1440
1530
1620
1710
1800
1890
1980
2070
2160
2250
2340
2430
2520
2610
2700
Y
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
-820
Pad
No
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Pad
Name
DUMMY1
C O M I1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
C O M I1
DUMMY2
DUMMY3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
X
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
3050
2845
2765
2695
2625
2555
2485
2415
2345
2275
2205
2135
2065
1995
1925
1855
1785
1715
1645
1575
1505
1435
1365
1295
1225
1155
1085
1015
945
875
805
735
665
595
525
455
385
315
245
175
105
35
Y
-700
-620
-550
-480
-410
-340
-270
-200
-130
-60
10
80
150
220
290
360
430
500
570
650
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
Pad
No
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
Pad
Name
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
DUMMY4
DUMMY5
C O M I2
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
C O M I2
DUMMY6
X
-35
-105
-175
-245
-315
-385
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1785
-1855
-1925
-1995
-2065
-2135
-2205
-2275
-2345
-2415
-2485
-2555
-2625
-2695
-2765
-2845
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
-3050
Y
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
820
650
570
500
430
360
290
220
150
80
10
-60
-130
-200
-270
-340
-410
-480
-550
-620
-700
5
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description
Name
VDD
I/O
Description
Power supply
Power
VSS
Connect to MPU power supply pin
0V (GND)
Bias voltage level for LCD driving
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the built-in power circuit is active and internal 1/5 bias resistors
are used.
V0
LCD bias
V1
V2
I/O
V3
1/5 bias
V1
V2
(4/5) x V0 (3/5) x V0
V3
V4
(2/5) x
V0
(1/5) x
V0
When the built-in power circuit is active and internal 1/4 bias resistors
are used.
V4
LCD bias
V1
1/4 bias (3/4) x V0
V2
V3
(2/4) x V0
V4
(1/4) x
V0
LCD DRIVER SUPPLY
Table 3. Pin Description (Continued)
6
Name
I/O
Description
CAP1+
O
Capacitor + connecting pin for the internal voltage converter
CAP1-
O
Capacitor - connecting pin for the internal voltage converter
CAP2+
O
Capacitor + connecting pin for the internal voltage converter
CAP2-
O
Capacitor - connecting pin for the internal voltage converter
VOUT
I/O
DC/DC voltage converter output
VR
I
Voltage adjust pin
This pin gives a voltage between V0 and VSS by resistance-division of
voltage.
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
SYSTEM CONTROL
Table 3. Pin Description (Continued)
Name
I/O
Description
External clock input
It must be fixed to "High" or "Low" when the internal oscillation circuit is used.
In case of the external clock mode, CK is used as the clock and OS bit
should be OFF.
MPU interface selection input
MI = "Low": 80 series MPU
MI = "High": 68 series MPU
CK
I
MI
I
PS
I
Parallel / Serial selection input
When PS = "Low": Serial mode
When PS = "High": 4-bit/8-bit bus mode
I
Interface data length selection pin for parallel data input
When PS = "Low"
IF = "Low" or "High": serial interface mode
When PS = “High”
IF = "Low": 4-bit bus mode
IF = "High": 8-bit bus mode
I
SEG direction selection input
When DIRS = "Low”
SEG1 → SEG2 → SEG79 → SEG80
When DIRS = "High”
SEG80 → SEG79 → SEG2 → SEG1
IF
DIRS
Display line mode selection input
DUTY1
DUTY0
I
DUTY1
DUTY0
Mode
Duty
0
0
2-line
1/18
0
1
3-line
1/26
1
0/1
4-line
1/34
7
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
MPU INTERFACE
Table 3. Pin Description (Continued)
Name
I/O
RESETB
I
Reset input
KS0094 is initialized while RESETB is low.
CSB
I
Chip selection input
KS0094 is selected while CSB is low.
RS
I
Register selection input
When RS = "Low", instruction register
When RS = "High", data register
I
In 80-series MPU interface mode
This pin is connected to WR pin of MPU and is an active low write signal.
In 68-series MPU interface mode
This pin is connected to R/W pin of MPU.
When RW_WR = "Low", write mode
When RW_WR = "High", read mode
I
In 80-series MPU interface mode
This pin is connected to RD pin of MPU and is a active low read signal.
In 68-series MPU interface mode
This pin is connected to E pin of MPU and enable read or write command
according to RW_WR signal.
RW_WR
E_RD
DB0 - DB3
DB4 - DB5
DB6 (SCL),
I/O
DB7 (SI)
Description
When 8-bit bus mode, used as bi-directional data bus DB0 - DB7.
During 4-bit bus mode, only DB4 - DB7 are used. In this case DB0 - DB3 pins
are not used.
When serial mode, DB6 (SCL) is used as serial clock input pin and DB7 (SI)
is used as serial data input pin.
LCD DRIVER OUTPUTS
Name
I/O
Description
COM1 – COM32
O
Common signal output for driving LCD
COMI1, COMI2
O
Common signal output for icon display
SEG1 – SEG80
O
Segment signal output for driving LCD
TEST
Name
I/O
TEST
I
Description
Test pin
This pin is not used for normal operation. Open at normal operation mode
NOTE: DUMMY – These pins should be opened (floated).
8
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
FUNCTION DESCRIPTION
SYSTEM INTERFACE
KS0094 has two kinds of interface type with MPU: bus mode, serial mode. Serial or bus mode is selected by PS
pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by
MI pin.
Table 4. Various Kinds of MPU Interface according to PS, MI and IF
PS
Bus
mode (H)
Serial
mode (L)
MI
IF
CSB
RS
RW_WR
E_RD
DB0∼
∼ DB3
DB4∼
∼ DB5
DB6
DB7
68 series
8 bit (H)
CSB
RS
R/W
E
DB0∼DB3
DB4∼DB5
DB6
DB7
DB4∼DB5
DB6
DB7
∗
(1)
(H)
4 bit (L)
CSB
RS
R/W
E
80 series
8 bit (H)
CSB
RS
WR
RD
DB0∼DB3
DB4∼DB5
DB6
DB7
(L)
4 bit (L)
CSB
RS
WR
RD
∗
DB4∼DB5
DB6
DB7
(H)/(L)(2)
(H)/(L)
CSB
RS
(H)/(L)
(H)/(L)
∗
∗
SCL
SI
NOTES:
1. ‘ * ‘: Don’t care (High, Low or Open)
2. ‘ (H)/(L) ‘: Fixed High (VDD) or Low (VSS)
PS: "High" = bus mode, "Low" = serial mode
MI: "High" = 68-series MPU, "Low" = 80-series MPU
IF: "High" = 8-bit mode, "Low" = 4-bit mode (PS: "High")
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, "Low" = instruction register
RW_WR: read / write indicating signal in 68 mode or active low signal for enabling write in 80 mode.
E_RD: active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode.
SCL (DB6): serial clock input
SI (DB7): serial data input
9
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Parallel Mode (PS = "High")
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and
one of these RAM is selected by RAM address setting instruction. The Instruction register (IR) is used only to
store instruction code transferred from MPU. To select DR or IR register, RS input pin is used.
During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used
as temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAM is
selected by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit
bus mode (figure 3, 4). The valid data comes from second reading. In 4-bit bus mode, after RAM address setting,
first and second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy
read make the address counter (AC) increased by 1. So it is recommended to set address again before writing.
The instruction read cycle is not supported and it is regarded as a no operation cycle.
In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7-DB4) by two times. The high order bits (for 8-bit
mode DB7-DB4) are written before the low order bits (for 8-bit mode DB3-DB0) in write and low order bits (for 8-bit
mode DB3-DB0) are read before the high order bits (for 8-bit mode DB7-DB4) in read transaction. The DB0-DB3
pins are floated in this 4-bit bus mode. After RESETB resets, KS0094 considers first 4-bit data from MPU as the
high order bits.
IF
MI
CSB
RS
RW_WR
E_RD
Valid
Data
DB7-DB0
Instruction
Write
NOP
Dummy
Read
RAM
Read
Data
Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
10
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
IF
MI
CSB
RS
RW_WR
E_RD
Valid
Data
DB7-DB0
Instruction
W rite
NOP
Dummy
Read
RAM
Read
Data
W rite
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
IF
MI
CSB
RS
RW_WR
E_RD
DB7-DB4
upper
4-bit
lower
4-bit
Instruction Write
upper
4-bit
NOP
Dummy Read
lower
4-bit
RAM Read
upper
4-bit
lower
4-bit
Data Write
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
IF
MI
CSB
RS
RW_WR
E_RD
DB7-DB4
upper
4-bit
lower
4-bit
Instruction Write
upper
4-bit
NOP
Dummy Read
lower
4-bit
RAM
Read
upper
4-bit
lower
4-bit
Data Write
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
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KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Serial Mode (PS = "Low")
When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, four ports, SCL
(DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB (chip
selection input) are used.
By setting CSB to "Low", KS0094 can receive SCL input. If CSB is set to "High", KS0094 resets the internal 8-bit
shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial
data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6).
At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS
input of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL).
In serial mode, the read is not possible.
CSB
SI (DB7)
S C L (DB6)
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
RS
Figure 7. Timing Diagram of Serial Data Transfer
12
D0
8
D7
9
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
ADDRESS COUNTER (AC)
Address Counter (AC) in KS0094 stores DDRAM / CGRAM / ICONRAM address. After writing into or reading from
DDRAM / CGRAM / ICONRAM, AC is automatically increased by 1. The address counter is only one and stores
the address among DDRAM / CGRAM / ICONRAM.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 80 x 8 bits (Max. 80 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number.
1st Ch.
16th Ch.
COM1
∼ COM8
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
COM9
∼ COM16
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
COM17 ∼ COM24
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
COM25 ∼ COM32
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
Hidden Line
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
SEG1
SEG80
DDRAM Address in 4 line Display
Figure 8. DDRAM Address
CHARACTER GENERATOR ROM (CGROM)
CGROM has one main ROM and four option ROM. The main CGROM has 160 characters and the option
CGROMs have 96 characters each. The total CGROM has 5 x 8-dot 544 characters. The R1, R0 bits select an
option CGROM between 4 option CGROM. If one of 4 CGROM is selected, the other CGROM font can not be
used. The CG bit of the instruction table selects the 6 characters (00h ∼ 05h) of CGROM or CGRAM.
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KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (Main ROM)
14
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Table 5. CGROM Character Code (Option ROM1) (Continued)
15
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (Option ROM2) (Continued)
16
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Table 5. CGROM Character Code (Option ROM3) (Continued)
17
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (Option ROM4) (Continued)
18
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
CHARACTER GENERATOR RAM (CGRAM)
CGRAM has up to 5 x 8-dot 6 characters. By writing font data to CGRAM, user defined character can be used.
CGRAM can be written regardless of CG bit.
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character code
CGRAM address
(DDRAM data)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0
(00h)
0 0 0 0 0 0 0 1
(01h)
0 0 0 0 0 0 1 0
(02h)
0 0 0 0 0 0 1 1
(03h)
RE
CGRAM data
A6 A5 A4 A3 A2 A1 A0
Pattern
P7 P6 P5 P4 P3 P2 P1 P0
number
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
Pattern 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pattern 2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Pattern 3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
0
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
1
0
1
1
1
Pattern 4
NOTE: ”-” - Don’t care
19
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) (continued)
Character code
CGRAM address
(DDRAM data)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 0 0
(04h)
0 0 0 0 0 1 0 1
(05h)
RE
CGRAM data
A6 A5 A4 A3 A2 A1 A0
Pattern
number
P7 P6 P5 P4 P3 P2 P1 P0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
Pattern 5
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
-
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Pattern 6
NOTE: ”-” - Don’t care
SEGMENT ICON RAM (ICONRAM)
ICONRAM has segment control data and segment pattern data. The number of icons is 160.
……
S1
S5
S76
……
S80
COMI1
COMI2
S81
……
S85
S156
……
Figure 9. Relationship between ICONRAM and Icon Display
20
S160
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Table 7. Relationship between ICONRAM Address and Display Pattern
D5
D4
D3
D2
D1
D0
60h
-
-
-
S1
S2
S3
S4
S5
1
61h
-
-
-
S6
S7
S8
S9
S10
1
62h
-
-
-
S11
S12
S13
S14
S15
.
.
...
.
.
1
6Dh
-
-
-
S66
S67
S68
S69
S70
1
6Eh
-
-
-
S71
S72
S73
S74
S75
1
6Fh
-
-
-
S76
S77
S78
S79
S80
1
70h
-
-
-
S81
S82
S83
S84
S85
1
71h
-
-
-
S86
S87
S88
S89
S90
1
72h
-
-
-
S91
S92
S93
S94
S95
.
.
.
...
...
1
7Dh
-
-
-
S146
S147
S148
S149
S150
1
7Eh
-
-
-
S151
S152
S153
S154
S155
1
7Fh
-
-
-
S156
S157
S158
S159
S160
...
...
.
...
D6
...
D7
...
1
ICONRAM bits
...
ICONRAM address
...
RE
NOTE: ”-” - Don’t care
21
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
HIGH POWER MODE
The power circuit built-in the KS0094 is a low power consumption type (when the High Power mode is OFF).
Accordingly, in the case of a large load liquid crystal or panel, the display quality may be degraded. In the case,
the display quality can be improved by entering HPM = “1” by command. Before determining whether or not to use
this mode. It is recommended to make a display check with real machine. In the case, the display quality cannot
be improved satisfactorily though the power mode is set, a liquid crystal driver power must be supplied from the
outside.
LOW POWER CONSUMPTION MODE
KS0094 provides with sleep mode for saving power consumption during standby period.
Sleep Mode (Power Save Bit ON, Oscillation Bit OFF)
To enter the Sleep mode, the power circuit and oscillation circuit should be turned off by using the power save
command and the power control command. This mode helps to save power consumption by reducing current to
reset level.
1. Liquid Crystal Display Output
COM1 - COM32, COMI1, COMI2 : VSS level
SEG1 - SEG80 : VSS level
2. Data written in DDRAM, CGRAM, ICONRAM and registers are remained as previous value.
3. Operation mode is retained the same as it was prior to execution of the sleep mode.
All internal circuits are stopped.
4. Power Circuit and Oscillation Circuit
The built-in power supply circuit and oscillation circuit are turned off by power save command and power
control command.
22
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
LCD DRIVER CIRCUIT
LCD Driver circuit has 34 commons and 80 segments signals for driving LCD. Data from ICONRAM / CGRAM /
CGROM are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. In case of
2-line display mode COM1 - COM16, COMI1 and COMI2 have 1/18 duty, in 3-line mode COM1 - COM24, COMI1
and COMI2 have 1/26 duty, and in 4-line mode COM1 - COM32, COMI1 and COMI2 have 1/34 duty ratio. SEG bidirectional function is selected by DIRS input pin, and COM shift direction is selected by function set instruction
"SS" bit.
Table 8. SEG Data Shift Direction
DIRS pin
SEG data shift direction
Low
SEG1 → SEG2 → SEG3
High
SEG80 → SEG79 → SEG78
SEG78 → SEG79 → SEG80
...................
SEG3 → SEG2 → SEG1
...................
Table 9. COM Data Shift Direction
Line
mode
CS
COM data shift direction
2-line
0 (left)
COM1
mode
1 (right)
COM16
3-line
0 (left)
COM1
mode
1 (right)
COM24
4-line
0 (left)
COM1
mode
1 (right)
→
COM2 ..…….. COM15
→
COM2 ............ COM23
→
COM32
COM16
→
COM15 ……..... COM2
→
→
→
→
COM23 .....…...... COM2
COM2 .......…. COM31
→
→
COM31 ..…….... COM2
→
COMI1
→
COMI2
COM1
→
COMI1
COM24
→
COMI1 → COMI2
→
COM32
→
→
COM1
COM1
→
→
→
COMI2
COMI1 → COMI2
COMI1
COMI1
→
→
COMI2
COMI2
23
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Table 10. Instruction Table
Instruction
RE
0
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
*
*
*
*
Description
DDRAM address is set to 30h from AC and the cursor returns
to home position The contents of DDRAM are not changed.
Determination of the DDRAM line which is displayed at the
Return home
first line at LCD
LS1, LS0 = 00: DDRAM line 1 shows at the first line of LCD
line shift
1
0
0
0
0
1
*
*
LS1
LS0
(default)
01: DDRAM line 2 shows at the first line of LCD
10: DDRAM line 3 shows at the first line of LCD
11: DDRAM line 4 shows at the first line of LCD
Line blink mode
LB4 = 0: DDRAM4 is normal display (default)
1: DDRAM4 is blink mode
LB3 = 0: DDRAM3 is normal display (default)
0
0
0
0
1
0
LB4
LB3
LB2
LB1
1: DDRAM3 is blink mode
LB2 = 0: DDRAM2 is normal display (default)
1: DDRAM2 is blink mode
LB1 = 0: DDRAM1 is normal display (default)
1: DDRAM1 is blink mode
Line blink
double height
Doubled height mode
DH4 = 0: DDRAM4 is normal display (default)
1: DDRAM4 is double height
DH3 = 0: DDRAM3 is normal display (default)
1
0
0
0
1
0
DH4 DH3 DH2 DH1
1: DDRAM3 is double height
DH2 = 0: DDRAM2 is normal display (default)
1: DDRAM2 is double height
DH1 = 0: DDRAM1 is normal display (default)
1: DDRAM1 is double height
Cursor / blink / display ON / OFF
C = 0: cursor OFF (default)
1: cursor ON
B = 0: blink OFF (default)
Display control
0/1
0
0
0
1
1
C
B
RE
D
1: blink ON
RE=0: extension register OFF (default)
1: extension register ON
D = 0: display OFF (default)
1: display ON
Power save / oscillation circuit ON / OFF
OS = 0: oscillator OFF (default)
Power save
0/1
0
0
1
0
0
*
*
OS
PS
1: oscillator ON
PS = 0: power save OFF (default)
1: power save ON
24
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Table 10. Instruction Table (Continued)
Instruction
RE
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
LCD power control
HPM = 0: high power mode OFF (default)
1: High power mode ON
VR =
0
0
0
1
0
1
HPM
VR
VF
0 : Voltage regulator OFF (default)
1 : Voltage regulator ON
VC
VF =
0 : Voltage follower OFF (default)
1 : Voltage follower ON
VC =
0 : Voltage converter OFF (default)
1 : Voltage converter ON
Power
Internal resistor select
control
IRS = 0: external resistors are used for regulator (default)
1: internal resistors are used for regulator
LCD bias select
BS = 0: 1/5 bias (default)
1
0
0
1
0
1
IRS
BS
IR1
IR0
1: 1/4 bias
Internal resistor ratio select
IR1, IR0 = 00: (1+Rb/Ra) = 2.81
01: (1+Rb/Ra) = 3.27
10: (1+Rb/Ra) = 3.50
11: (1+Rb/Ra) = 3.00
0
0
0
1
1
0
R1
R0
CS
1
0
0
1
1
0
*
*
SS
System
set
Option CGROM select
R1,R0 = 00: main ROM + option ROM1 (default)
01: main ROM + option ROM2
10: main ROM + option ROM3
11: main ROM + option ROM4
CG Shifting direction of COM
CS = 0: COM1 → COM32 (default)
1: COM32 → COM1
Select CGRAM or CGROM
CG = 0: CGROM (default), 1: CGRAM
Segment symmetry of each segment character
*
SS = 0: normal character display (default)
1: symmetrical character display
DDRAM /
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
DDRAM or Electronic volume Address
Range: 30h - 7Fh
CGRAM
address set
1
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
CGRAM or segment ICON RAM Address
Range: 00h - 2Fh
Write DDRAM / CGRAM / ICONRAM/electronic volume RAM
Write data
0/1
1
D7
D6
D5
D4
D3
D2
D1
D0 This is determined by the address set instruction executed
immediately before writing data.
Read data
0/1
1
D7
D6
D5
D4
D3
D2
D1
Read DDRAM / CGRAM / ICONRAM
D0 This is determined by the address set instruction executed
immediately before reading data.
NOP
0/1
0
0
0
0
0
0
0
0
0
Non-operation Instruction
Test
0/1
0
0
0
0
0
*
*
*
*
Don’t use this Instruction
NOTES:
1. "-": Don’t care
2. "*": Don’t use
25
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Return Home
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
0
1
*
*
*
*
*: Don’t care
Return Home instruction field makes cursor return home. DDRAM address is set to 30h from address counter and
the cursor returns to home position. The contents of DDRAM are not changed.
Line Shift Mode
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
1
0
0
0
0
1
*
*
LS2
DB0
LS1
*: Don’t care
Line Shift mode instruction field selects the DDRAM to be displayed in first line.
LS1, LS0 = 00: scroll amount 0 line (default)
01: scroll 1 line upward (display line 1 from DDRAM line 2)
10: scroll 2 line upward (display line 2 from DDRAM line 3)
11: scroll 2 line upward (display line 3 from DDRAM line 4)
LCD
LCD
LCD
LCD
DD RAM Line1 (30 h ~ 3Fh)
DD RAM Line2 (40 h ~ 4Fh)
DD RAM Line3 (50 h ~ 5Fh)
DD RAM Line4 (60 h ~ 6Fh)
DD RAM Line2 (40 h ~ 4Fh)
DD RAM Line3 (50 h ~ 5Fh)
DD RAM Line4 (60 h ~ 6Fh)
DD RAM Line5 (70 h ~ 7Fh)
DD RAM Line3 (50 h ~ 5Fh)
DD RAM Line4 (60 h ~ 6Fh)
D D R A M L i n e 5 (70 h ~ 7Fh)
D D R A M L i n e 1 (30 h ~ 3Fh)
DD RAM Line4 (60 h ~ 6Fh)
D D R A M L i n e 5 (70 h ~ 7Fh)
D D R A M L i n e 1 (30 h ~ 3Fh)
DD RAM Line2 (40 h ~ 4Fh)
D D R A M L i n e 5 (70 h ~ 7Fh)
DD RAM Line1 (30 h ~ 3Fh)
DD RAM Line2 (40 h ~ 4Fh)
DD RAM Line3 (50 h ~ 5Fh)
LS2, LS1 = 00
LS2, LS1 = 01
LS2, LS1 = 10
LS2, LS1 = 11
Figure 10. Line Shift Mode Display at 3-line LCD
LCD
LCD
LCD
DD RAM Line2 (40h~4Fh)
DD RAM Line3 (50h~ 5Fh)
DD RAM Line4 (60h~6Fh)
DD RAM Line2 (40h~4Fh)
DD RAM Line3 (50h~5Fh)
DD RAM Line4 (60h~ 6Fh)
DD RAM Line5 (70h~7Fh)
DD RAM Line3 (50h~5Fh)
DD RAM Line4 (60h~6Fh)
DD RAM Line5 (70h~ 7Fh)
DD RAM Line1 (30h~3Fh)
DD RAM Line4 (60h~6Fh)
DD RAM Line5 (70h~7Fh)
DD RAM Line1 (30h~ 3Fh)
DD RAM Line2 (40h~4Fh)
DD RAM Line5 (70h~7Fh)
DD RAM Line1 (30h~3Fh)
DD RAM Line2 (40h~ 4Fh)
DD RAM Line3 (50h~5Fh)
LS2, LS1 = 00
LS2, LS1 = 01
LS2, LS1 = 10
LS2, LS1 = 11
Figure 11. Line Shift Mode Display at 4-line LCD
26
LCD
DD RAM Line1 (30h~3Fh)
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Line Blink Display Control
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
LB4
LB3
LB2
LB1
Displays the specified line in black-and-white form. The specified line corresponds to the address line of DDRAM.
Display the specified line of the DDRAM in black-and-white form by setting LB4 to LB1. Blinking is performed at
the same frequency as cursor blink. If blinking is caused to occur at the same time, the cursor position will be hard
to know.
LB4 = 0: displays the data for line 4 of the DDRAM in standard form (no blink)
(DDRAM 60H to 6FH)
= 1: displays the data for line 4 of the DDRAM in black-and-white reverse blink form
(DDRAM 60H to 6FH)
LB3 = 0: displays the data for line 3 of the DDRAM in standard form (no blink)
(DDRAM 50H to 5FH)
= 1: displays the data for line 3 of the DDRAM in black-and-white reverse blink form
(DDRAM 50H to 5FH)
LB2 = 0: displays the data for line 2 of the DDRAM in standard form (no blink)
(DDRAM 40H to 4FH)
= 1: displays the data for line 2 of the DDRAM in black-and-white reverse blink form
(DDRAM 40H to 4FH)
LB1 = 0: displays the data for line 1 of the DDRAM in standard form (no blink)
(DDRAM 30H to 3FH)
= 1: displays the data for line 1 of the DDRAM in black-and-white reverse blink form
(DDRAM 30H to 3FH)
Double Height Mode
RE
RS
DB7
DB6
DB5
DB4
1
0
0
0
1
0
Double Height mode instruction field selects double height line type.
DB3
DB2
DB1
DB0
DH4
DH3
DH2
DH1
DH4 = 0: displays the data for line 4 of the DDRAM in standard form
(DDRAM 60H to 6FH)
= 1: displays the data for line 4 of the DDRAM in vertical double size form
(DDRAM 60H to 6FH)
DH3 = 0: displays the data for line 3 of the DDRAM in standard form
(DDRAM 50H to 5FH)
= 1: displays the data for line 3 of the DDRAM in vertical double size form
(DDRAM 50H to 5FH)
DH2 = 0: displays the data for line 2 of the DDRAM in standard form
(DDRAM 40H to 4FH)
= 1: displays the data for line 2 of the DDRAM in vertical double size form
(DDRAM 40H to 4FH)
DH1 = 0: displays the data for line 1 of the DDRAM in standard form
(DDRAM 30H to 3FH)
= 1: displays the data for line 1 of the DDRAM in vertical double size form
(DDRAM 30H to 3FH)
27
KS0094
PRELIMINARY SPEC. VER. 0.4
(1) Initial Status
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
(2) DD4, DD3, DD2, DD1= 1010
(3) 1-line Shift
30H -------------------- 3FH
30H -------------------- 3FH
30H -------------------- 3FH
40H -------------------- 4FH
40H --------------- 4FH
40H --------------- 4FH
60H -------------------- 6FH
50H -------------------- 5FH
50H -------------------- 5FH
70H -------------------- 7FH
60H --------------- 6FH
60H --------------- 6FH
70H -------------------- 7FH
70H -------------------- 7FH
50H -------------------- 5FH
(4) 2-line Shift
(5) 3-line Shift
30H -------------------- 3FH
30H -------------------- 3FH
40H --------------- 4FH
40H --------------- 4FH
50H -------------------- 5FH
50H -------------------- 5FH
60H --------------- 6FH
60H --------------- 6FH
70H -------------------- 7FH
70H -------------------- 7FH
Figure 12. Line Double Height Mode Display
28
DDRAM Area
Display Area
XXH : DDRAM Address
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Display Control
RE
RS
DB7
DB6
DB5
DB4
DB3
0/1
0
0
0
1
0
C
Display Control instruction field controls cursor / blink / display ON / OFF.
DB2
DB1
DB0
B
RE
D
C: Cursor ON / OFF control bit
When C = "High", cursor is turned ON
When C = "Low", cursor is disappeared in current display (default).
B: Cursor blink ON / OFF control bit
When C = "High" and B = "High", KS0094 make LCD alternate between inverting display character and normal
display character at the cursor position with about a half second. On the contrary, if C = "Low", only a normal
character is displayed regardless of "B" flag.
When B = "Low", blink is OFF (default).
RE: Extended register access is specified by setting RE
When RE = “High”, extended register ON
When RE = “Low”, extended register OFF
D: Display ON / OFF control bit
When D = "High", entire display is turned ON.
When D = "Low", display is turned OFF, but display data are remained in DDRAM (default).
Table 11. Cursor Attributes
C, B
Display state
1, 0
1, 1
(Blinking mode)
0, 0
0, 1
29
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Power Save
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0/1
0
0
1
0
0
*
*
OS
PS
*: Don’t care
Power Save instruction field is used to control the oscillator and to set or to reset the power save mode.
OS: oscillator ON / OFF control bit
When OS = "High", internal oscillator is turned ON
When OS = "Low", internal oscillator is turned OFF (default)
PS: power save ON / OFF control bit
When PS = "High", power save mode is turned ON
When PS = "Low", power save mode is turned OFF (default)
Power Control (1)
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
HPM
VR
VF
VC
Power Control instruction field sets high power mode and voltage regulator / converter / follower ON / OFF.
HPM: high power mode control bit
When HPM = “High”, high power mode is turned ON
When HPM = “Low”, high power mode is turned OFF (default)
VR: voltage regulator circuit control bit
When VR = "High", voltage regulator is turned ON
When VR = "Low", voltage regulator is turned OFF (default)
VF: voltage follower circuit control bit
When VF = "High", voltage follower is turned ON
When VF = "Low", voltage follower is turned OFF (default)
VC: voltage converter circuit control bit
When VC = "High", voltage converter is turned ON
When VC = "Low", voltage converter is turned OFF (default)
NOTE: The oscillation circuit must be turned on for the voltage converter circuit to be active.
Power Control (2)
RE
RS
DB7
DB6
DB5
DB4
DB3
1
0
0
1
0
1
IRS
IRS: initial resistors select
When IRS = “High”, internal resistors are used for regulator
When IRS = “Low”, external resistors are used for regulator (default)
BS: bias select
When BS = “High”, it’s 1/4 bias
When BS = “Low”, it’s 1/5 bias (default)
IR1, IR0: internal resistor ratio select
When IR1,IR0 = 00, (1 + Rb/Ra) = 2.81,
When IR1,IR0 = 01, (1 + Rb/Ra) = 3.27,
When IR1,IR0 = 10, (1 + Rb/Ra) = 3.50,
When IR1,IR0 = 11, (1 + Rb/Ra) = 3.00,
30
V0 = 5.60V
V0 = 6.54V
V0 = 7.00V
V0 = 6.00V
DB2
DB1
DB0
BS
IR1
IR0
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
System Set (1)
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
0
0
0
1
1
0
R1
R0
R1, R0: selects an option ROM
When R1, R0 = 00, standard ROM (160 characters) + option ROM1 (96 characters)
When R1, R0 = 01, standard ROM (160 characters) + option ROM2 (96 characters)
When R1, R0 = 10, standard ROM (160 characters) + option ROM3 (96 characters)
When R1, R0 = 11, standard ROM (160 characters) + option ROM4 (96 characters)
DB1
DB0
CS
CG
CS: data shift direction of common
CS sets the shift direction of common display data
When CS = "High", COM right shift
When CS = "Low", COM left shift (default)
(refer to table 9 and figure 13)
CG: CGRAM enable bit
When CG = "High", CGRAM can be used and you can use this RAM for eight special character area.
(00h - 05h=CGRAM font display)
When CG = "Low", CGRAM is disabled. CGROM (00h - 05h) can be used and the additional current
consumption is saved by using this mode (default)
(00h - 05h=CGROM font display)
System Set (2)
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
1
0
0
1
1
0
*
*
SS
DB0
*
*: Don’t care
SS: the normal / reverse character display of SEG is specified by setting SS.
When SS = “LOW”, normal display of SEG
When SS = ‘HIGH”, reverse display of SEG
ROM Font
(SS, CS) = (0, 0)
(SS, CS) = (1, 0)
(SS, CS) = (0, 1)
(SS, CS) = (1, 1)
Figure 13. Example of Display according to SS and CS-bit
31
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
DDRAM Address Set
RE
DB7
RS
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Above RAM Address Set instruction field sets DDRAM and electronic volume register in the address counter.
Before writing / reading data into / from the DDRAM, set the address by DDRAM Address set instruction. Next,
when data are written / read in succession, the address is automatically increased by 1. After accessing 7Fh, the
address of AC is 00h. The read data from the unused address are unknown.
The address ranges are 00h - 7Fh.
Table 12. RAM Address Mapping (RE = 0)
Address
0
1
2
00h
4
Unused
5
6
7
8
9
EV
Test
10h
Unused
20h
Unused
30h
DDRAM line-1
40h
DDRAM line-2
50h
DDRAM line-3
60h
DDRAM line-4
70h
DDRAM line-5
EV: Electric volume RAM
TEST: Testing register, don’ use it.
32
3
A
B
C
D
Unused
E
F
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
CGRAM Address Set
RE
DB7
DB1
DB0
1
0
1
AC6
AC5
AC4
AC3
AC2
AC1
Above RAM Address set instruction field sets CGRAM, segment icon RAM in the address counter.
AC0
RS
DB6
DB5
DB4
DB3
DB2
Before writing / reading data into / from the CGRAM / ICONRAM, set the address by CGRAM Address Set
instruction. Next, when data are written/read in succession, the address is automatically increased by 1. After
accessing 7Fh, the address of AC is 00h. The read data from the unused address are unknown.
The address ranges are 00h - 7Fh.
Table 13. RAM Address Mapping (RE = 1)
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
00h
CGRAM (00H)
CGRAM (01H)
10h
CGRAM (02H)
CGRAM (03H)
20h
CGRAM (04H)
CGRAM (05H)
30h
Unused
40h
Unused
50h
Unused
60h
ICONRAM (S1 - S80)
70h
ICONRAM (S81 - S160)
D
E
F
33
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Write Data
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0/1
1
D7
D6
D5
D4
D3
D2
D1
D0
This instruction field make KS0094 write binary 8-bit data to DDRAM / CGRAM / ICONRAM or register. The RAM
address to be written into is determined by previous DD/CGRAM Address Set instruction. After writing operation,
the address counter (AC) automatically increased by 1.
Read Data
RE
RS
DB7
DB6
DB5
0/1
1
D7
D6
D5
DDRAM / CGRAM / ICONRAM data read instruction.
DB4
DB3
DB2
DB1
DB0
D4
D3
D2
D1
D0
Each RAM is selected by address set instruction. And then you can read the RAM data. You can get correct RAM
data from second read transaction. The first read data after setting RAM address is dummy data, so the correct
RAM data come from the second read transaction. After reading operation, the address counter (AC) is increased
by 1 automatically.
NOP
RE
RS
DB7
DB6
DB5
DB4
DB3
0/1
0
0
0
0
0
0
No operation command
It is recommended to add this command at each breakpoint of the program.
DB2
DB1
DB0
0
0
0
Test Mode
RE
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0/1
0
0
0
0
0
*
*
*
*
*: Don’t care
An IC test mode set command. Don’t use it any case.
34
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
INITIALIZING & POWER SAVE MODE SETUP
HARDWARE RESET
When RESETB pin = "Low", KS0094 can be initialized as the following state.
(1) Control Display ON / OFF Instruction
C = 0: cursor OFF
B = 0: blink OFF
RE = 0: extension register OFF
D = 0: display OFF
(2) Power Save Set Instruction
OS = 0: oscillator OFF
PS = 0: power save OFF
(3) Power Control Set Instruction
HPM = 0: high power mode OFF
VR = 0: voltage regulator OFF
VF = 0: voltage follower OFF
VC = 0: voltage converter OFF
IRS = 1: for built-in resistor
BS = 0: 1/5 bias
IR1, 0 = 00: Rb / Ra = 2.81
(4) System Set Instruction
R1, R0 = 00: main ROM + option ROM
CS = 0: COM left shift
SS = 0 : normal display character
CG = 0: CGRAM is not used
(5) Return Home
Address counter = 30h
(6) Electronic Contrast Control Register: address 10h = data (0, 0, 0, 0, 0)
(7) In Case of 4-bit Interface Mode Selection
KS0094 considers the first 4-bit data from MPU as the high order bits.
NOTE: If initialization is not done by the RESETB pin at application, unknown condition might result. Then you can
initialize by instruction.
35
KS0094
PRELIMINARY SPEC. VER. 0.4
VDD
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
tRESETB
RESETB
tRW
RESETB pulse width
tRW
10µs
RESETB start time
tRESETB
50ns
Figure 14. RESET Timing
36
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
INITIALIZING AND POWER SAVE SETUP
Initializing by Instruction
VDD-VSS Power ON
Keep RESETB Pin = "L"
When the power is stable,
release the reset state (RESETB = "H").
Waiting for 10us or more
Command Input
1. Function Set (N, S, CG)
2. Electronic Volume Register Setup (08h)
3. Power Save (PS: Power Save OFF, OS: OSC ON)
4. Power Control (VR, VF, VC are all ON)
Waiting for 500us or more
Command Input
5. RAM Address set
Command Input
6. Data Writing (RAM Clear)
(DDRAM = 20h, CGRAM = 00h)
NOTE:
At command 5 and 6, the internal RAM
should be cleared.
To clear DDRAM,
RE bit should be set 0,
set address at 30h (first DDRAM)
and then write 20h (space character code)
80 times
To clear CGRAM (RE=1),
RE bit should be set 1,
Set address at 00h (first CGRAM)
and then write 00h (null data) 48 times
To clear ICONRAM (RE=1),
RE bit should be set 1,
set ICONRAM address at 60h (first
ICONRAM) and then write 00h (null data)
32 times
Command Input
7. Display Control (D: ON)
End of Initialization
37
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Sleep Mode Set or Release by Instruction
a) Sleep Mode Set
End of Initialization
Normal Operation status
(Power save is OFF and oscillator is ON.)
Command Input
1. Display Control (D: OFF)
2. Power Save (PS: Power Save ON, OS: OSC OFF)
3. Power Control (VR, VF, VC are all OFF)
Enter the Sleep Mode
b) Sleep Mode Release
Sleep Mode
Command input
1. Power Save (PS: Power Save OFF, OS: OSC ON)
2. Power Control (VR, VF, VC are all ON)
Waiting for 500 us or more
Command Input
3. Display Control (D: ON)
Return to Normal Operation
38
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Recommendation of Power ON / OFF Sequence
a) Power ON Sequence
Power ON
Voltage Converter ON
[VR, VF, VC = 0, 0, 1]
Waiting for ≥ 1ms
Voltage Regulator ON
[VR, VF, VC = 1, 0, 1]
Waiting for ≥ 1ms
Voltage Follower ON
[VR, VF, VC = 1, 1, 1]
Operation Command Input
b) Power OFF Sequence
Operation Command Input
Display OFF
Voltage Regulator OFF
[VR, VF, VC = 0, 1, 1]
Waiting for ≥ 50ms
Voltage Follower OFF
[VR, VF, VC = 0, 0, 1]
Waiting for ≥ 1ms
Voltage Converter OFF
[VR, VF, VC = 0, 0, 0]
Waiting for ≥ 1ms
Operation Command Input
39
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVING POWER SUPPLY CIRCUIT
The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving Power
Supply circuit consists of voltage converter, voltage regulator, and voltage follower. It is controlled by power
control instruction. Table 14 shows how the LCD Driving Power Supply circuit works by power control instruction
sets.
Table 14. Power Supply Control Mode Set
VR VF VC
Voltage
regulator
Voltage
follower
Voltage
converter
VOUT pin
VR pin
V0, V1, V2,
V3, V4 pin
Enable
Enable
Enable
Internal
voltage
output
Used for
voltage
adjustment
Internal voltage output
1 1 1
Enable
Enable
Disable
External
voltage
input
Used for
voltage
adjustment
Internal voltage output
1 1 0
0 1 0
Disable
Enable
Disable
Open
Open
V1∼V4: Internal voltage output
V0: External voltage input
0 0 0
Disable
Disable
Disable
Open
Open
V0∼V4: External voltage input
NOTE: SEC recommendation is to use only the case listed above table.
VOLTAGE CONVERTER
The Voltage Converter circuit generates positive 4 times voltage of 2.0V that is generated internally. VOUT is
generated from the Voltage Converter. And this conversion voltage is used in the built-in voltage regulator circuit.
This application circuit is same as 3 times DC/DC converter.
VOUT
VDD
KS0094
VDD
-
+
+
-
4 x 2.0V = 8.0V
2.0V
(Internal)
CAP1+
CAP1-
+
CAP2+
-
CAP2VOUT
VSS
Figure 15. DC/DC Converter Output and Circuit
40
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
VOLTAGE REGULATOR
The Voltage Regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained
by adjusting resistors Ra and Rb as shown in equation (1), and by setting electronic contrast control data bits, see
equation (2).
The potential of V0 Pin can be adjusted within VOUT - VREF. VREF is the internal constant voltage source of the
chip and this value is 2.0V in the condition VDD ≥ 2.2V
n
Voltage regulation by adjusting resistors Ra, Rb
When REF is "Low"
Rb
V0 = ( 1 +
) x VREF --- (1)
Ra
The internal VREF of voltage regulator has the temperature compensation function, and the temperature coefficient
is approximately 0%
Rb
VOUT
VR
V0
_
+
Ra
VREF
Inside Chip
VSS
GND
Figure 16. Voltage Regulator Circuit
41
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
ELECTRONIC CONTRAST CONTROL (32 STEPS)
Electronic Contrast Control data bits is 10h = (d4, d3, d2, d1, d0). Voltage regulation is adjusted as 32-contrast
step according to the value of Electronic Contrast Control data bits. LCD drive voltage V0 has one of 32 voltage
values if 5-bit data is set to the Electronic Contrast Control register (RE = 0 address 08h). When using the
Electronic Contrast Control function, you need to turn the voltage regulators on using power control instruction.
When REF = "Low"
Rb
V0 = ( 1 +
) x VEV --- (2)
Ra
VEV = VREF - nα (n = 0, 1, 2, ... 30, 31)
α = VREF / 150
Table 15. Electronic Contrast Control Register
No.
d7
d6
d5
d4
d3
d2
d1
d0
nα
α
V0
Contrast
1
-
-
-
0
0
0
0
0
0α (default)
Maximum
High
2
-
-
-
0
0
0
0
1
1α
.
.
3
-
-
-
0
0
0
1
0
2α
.
.
4
-
-
-
0
0
0
1
1
3α
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
31
-
-
-
1
1
1
1
0
30 α
.
.
32
-
-
-
1
1
1
1
1
31α
Minimum
Low
NOTE:
1. "-": Don’t care
42
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Rb
VOUT
VR
V0
_
+
Ra
VREF
+
VEV
Inside Chip
-
VSS
GND
Figure 17. Electronic Contrast Control Circuit
The voltage rage of the V5 output can be adjusted by changing the built-in resister ratio (1 + Rb / Ra) by
command. Reference values are shown in table 16.
Table 16. V0 Voltage Regulating Built-in Resister Ratio Set Values (Reference Values)
Command
IR1
IR0
0
0
1
1
0
1
0
1
(1+Rb / Ra)
V0
2.81
3.27
3.50
3.00
5.60V
6.54V
7.00V
6.00V
43
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
VOLTAGE GENERATOR CIRCUIT
VDD
VDD
C1
+
C1
CAP1+
CAP1CAP2+
CAP2-
C1
VOUT
VR
Rb
Ra
GND
C2
C2
C2
C2
C2
- +
V0
V1
V2
V3
V4
VSS
GND
C1: 1 ~ 4.7uF
C2: 0.1uF
Figure 18. When Built-in Power Supply is used (VR, VF, VC = 1, 1, 1)
VDD
VDD
External
Power
Supply
GND
VDD
VDD
CAP1+
CAP1CAP2+
CAP2VOUT
VDD
VDD
CAP1+
CAP1CAP2+
CAP2VOUT
CAP1+
CAP1CAP2+
CAP2VOUT
VR
VR
VR
Rb
Ra
GND
C2
C2
C2
C2
C2
-
+
External
Power
Supply
V0
V1
V2
V3
V4
VSS
-
+
V0
V1
V2
V3
V4
VSS
GND
GND
(VR, VF, VC = 1, 1, 0)
External
Power
Supply
V0
V1
V2
V3
V4
VSS
GND
(VR, VF, VC = 0, 1, 0)
(VR, VF, VC = 0, 0, 0)
All capacitor is C2.
C2: 0.1 to 4.7uF
Figure 19. When External Power Supply is used
44
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
MPU INTERFACE
VDD
VDD
VCC
A0
A1-A7
IORQ
RS
Decoder
PS
CSB
KS0094
RD
MPU
VDD
MI
E_RD
WR
RW_WR
VDD
D0-D7
GND
DB[0:7]
RES
RESETB
IF
VSS
RESETB
Figure 20. Parallel Interfacing with 8080-series Microprocessors
VDD
VDD
VCC
A1-A7
VMA
Decoder
PS
CSB
KS0094
MI
RW_WR
R/W
MPU
VDD
RS
A0
E_RD
E
VDD
DB[0:7]
D0-D7
GND
RES
RESETB
IF
VSS
RESETB
Figure 21. Parallel Interfacing with 6800-series Microprocessors
45
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
VDD
VCC
PORT4
RS
PORT3
CSB
VDD
VDD
or VSS
KS0094
MPU
GND
PORT1
SCL(DB6)
PORT2
SI(DB7)
RES
RESETB
MI
IF
E_RD
RW_WR
PS
VSS
RESETB
Figure 22. Clock Synchronized Serial Interfacing with any Microprocessors
46
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
APPLICATION INFORMATION FOR LCD PANEL
Chip Bottom & Lower View (CS bit = "0", DIRS = "0")
SEG80
SEG79
SEG78
BOTTOM VIEW
SEG77
................................................
SEG76
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
C O M I1
C O M 16
C O M 15
C O M 14
C O M 13
C O M 12
C O M 11
C O M 10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COMI1
C O M I2
C O M32
C O M31
C O M30
C O M29
C O M28
C O M27
C O M26
C O M25
C O M24
C O M23
C O M22
C O M21
C O M20
C O M19
C O M18
COM17
C O M I2
Figure 23. Chip Bottom & Lower View (CS bit = "0", DIRS = "0")
47
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Chip Bottom & Upper View (CS bit = "1", DIRS = "1")
BOTTOM VIEW
SEG1
SEG2
SEG3
SEG4
................................................
SEG5
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
C O M I2
C O M17
C O M18
C O M19
C O M20
C O M21
C O M22
C O M23
C O M24
C O M25
C O M26
C O M27
C O M28
C O M29
C O M30
C O M31
COM32
C O M I2
C O M I1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
C O M10
C O M11
C O M12
C O M13
C O M14
C O M15
COM16
C O M I1
Figure 24. Chip Bottom & Upper View (CS bit = "1", DIRS = "1")
48
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Chip Top & Lower View (CS bit = "0", DIRS = "1")
SEG1
SEG2
SEG3
TOP
SEG4
................................................
SEG5
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
C O M I2
C O M 32
C O M 31
C O M 30
C O M 29
C O M 28
C O M 27
C O M 26
C O M 25
C O M 24
C O M 23
C O M 22
C O M 21
C O M 20
C O M 19
C O M 18
COM17
COMI2
VIEW
C O M I1
C O M16
C O M15
C O M14
C O M13
C O M12
C O M11
C O M10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
C O M I1
Figure 25. Chip Top & Lower View (CS bit = "0", DIRS = "1")
49
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Chip Top & Upper View (CS bit = "1", DIRS = "0")
TOP
VIEW
SEG80
SEG79
SEG77
SEG76
................................................
SEG75
SEG9
SEG10
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
C O M I1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
C O M10
C O M11
C O M12
C O M13
C O M14
C O M15
COM16
C O M I1
C O M I2
C O M17
C O M18
C O M 19
C O M20
C O M21
C O M22
C O M23
C O M24
C O M25
C O M26
C O M27
C O M28
C O M29
C O M30
C O M31
COM32
C O M I2
Figure 26. Chip Top & Upper View (CS bit = "0", DIRS = "1")
50
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
FRAME FREQUENCY
1/18 Duty (2-line Mode)
1-line selection period
1 2
.............
17 18 1 2
.............
17 18 1 2 . . . . . . . . . .
V0
V1
COM1
V4
VSS
1 Frame
1 Frame
1-line Selection Period = 16 Clocks
One Frame
= 16 x 18 x 44.44 us = 12.8 ms (1 Clock = 44.44 us at f OSC = 45 kHz)
Frame Frequency
= 1 / 12.8 ms = 78.1 Hz
1/26 Duty (3-line Mode)
1-line selection period
1 2
.............
25 26 1 2
.............
25 26 1 2 . . . . . . . . . .
V0
V1
COM1
V4
VSS
1 Frame
1 Frame
1-line Selection Period = 16 Clocks
One Frame
= 16 x 26 x 29.63 us = 12.33 ms (1 Clock = 29.63 us at f OSC = 45 kHz)
Frame Frequency
= 1 / 12.33 ms = 81.1 Hz
1/34 Duty (4-line Mode)
1-line selection period
1 2
.............
33 34 1 2
.............
33 34 1 2 . . . . . . . . . .
V0
V1
COM1
V4
VSS
1 Frame
1 Frame
1-line Selection Period = 16 Clocks
One Frame
= 16 x 34 x 22.2 us = 11.97 ms (1 Clock = 22.2 us at f OSC = 45 kHz)
Frame Frequency
= 1 / 11.97 ms = 83 Hz
51
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
MAXIMUM ABSOLUTE RATINGS
Table 17. Maximum Absolute Ratings
Characteristic
Symbol
Value
Unit
Power supply voltage (1)
VDD
-0.3 to + 7.0
V
Power supply voltage (2)
VOUT, V0
-0.3 to + 9.0
V
Power supply voltage (3)
V1, V2, V3, V4
-0.3 to V0
V
Input voltage
VIN
-0.3 to VDD+0.3
V
Operating temperature
TOPR
-30 to +85
o
Storage temperature
TSTG
-55 to +125
o
NOTE1: All the voltage levels are based on VSS = 0V.
NOTE2: Voltage greater than above may damage the circuit
Voltage level : VOUT ≥ V0 ≥ VDD ≥ VSS
Voltage level : V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
52
C
C
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 18. DC Characteristics
(VDD = 2.2V to 3.6V, Ta = -30 to +85 oC)
Min.
Typ.
Max.
Unit
Item
Symbol
Condition
Operating voltage
VDD
-
2.2
-
3.6
IDD1
Display operation
VLCD=6V without load
No access from MPU
-
-
95
IDD2
Access operation from MPU
(Fcyc = 200kHZ)
-
-
500
IDDS1
Sleep operation without load
oscillator OFF, power save ON
-
-
5
VIH
-
0.8VDD
VDD
VIL
-
Vss
0.2VDD
VOH
IOH = -1mA, VDD =2.4V
VDD0.4
Supply current
(VDD = 3V,
o
Ta = 25 C)
Input voltage
V
uA
V
Output voltage
V
VOL
IOL = 1mA, VDD =2.4V
Input leakage current
IIZ
VIN = 0V to VDD
-1
Output leakage current
IOZ
VIN = 0V to VDD
-3
RCOM
Io = ±50uA
-
-
5
RSEG
Io = ±50uA
-
-
10
VDD = 3V, Ta = 25 oC
(4-line mode)
70
85
100
Hz
f FR
Conversion
efficiency
VEF
RL = ∞
95
99
-
%
Output
voltage
VOUT
Ta = 25 oC, C = 1uF
7.5
8.0
8.5
V
Voltage regulator
reference voltage
VREF
Ta = 25 oC
1.94
2.0
2.06
LCD driving voltage
VLCD
VLCD = V0 - Vss
3.0
-
7.0
RON resistance
Frame frequency
(Internal OSC)
Voltage
converter
0.4
-
1
uA
3
uA
kΩ
V
53
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
Parallel Write Interface (68 Mode)
(VDD = 2.2V to 3.6V, Ta = -30 to +85 oC)
Characteristic
Symbol
Min.
Typ.
Max.
E_RD cycle time
tC
650
-
-
Pulse rise / fall time
tR,tF
-
-
25
E_RD pulse width high
tWH
450
-
-
E_RD pulse width low
tWL
150
-
-
RS and CSB setup time
tSU1
60
-
-
RS and CSB hold time
tH1
30
-
-
DB setup time
tSU2
100
-
-
DB hold time
tH2
50
-
-
RS,CSB
tS U 1
tH 1
RW_WR
tW H
tW L
tF
E_RD
tR
DB0~DB7
tS U 2
Valid
t
H2
Data
tC
Figure 27. Write Timing Diagram (68-series)
54
Unit
ns
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Parallel Read Interface (68 Mode)
(VDD = 2.2V to 3.6V, Ta = -30 to +85 oC)
Characteristic
Symbol
Min.
Typ.
Max.
E_RD cycle time
tC
650
-
-
Pulse rise / fall time
tR,tF
-
-
25
E_RD pulse width high
tWH
450
-
-
E_RD pulse width low
tWL
150
-
-
RS and CSB setup time
tSU
60
-
-
RS and CSB hold time
tH
30
-
-
DB output delay time
tD
100
-
-
DB output hold time
tDH
50
-
-
Unit
ns
RS,CSB
t SU
tH
RW_WR
tW H
tW L
tF
E_RD
tR
DB0~DB7
tD
tDH
Valid
Data
tC
Figure 28. Read Timing Diagram (68-series)
55
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Parallel Write Interface (80 Mode)
(VDD = 2.2V to 3.6V, Ta = -30 to +85 oC)
Characteristic
Symbol
Min.
Typ.
Max.
RW_WR cycle time
tC
650
-
-
Pulse rise / fall time
tR,tF
-
-
25
RW_WR pulse width high
tWH
150
-
-
RW_WR pulse width low
tWL
450
-
-
RS and CSB setup time
tSU1
60
-
-
RS and CSB hold time
tH1
30
-
-
DB setup time
tSU2
100
-
-
DB hold time
tH2
50
-
-
R S ,CSB
tS U 1
tH 1
E_RD
tW L
tW H
tR
RW_WR
tF
DB0~DB7
tS U 2
Valid
t H2
Data
tC
Figure 29. Write Timing Diagram (80-series)
56
Unit
ns
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 0.4
KS0094
Parallel Read Interface (80 Mode)
(VDD = 2.2V to 3.6V, Ta = -30 to +85 oC)
Characteristic
Symbol
Min.
Typ.
Max.
E_RD cycle time
tC
650
-
-
Pulse rise / fall time
tR,tF
-
-
25
E_RD pulse width high
tWH
150
-
-
E_RD pulse width low
tWL
450
-
-
RS and CSB setup time
tSU
60
-
-
RS and CSB hold time
tH
30
-
-
DB output delay time
tD
100
-
-
DB output hold time
tDH
50
-
-
Unit
ns
R S ,CSB
t SU
tH
RW_WR
tW L
tW H
tR
E_RD
tF
DB0~DB7
tD
tDH
Valid
Data
tC
Figure 30. Read Timing Diagram (80-series)
57
KS0094
PRELIMINARY SPEC. VER. 0.4
34 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Clock Synchronized Serial Mode
(VDD = 2.2V to 3.6V, Ta = -30 to +85 oC)
Characteristic
Symbol
Min.
Typ.
Max.
SCL clock cycle time
tC
1000
-
-
Pulse rise / fall time
tR,tF
-
-
25
SCL clock width (high, low)
tW
300
-
-
CSB setup time
tSU1
150
-
-
CSB hold time
tH1
700
-
-
RS data setup time
tSU2
50
-
-
RS data hold time
tH2
300
-
-
SI data setup time
tSU3
50
-
-
SI data hold time
tH3
50
tC
tSU1
tH 1
CSB
tW
tR
SCL
tW
tF
tS U 2
tH 2
RS
tSU3
tH3
SI
Figure 31. Clock Synchronized Serial Interface Mode Timing Diagram
58
Unit
ns