SAMSUNG KS0672

KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
August. 1999.
Ver. 0.0
Prepared by:
Myoung-Sik, Suh
mail to: [email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672 Specification Revision History
Version
0.0
2
Content
Original
Date
Aug.1999
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
CONTENTS
INTRODUCTION ................................................................................................................................................. 4
FEATURES ......................................................................................................................................................... 4
BLOCK DIAGRAM .............................................................................................................................................. 5
PIN ASSIGNMENTS............................................................................................................................................ 6
PIN DESCRIPTIONS ........................................................................................................................................... 7
OPERATION DESCRIPTION............................................................................................................................... 8
DISPLAY DATA TRANSFER ............................................................................................................................ 8
EXTENSION OF OUTPUT ............................................................................................................................... 8
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE .................................................. 8
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15
RECOMMENDED OPERATION CONDITIONS.................................................................................................. 15
DC CHARACTERISTICS................................................................................................................................... 16
AC CHARACTERISTICS................................................................................................................................... 17
WAVEFORMS ................................................................................................................................................... 18
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD ........................ 19
3
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The KS0672 is a 384 channel output, TFT-LCD source driver for 64 gray scale displays. Data input is based on
digital input consisting of 6 bits by 6 dots, which can realize a full-color display of 260,000 colors by output of 64
values gamma-corrected.
This device has an internal D/A (Digital-to-Analog) converter for each output and 10 (5-by-2) external power
supplies. Because the output dynamic range is as large as 6.6 - 12.6 Vp-p, it is unnecessary to operate level
inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a
single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the
even output pins.
KS0672 can be adopted to larger panel, and SHL (Shift Direction Selection) pin makes use of the LCD panel
connection conveniently. Maximum operation clock frequency is 65 MHz at a 2.7 V logic operation. It can be
applied to the TFT-LCD panel of XGA, SXGA standards.
FEATURES
•
TFT active matrix LCD source driver LSI
•
64 gray scale is possible through 10 (5 by 2) external power supply and D/A converter
•
Both dot inversion display and N-line inversion display are possible
•
CMOS level input
•
Compatible with gamma-correction
•
Input data inversion function (DATPOL)
•
Logic supply voltage: 2.7 - 3.6 V
•
LCD driver supply voltage: 7.0 - 13.0 V
•
Output dynamic range: 6.6 - 12.6 Vp-p
•
Maximum operating frequency: fMAX = 65 MHz (internal data transmission rate at 2.7 V operation)
•
Output: 384 outputs
•
TCP
4
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
BIAS
Output Buffer
10
D/A Converter
Y001
Y002
Y003
Y382
Y383
Y384
BLOCK DIAGRAM
TEST
POL
VGMA1 VGMA10
6
6
6
6
6
6
6
6
Data Latch
CLK1
6
6
6
Data Register
D00 - D05
6
D10 - D15
6
D20 - D25
6
D30 - D35
6
D40 - D45
6
D50 - D55
6
Data Control
DATPOL
CLK2
6
36
64bit Shift Register
DIO2
SHL
DIO1
Figure 1. KS0672 Block Diagram
5
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001
Y002
Y003
(Top View)
KS0672
Y004
Y381
Y382
Y383
Y384
Figure 2. KS0672 Pin Assignments
6
VSS2
VDD2
TEST
D00
D01
D02
D03
D04
D05
D10
D11
D12
D13
D14
D15
D20
D21
D22
D23
D24
D25
DIO1
DATPOL
VSS1
CLK2
VDD1
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VGMA9
VGMA10
DIO2
D30
D31
D32
D33
D34
D35
D40
D41
D42
D43
D44
D45
D50
D51
D52
D53
D54
D55
CLK1
POL
SHL
VDD2
VSS2
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
PIN DESCRIPTIONS
Symbol
Pin Name
Description
VDD1
Logic power supply
2.7 - 3.6 V
VDD2
Driver power supply
7.0 - 13.0 V
VSS1
Logic ground
Ground (0 V)
VSS2
Driver ground
Ground (0 V)
Y1 - Y384
Driver outputs
The D/A converted 64 gray scale analog voltage is output.
D0<0:5>
- D5<0:5>
Display data input
SHL
Shift direction control
input
DIO1
Start pulse input / output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
DIO2
Start pulse input / output
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
DATPOL
Data inversion input
The display data is input with a width of 36 bits,
gray-scale data (6 bits) by 6 dots (R,G,B) DX0: LSB, DX5: MSB
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1 → Y384, DIO2 output
SHL = L: DIO2 input, Y384 → Y1, DIO1 output
DATPOL = L: Display data is not inverted
DATPOL = H: Display data is inverted
POL
Polarity input
POL = H: The reference voltage for odd number outputs are VGMA1 –
VGMA5 and those for even number outputs are VGMA6 – VGMA10.
POL = L: The reference voltage for odd number outputs are VGMA6 –
VGMA10 and those for even number outputs are VGMA1 – VGMA5.
CLK2
Shift clock input
Refer to the shift register's shift clock input. the display data is loaded
to the data register at the rising edge of CLK2.
CLK1
VGMA1
–
VGMA10
TEST
Latch input
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start
pulse (DIO1, DIO2) and blanking period" of the switching characteristic
waveform. Outputs the G/S data at falling edge.
Input the gamma corrected power supplies from external source.
Gamma corrected power VDD2 > VGMA1 > VGMA2 > ……… > VGMA9 > VGMA10 > VSS2
supplies
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
Test input
TEST = L: Normal operation mode
TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15kΩ)
7
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the
data of 384 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data
is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is
provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
(1) SHL = "L"
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins
except DIO1 and DIO2 are connected together in each device.
(2) SHL = "H"
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins
except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power
supplies (VGMA1 - VGMA10). Besides, to be able to deal with dot line inversion when mounted on a singleside, gradation voltages with different polarity can be output to the odd number output pins and the even
number output pins. Among 5-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity
with respect to the common voltage, for the respective 5 gamma corrected voltages of VGMA1 - VGMA5 and
VGMA6 - VGMA10.
SHL = H
OUTPUT
Y1
Y2
Y3
......
-
First
DATA
D00 - D05 D10 - D15 D20 - D25
......
Y2
......
Y382
Y383
Y384
Last
D30 - D35 D40 - D45 D50 - D55
SHL = L
OUTPUT
Y1
Y3
-
Last
DATA
D00 - D05 D10 - D15 D20 - D25
Y382
Y383
First
......
D30 - D35 D40 - D45 D50 - D55
Figure 3. Relationship between Shift Direction and Output Data
8
Y384
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
VDD2
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VCOM
VGMA6
VGMA7
VGMA8
VGMA9
VGMA10
VSS2
00H
08H
10H
18H
20H
28H
30H
38H
3FH Input data
Figure 4. Gamma Correction Curve
9
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Table 1. Resistor Strings (R0 - R62, unit: Ω )
10
Name
Value
Name
Value
Name
Value
Name
Value
R0
500
R16
330
R32
175
R48
210
R1
500
R17
330
R33
175
R49
220
R2
500
R18
330
R34
170
R50
230
R3
500
R19
320
R35
170
R51
240
R4
500
R20
300
R36
165
R52
250
R5
500
R21
280
R37
165
R53
260
R6
500
R22
270
R38
165
R54
270
R7
500
R23
260
R39
165
R55
290
R8
500
R24
250
R40
170
R56
300
R9
500
R25
240
R41
170
R57
310
R10
500
R26
230
R42
170
R58
320
R11
500
R27
220
R43
175
R59
340
R12
450
R28
210
R44
175
R60
340
R13
450
R29
200
R45
175
R61
340
R14
400
R30
190
R46
180
R62
340
R15
370
R31
180
R47
200
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
Table 2. Relationship between Input Data and Output Voltage Value
Input data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
G/S
Output voltage
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VGMA1
VGMA1 + (VGMA2 - VGMA1) × 500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 1000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 1500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 2000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 2500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 3000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 3500 / 7670
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VGMA1 + (VGMA2 - VGMA1) × 4000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 4500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 5000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 5500 / 7670
VGMA1 + (VGMA2 - VGMA1) × 6000 / 7670
VGMA1 + (VGMA2 - VGMA1) × 6450 / 7670
VGMA1 + (VGMA2 - VGMA1) × 6900 / 7670
VGMA1 + (VGMA2 - VGMA1) × 7300 / 7670
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VGMA2
VGMA2 + (VGMA3 - VGMA2) × 330 / 4140
VGMA2 + (VGMA3 - VGMA2) × 660 / 4140
VGMA2 + (VGMA3 - VGMA2) × 990 / 4140
VGMA2 + (VGMA3 - VGMA2) × 1310 / 4140
VGMA2 + (VGMA3 - VGMA2) × 1610 / 4140
VGMA2 + (VGMA3 - VGMA2) × 1890 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2160 / 4140
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
VGMA2 + (VGMA3 - VGMA2) × 2420 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2670 / 4140
VGMA2 + (VGMA3 - VGMA2) × 2910 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3140 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3360 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3570 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3770 / 4140
VGMA2 + (VGMA3 - VGMA2) × 3960 / 4140
NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5
11
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
12
DX5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
G/S
Output voltage
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
VGMA3
VGMA3 + (VGMA4 - VGMA3) × 175 / 2765
VGMA3 + (VGMA4 - VGMA3) × 350 / 2765
VGMA3 + (VGMA4 - VGMA3) × 520 / 2765
VGMA3 + (VGMA4 - VGMA3) × 690 / 2765
VGMA3 + (VGMA4 - VGMA3) × 855 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1020 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1185 / 2765
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VGMA3 + (VGMA4 - VGMA3) × 1350 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1520 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1690 / 2765
VGMA3 + (VGMA4 - VGMA3) × 1860 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2035 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2210 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2385 / 2765
VGMA3 + (VGMA4 - VGMA3) × 2565 / 2765
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VGMA4
VGMA4 + (VGMA5 - VGMA4) × 210 / 4260
VGMA4 + (VGMA5 - VGMA4) × 430 / 4260
VGMA4 + (VGMA5 - VGMA4) × 660 / 4260
VGMA4 + (VGMA5 - VGMA4) × 900 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1150 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1410 / 4260
VGMA4 + (VGMA5 - VGMA4) × 1680 / 4260
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
VGMA4 + (VGMA5 - VGMA4) × 1970 / 4260
VGMA4 + (VGMA5 - VGMA4) × 2270 / 4260
VGMA4 + (VGMA5 - VGMA4) × 2580 / 4260
VGMA4 + (VGMA5 - VGMA4) × 2900 / 4260
VGMA4 + (VGMA5 - VGMA4) × 3240 / 4260
VGMA4 + (VGMA5 - VGMA4) × 3580 / 4260
VGMA4 + (VGMA5 - VGMA4) × 3920 / 4260
VGMA5
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
G/S
Output voltage
VL0
VL1
VL2
VL3
VL4
VL5
VL6
VL7
VGMA10
VGMA10 + (VGMA9 - VGMA10) × 500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 1000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 1500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 2000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 2500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 3000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 3500 / 7670
VL8
VL9
VL10
VL11
VL12
VL13
VL14
VL15
VGMA10 + (VGMA9 - VGMA10) × 4000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 4500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 5000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 5500 / 7670
VGMA10 + (VGMA9 - VGMA10) × 6000 / 7670
VGMA10 + (VGMA9 - VGMA10) × 6450 / 7670
VGMA10 + (VGMA9 - VGMA10) × 6900 / 7670
VGMA10 + (VGMA9 - VGMA10) × 7300 / 7670
VL16
VL17
VL18
VL19
VL20
VL21
VL22
VL23
VGMA9
VGMA9 + (VGMA8 - VGMA9) × 330 / 4140
VGMA9 + (VGMA8 - VGMA9) × 660 / 4140
VGMA9 + (VGMA8 - VGMA9) × 990 / 4140
VGMA9 + (VGMA8 - VGMA9) × 1310 / 4140
VGMA9 + (VGMA8 - VGMA9) × 1610 / 4140
VGMA9 + (VGMA8 - VGMA9) × 1890 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2160 / 4140
VL24
VL25
VL26
VL27
VL28
VL29
VL30
VL31
VGMA9 + (VGMA8 - VGMA9) × 2420 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2670 / 4140
VGMA9 + (VGMA8 - VGMA9) × 2910 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3140 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3360 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3570 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3770 / 4140
VGMA9 + (VGMA8 - VGMA9) × 3960 / 4140
NOTE: VGMA6 > VGMA7 > VGMA8 > VGMA9 > VGMA10 > VSS2
13
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
14
DX5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
G/S
Output voltage
VL32
VL33
VL34
VL35
VL36
VL37
VL38
VL39
VGMA8
VGMA8 + (VGMA7 - VGMA8) × 175 / 2765
VGMA8 + (VGMA7 - VGMA8) × 350 / 2765
VGMA8 + (VGMA7 - VGMA8) × 520 / 2765
VGMA8 + (VGMA7 - VGMA8) × 690 / 2765
VGMA8 + (VGMA7 - VGMA8) × 855 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1020 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1185 / 2765
VL40
VL41
VL42
VL43
VL44
VL45
VL46
VL47
VGMA8 + (VGMA7 - VGMA8) × 1350 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1520 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1690 / 2765
VGMA8 + (VGMA7 - VGMA8) × 1860 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2035 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2210 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2385 / 2765
VGMA8 + (VGMA7 - VGMA8) × 2565 / 2765
VL48
VL49
VL50
VL51
VL52
VL53
VL54
VL55
VGMA7
VGMA7 + (VGMA6 - VGMA7) × 210 / 4260
VGMA7 + (VGMA6 - VGMA7) × 430 / 4260
VGMA7 + (VGMA6 - VGMA7) × 660 / 4260
VGMA7 + (VGMA6 - VGMA7) × 900 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1150 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1410 / 4260
VGMA7 + (VGMA6 - VGMA7) × 1680 / 4260
VL56
VL57
VL58
VL59
VL60
VL61
VL62
VL63
VGMA7 + (VGMA6 - VGMA7) × 1970 / 4260
VGMA7 + (VGMA6 - VGMA7) × 2270 / 4260
VGMA7 + (VGMA6 - VGMA7) × 2580 / 4260
VGMA7 + (VGMA6 - VGMA7) × 2900 / 4260
VGMA7 + (VGMA6 - VGMA7) × 3240 / 4260
VGMA7 + (VGMA6 - VGMA7) × 3580 / 4260
VGMA7 + (VGMA6 - VGMA7) × 3920 / 4260
VGMA6
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)
Parameter
Symbol
Ratings
Unit
Logic supply voltage
VDD1
-0.3 to 5.5
V
Driver supply voltage
VDD2
-0.3 to 15.0
V
VGMA1 - 5
0.4 VDD2 to VDD2 + 0.3
VGMA6 - 10
-0.3 to 0.6 VDD2
Others
-0.3 to VDD1 + 0.3
DIO1, 2
-0.3 to VDD1 + 0.3
Y1 - Y384
-0.3 to VDD2 + 0.3
Operating power dissipation
Pd
200
mW
Operation temperature
Top
-20 to 75
°C
Storage temperature
Tstg
-55 to 125
°C
Input voltage
Output voltage
V
V
CAUTIONS:
If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently
destroyed. These are stress ratings only, and functional operation of the device at these or any other
condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Turn on power order: VDD1 → control signal input → VDD2 → VGMA1 - VGMA10
Turn off power order: VGMA1 - VGMA10 → VDD2 → control signal input → VDD1
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = -20 to 75 ° C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Logic supply voltage
VDD1
2.7
3.0
3.6
V
Driver supply voltage
VDD2
7.0
9.0
13.0
V
VGMA1 - VGMA5
0.5 VDD2
-
VDD2 - 0.2
V
VGMA6 - VGMA10
VSS2 + 0.2
-
0.5 VDD2
V
Driver part output voltage
Vyo
VSS2 + 0.2
-
VDD2 - 0.2
V
Maximum clock frequency
fmax
65
MHz
Output load capacitance
CL
200
pF / PIN
Gamma corrected voltage
VDD1 = 2.7 V
-
-
15
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
DC CHARACTERISTICS
Table 5. DC Characteristics (Ta = -20 to 75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 7 to 13 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
High level input voltage
VIH
0.7 VDD1
-
VDD1
Low level input voltage
VIL
0
-
0.3 VDD1
Input leakage current
IL
SHL, CLK2, D00 - D55,
CLK1, POL, DATPOL,
DIO1 (DIO2)
-1
-
1
High level output voltage
VOH
DIO1 (DIO2),
IO = -1.0 mA
VDD1 - 0.5
-
-
Low level output voltage
VOL
DIO1 (DIO2),
IO = +1.0 mA
-
-
0.5
Resistor
R0 - R62
Refer to Table 1. Resistor
Strings
Rn × 0.7
IVOH
VDD2 = 9.0 V,
Vx = 2.5 V, Vyo = 8.5 V
-
IVOL
VDD2 = 9.0 V,
Vx = 6.5 V, Vyo = 0.5 V
Driver output current
Output voltage deviation
∆VO
V
µA
V
Rn × 1.3
Ω
-0.5
-0.3
mA
0.3
0.5
-
mA
VSS2 + 0.2 V to
VDD2 - 1.5 V
-
±10
±20
VDD2 - 1.5 V to
VDD2 - 0.2 V
-
±15
±25
Output RMS voltage
deviation
dVrms(2)
Input data: 00H to 3FH
-
±5
±15
Output voltage range
Vyo
Input data: 00H to 3FH
VSS2 + 0.2
-
VDD2 - 0.2
Logic part dynamic
current
IDD1
VDD1 = 3.0 V (3)
-
4.0
5.5
IDD2
VDD1 = 3.0 V,
VDD2 = 9.0 V,
VGMA1 = 8.5 V,
VGMA5 = 5.0 V,
VGMA6 = 4.0 V,
(3) (4)(5)
VGMA10 = 0.5 V
-
4.0
7.0
Driver part dynamic
current
Unit
mV
V
mA
NOTES:
1. Vyo is the output voltage of analog output pins Y1 to Y384. Vx is the voltage applied to analog output pins Y1 to Y384.
2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale.
3. CLK1 period is defined to be 20 µs at fCLK2 = 33 MHz, data pattern = 101010 , (checkerboard pattern), Ta = 25 °C
4. The current consumption per driver when XGA single-sided mounting (8 drivers) is connected in cascade
5. No load
16
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
AC CHARACTERISTICS
Table 6. AC Characteristics (Ta = -20 to 75 °C, VDD2 = 7 to 13 V, VDD1 = 2.7 to 3.6 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Clock pulse width
PWCLK
-
15
-
-
Clock pulse low period
PWCLK(L)
-
5
-
-
Clock pulse high period
PWCLK(H)
-
5
-
-
tSETUP1
(1)
3/5
-
-
tHOLD1
(1)
0/2
-
-
Start pulse setup time
tSETUP2
(1)
3/5
-
-
Start pulse hold time
tHOLD2
(1)
0/2
-
-
DATPOL-CLK2 setup
time
tSETUP4
(1)
3/5
-
-
DATPOL-CLK2 hold time
tHOLD4
(1)
0/2
0
-
Start pulse delay time
tPLH1
CL = 20 pF
-
-
12
CLK1 setup time
tSETUP3
-
1
-
-
Driver output delay time1
tPHL1
(2),(4)
-
-
5
Driver output delay time2
tPHL2
(3),(4)
-
-
10
CLK1 pulse high period
PWCLK1
-
0.2
-
2
Data invalid period
tINV
DIO1 (2) ↑ → CLK2↑
Last data timing
tLDT
-
1
-
-
CLK2
period
CLK1-CLK2 time
tCLK1–CLK2
CLK1↑ → CLK2↑
6
-
-
ns
POL-CLK1 time
tPOL–CLK1
POL↑ or ↓ → CLK1↑
5
-
-
ns
Data setup time
Data hold time
Unit
ns
CLK2
period
µs
1
NOTES:
1. Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1 / VIH = 0.5 VDD1, VIL = 0.5 VDD1)
2. The value is specified when the drive voltage value reaches the target output voltage level of 90%
3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
4. Yout Load Condition
10kΩ
20kΩ
20kΩ
YOUT
30pF
30pF
30pF
VCOM = 0.5VDD2
Figure 5. Yout Load Condition
17
18
Figure 6. Waveforms
POL
tPOL-CLK1
LAST
DATA
tLDT
tHOLD4
DXX
HI-Z
PWCLK1
tHOLD2
tSETUP4
tHOLD1
PWCLK(L)
0.5VDD1
tSETUP3
tSETUP2
INVALID DATA
1st
tSETUP1
1st
DATA
tINV
CLK1
CLK2
Y(1:384)
CLK1
DIO2 output
(DIO1 output)
DIO1 input
(DIO2 input)
DATPOL1
DATPOL2
DXX
CLK2
PWCLK
PWCLK(H)
Target output voltage
Target output voltage 90%
tPLH1
LAST-1 LAST
INVALID DATA
tPHL2
tCLK1-CLK2
tPHL1
VIH
VIL
KS0672
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
WAVEFORMS
Y2N:even
number output
Y2N-1:odd
number output
POL
CLK1
DXX
CLK1
DIO1 input
(DIO2 input)
CLK2
Last data
N-1th
DATA
Nth
DATA
VGMA1 - VGMA5
VGMA6 - VGMA10
First data in
the next line
2nd
DATA
VGMA1 - VGMA5
VGMA6 - VGMA10
HI-Z
1st
DATA
1CLK2
VGMA1 - VGMA5
HI-Z
blanking time = Min. 3CLK2
INVALID DATA
1CLK2(Min.)
VGMA6 - VGMA10
HI-Z
tLDT
0.5VDD1
HI-Z
6 BIT 384 CHANNEL TFT-LCD SOURCE DRIVER
KS0672
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND
BLANKING PERIOD
Figure 7. Waveforms
19