SAMSUNG KS0713

KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
January.2000
Ver. 4.0
Prepared by:
Jae-Su, Ko
[email protected]
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
KS0713 Specification Revision History
Version
2.0
2.1
Content
Neglect the more past version than version 2.0
fOSC = 16kHz (Typ.) → 22kHz (Typ.): For removing flicker phenomenon
Temperature coefficient (when TEMPS = L): -0.0%/°C → -0.05%/°C
Date
Nov.1998
Nov.1998
Modified some syntax errors
3.0
Voltage regulator reference voltage [VREF]: TBD → 2.0
Nov.1998
Modified voltage regulator block of “Functional Description”
3.1
3.2
3.3
2
VLCD absolute maximum rating: 15.0V → 17.0V
Power consumption: 100µA → 80µA
Oscillator frequency (1): 19 (Min.) →17 (Min.), 25 (Max.) →27 (Max.)
Oscillator frequency (2): 22 (Min.) →20 (Min.), 28 (Max.) →30 (Max.)
Modified Y-axis values of “Pad Center Coordinates”
Modified the contents of “Referential Instruction Setup Flow”
3.4
Word-processor version change
Apr.1999
3.5
Modified error: pad No.113 (COMS) Y Coordinate: -1210 → -1140 (after)
Oct.1999
4.0
Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V
Jan.2000
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................1
FEATURES ..........................................................................................................................................................1
BLOCK DIAGRAM ...............................................................................................................................................3
PAD CONFIGURATION .......................................................................................................................................4
PAD CENTER COORDINATES............................................................................................................................5
PIN DESCRIPTION ..............................................................................................................................................8
POWER SUPPLY..........................................................................................................................................8
LCD DRIVER SUPPLY..................................................................................................................................8
SYSTEM CONTROL .....................................................................................................................................9
MICROPROCESSOR INTERFACE .............................................................................................................11
LCD DRIVER OUTPUTS .............................................................................................................................13
FUNCTIONAL DESCRIPTION............................................................................................................................14
MICROPROCESSOR INTERFACE .............................................................................................................14
DISPLAY DATA RAM (DDRAM) ..................................................................................................................18
LCD DISPLAY CIRCUITS............................................................................................................................21
LCD DRIVER CIRCUIT ...............................................................................................................................23
POWER SUPPLY CIRCUITS ......................................................................................................................24
REFERECE CIRCUIT EXAMPLES..............................................................................................................31
RESET CIRCUIT .........................................................................................................................................33
INSTRUCTION DESCRIPTION...........................................................................................................................34
SPECIFICATIONS..............................................................................................................................................48
ABSOLUTE MAXIMUM RATINGS...............................................................................................................48
DC CHARACTERISTICS.............................................................................................................................49
REFERENCE DATA....................................................................................................................................52
AC CHARACTERISTICS .............................................................................................................................54
REFERENCE APPLICATIONS...........................................................................................................................58
MICROPROCESSOR INTERFACE .............................................................................................................58
CONNECTIONS BETWEEN KS0713 AND LCD PANEL..............................................................................59
TCP PIN LAYOUT (SAMPLE)......................................................................................................................64
3
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INTRODUCTION
The KS0713 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 65
commons and 132 segments driver circuits. This chip is connected directly to a microprocessor, accepts serial or
8-bit parallel display data and stores in an on-chip Display Data RAM of 65 x 132 bits. It provides a high-flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no externally operating clock to minimize power
consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible
to make a display system with the fewest components.
FEATURES
Driver Output Circuits
−
65 common outputs / 132 segment outputs
On-chip Display Data RAM
−
Capacity: 65 x 132 = 8,580 bits
Applicable Duty Ratios
Duty ratio
Applicable LCD bias
Maximum display area
1/65
1/7 or 1/9
65 × 132
1/49
1/6 or 1/8
49 × 132
1/33
1/5 or 1/6
33 × 132
Microprocessor Interface
−
−
8-bit parallel bi-directional interface with 6800-series or 8080-series
Serial interface (only write operation) available
Function Set
−
−
Various instructions sets
H/W, S/W reset capable
Built-in Analog Circuit
−
−
−
−
−
On-chip oscillator circuit
Voltage converter (x2, x3, x4, x5)
Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C)
Voltage follower
Electronic contrast control function (64 steps)
Operating Voltage Range
−
−
Supply voltage (VDD): 2.4 to 3.6 V
LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V
Low Power Consumption
−
−
70 µΑ Typ. (VDD = 3V, x4 boosting, V0 = 11V, internal power supply ON)
10 µΑ Max. (during power save [standby] mode)
Package Type
−
Gold bumped chip or TCP
1
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Series Specifications
Product code
TEMPS pin
Temp. coefficient
KS0713UM-L0CC
0
(VSS connected)
-0.05%/°C
KS0713UM-L4CC
KS0713UM-H0CC
KS0713UM-H4CC
KS0713TB-XX-L0TF
KS0713TB-XX-L4TF
KS0713TB-XX-H0TF
KS0713TB-XX-H4TF
1
(VDD connected)
-0.2%/°C
0
(VSS connected)
-0.05%/°C
-0.2%/°C
470 µm
670 µm
470 µm
670 µm
TCP
1
(VDD connected)
Chip thickness
670 µm
COG
* XX: TCP ordering number
2
Package
470 µm
670 µm
470 µm
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
BLOCK DIAGRAM
COMS
:
COM64
COM33
SEG132
COMMON CONTROLLER
PAGE
I/O
ADDRESS
BUFFER
CIRCUIT
V/R
CIRCUIT
DISPLAY DATA RAM
65 X 132 = 8,580 Bits
LINE
ADDRESS
CIRCUIT
V/C
CIRCUIT
DISPLAY
TIMING
GENERATOR
CIRCUIT
MS
CL
M
FRS
DISP
DUTY0
DUTY1
OSCILLATOR
CLS
COLUMN ADDRESS
CIRCUIT
VOUT
C1C1+
C2C2+
C3C3+
DCDC5B
BSTS
33 COMMON
DRIVER
CIRCUITS
V/F
CIRCUIT
V0
VR
INTRS
TEMPS
SEG131
:
132 SEGMENT
DRIVER CIRCUITS
SEGMENT CONTROLLER
HPMB
SEG130
:
SEG3
SEG2
33 COMMON
DRIVER
CIRCUITS
SEG1
:
COM32
COM1
COMS
VDD
V0
V1
V2
V3
V4
VSS
STATUS REGISTER
INSTRUCTION REGISTER
BUS HOLDER
INSTRUCTION DECODER
MPU INTERFACE (PARALLEL & SERIAL)
DB0
DB1
DB2
DB3
DB4
DB5
DB6(SCLK)
DB7(SID)
MI
RESETB
PS
RW_WR
E_RD
RS
CS2
CS1B
Figure 1. Block Diagram
3
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
PAD CONFIGURATION
148
287
ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð
Y
KS0713
(TOP VIEW)
ððð
324
(0,0)
X
ðððððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððððððð
1
ðððð- - - -ððð
ðððð
288
147
111
110
Figure 2. KS0713 Chip Configuration
Table 1. KS0713 Pad Dimensions
Items
Pad No.
Chip size
-
Pad pitch
X
Y
10860
2920
1 to 110
90
111 to 324
70
1 to 110
56
114
Bumped
111 to 147
108
50
pad size
148 to 287
50
108
288 to 324
108
50
Bumped pad height
1 to 324
COG Align Key Coordinate
30µm 30µm 30µm
µm
17 (Typ.)
108µm
108µm
42µm
30µm
(+5065, +1317)
42µm
108µm
108µm
60µm
(+5060, -1180)
42µm
42µm
(-5060, -1180)
4
Unit
ILB Align Key Coordinate
30µm 30µm 30µm
30µm 30µm 30µm
(-5065, +1302)
Size
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
DUMMY
DUMMY
FRS
M
CL
DISP
VSS
CS1B
CS2
VDD
RESETB
RS
VSS
RW_WR
E_RD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VDD
VDD
VDD
DUTY0
DUTY1
VSS
MS
CLS
VDD
MI
PS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
X
Y
No.
-4905
-4815
-4725
-4635
-4545
-4455
-4365
-4275
-4185
-4095
-4005
-3915
-3825
-3735
-3645
-3555
-3465
-3375
-3285
-3195
-3105
-3015
-2925
-2835
-2745
-2655
-2565
-2475
-2385
-2295
-2205
-2115
-2025
-1935
-1845
-1755
-1665
-1575
-1485
-1395
-1305
-1215
-1125
-1035
-945
-855
-765
-675
-585
-495
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
VDD
VDD
VDD
VDD
VDD
VDD
VOUT
VOUT
VOUT
VOUT
C3+
C3+
C3+
C3+
C3C3C3C3C1+
C1+
C1+
C1+
C1C1C1C1C2+
C2+
C2+
C2+
C2C2C2C2VSS
VSS
VR
VR
V0
V0
V1
V1
V2
V2
V3
V3
V4
V4
VSS
VSS
X
-405
-315
-225
-135
-45
45
135
225
315
405
495
585
675
765
855
945
1035
1125
1215
1305
1395
1485
1575
1665
1755
1845
1935
2025
2115
2205
2295
2385
2475
2565
2655
2745
2835
2925
3015
3105
3195
3285
3375
3465
3555
3645
3735
3825
3915
4005
Y
No.
Name
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
BSTS
DCDC5B
VDD
HPM
INTRS
VSS
TEMPS
VDD
DUMMY
DUMMY
DUMMY
DUMMY
COMS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
X
4095
4185
4275
4365
4455
4545
4635
4725
4815
4905
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
5271
4865
4795
4725
Y
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1336
-1280
-1210
-1140
-1070
-1000
-930
-860
-790
-720
-650
-580
-510
-440
-370
-300
-230
-160
-90
-20
50
120
190
260
330
400
470
540
610
680
750
820
890
960
1030
1100
1170
1240
1301
1301
1301
5
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
No.
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
6
Name
DUMMY
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
X
4655
4585
4515
4445
4375
4305
4235
4165
4095
4025
3955
3885
3815
3745
3675
3605
3535
3465
3395
3325
3255
3185
3115
3045
2975
2905
2835
2765
2695
2625
2555
2485
2415
2345
2275
2205
2135
2065
1995
1925
1855
1785
1715
1645
1575
1505
1435
1365
1295
1225
Y
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Name
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
X
1155
1085
1015
945
875
805
735
665
595
525
455
385
315
245
175
105
35
-35
-105
-175
-245
-315
-385
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
-1435
-1505
-1575
-1645
-1715
-1785
-1855
-1925
-1995
-2065
-2135
-2205
-2275
Y
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Name
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COMS
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
X
-2345
-2415
-2485
-2555
-2625
-2695
-2765
-2835
-2905
-2975
-3045
-3115
-3185
-3255
-3325
-3395
-3465
-3535
-3605
-3675
-3745
-3815
-3885
-3955
-4025
-4095
-4165
-4235
-4305
-4375
-4445
-4515
-4585
-4655
-4725
-4795
-4865
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
Y
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1301
1240
1170
1100
1030
960
890
820
750
680
610
540
470
400
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
Name
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
DUMMY
DUMMY
X
Y
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
-5271
330
260
190
120
50
-20
-90
-160
-230
-300
-370
-440
-510
-580
-650
-720
-790
-860
-930
-1000
-1070
-1140
-1210
-1280
No.
Name
X
Y
No.
Name
X
Y
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
PIN DESCRIPTION
POWER SUPPLY
Table 3. Power Supply Pin Description
Name
I/O
Description
VDD
Supply
Power supply
VSS
Supply
Ground
LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier
for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD Bias.
V0
V1
LCD bias
V1
V2
V3
V4
V3
1/9 bias
(8/9) x V0
(7/9) x V0
(2/9) x V0
(1/9) x V0
V4
1/8 bias
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/7 bias
(6/7) x V0
(5/7) x V0
(2/7) x V0
(1/7) x V0
1/6 bias
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/5 bias
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
V2
I/O
LCD DRIVER SUPPLY
Table 4. LCD Driver Supply Pin Description
8
Name
I/O
Description
C1-
O
Capacitor 1 negative connection pin for voltage converter
C1+
O
Capacitor 1 positive connection pin for voltage converter
C2-
O
Capacitor 2 negative connection pin for voltage converter
C2+
O
Capacitor 2 positive connection pin for voltage converter
C3-
O
Capacitor 3 negative connection pin for voltage converter
C3+
O
Capacitor 3 positive connection pin for voltage converter
VOUT
I/O
Voltage converter input / output pin
DCDC5B
I
VR
I
5 times boosting circuit enable input pin
When this pin is low in 4 times boosting circuit, the 5-times boosting voltage appears at
VOUT.
V0 voltage adjustment pin
It is valid only when on-chip resistors are not used (INTRS = “L”).
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
SYSTEM CONTROL
Table 5. System Control Pin Description
Name
I/O
Description
Master / Slave operation select pin
− MS = "H": master operation
− MS = "L": slave operation
The following table depends on the MS status.
MS
I
MS
H
L
CLS
OSC
circuit
Power
supply
circuit
CL
M
FRS
DISP
H
Enabled
Enabled
Output
Output
Output
Output
L
Disabled
Enabled
Input
Output
Output
Output
-
Disabled
Disabled
Input
Input
Output
Input
Built-in oscillator circuit enable / disable select pin
− CLS = “H”: enable
− CLS = “L”: disable (external display clock input to CL pin)
CLS
I
CL
I/O
Display clock input / output pin
When the KS0713 is used in master/slave mode (multi-chip), the CL pins must be
connected each other.
M
I/O
LCD AC signal input / output pin
When the KS0713 is used in master/slave mode (multi-chip), the M pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
FRS
O
Static driver segment output pin
This pin is used together with the M pin.
I/O
LCD display blanking control input / output
When KS0713 is used in master/slave mode (multi-chip), the DISP pins must be
connected each other.
− MS = “H”: output
− MS = “L”: input
DISP
INTRS
I
HPM
I
TEMPS
I
Internal resistors select pin
This pin selects the resistors for adjusting V0 voltage level.
− INTRS = "H": use the internal resistors.
− INTRS = "L": use the external resistors.
V0 voltage is controlled with VR pin and external resistive divider.
Power control pin of the power supply circuit for LCD driver
− HPM = "H": high power mode
− HPM = "L": normal mode
This pin is valid in master operation.
Selects temperature coefficient of the reference voltage
− TEMPS = "L": -0.05%/°C
− TEMPS = "H": -0.2%/°C
9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Table 5. System Control Pin Description (Continued)
Name
I/O
Description
Selects input voltages of the built-in voltage converter
BSTS
I
BSTS
Voltage converter
input voltage
Remarks
L
4V
VDD > 4V
H
VDD
2.4V ≤ VDD ≤ 3.6V
When BSTS pin is “L”, VDD must be higher than 4V in four times boosting.
NOTE: Because the maximum voltage of VDD has been changed to 3.6V, we strongly
recommend that BSTS pin should be fixed to “H”.
The LCD driver duty ratio depends on the following table
DUTY0
DUTY1
10
I
DUTY1
DUTY0
Duty ratio
L
L
1/33
L
H
1/49
H
L/H
1/65
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Table 6. Microprocessor Interface Pin Description
Name
I/O
RESETB
I
Description
Reset input pin
When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input
PS
I
PS
Interface
mode
Chip
select
Data /
instruction
Data
Read / Write
Serial clock
H
Parallel
CS1B,
CS2
RS
DB0 to DB7
E_RD
RW_WR
-
L
Serial
CS1B,
CS2
RS
SID(DB7)
Write only
SCLK(DB6)
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to
DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.
MI
CS1B
CS2
RS
I
Microprocessor interface selects input pin
− MI = "H": 6800-series MPU interface
− MI = "L": 8080-series MPU interface
I
Chip select input pins
Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.
When chip select is non-active, DB0 to DB7 may be high impedance.
I
Register select input pin
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
RW_WR
MI
MPU type
RW_WR
H
6800-series
RW
Read / Write control input pin
− RW = “H”: read
− RW = “L”: write
L
8080-series
/WR
Write enable clock input pin
The data ON DB0 to DB7 are latched at the rising
edge of the /WR signal.
I
Description
11
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Table 6. Microprocessor Interface Pin Description (Continued)
Name
I/O
Description
Read / Write execution control pin
MI
E_RD
DB0
to
DB7
12
I
I/O
MPU type
E_RD
H
6800-series
E
L
8080-series
/RD
Description
Read / Write control input pin
− RW = “H”: When E is “H”, DB0 to DB7 are in an
output status.
− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.
Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");
− DB0 to DB5: high impedance
− DB6: serial input clock (SCLK)
− DB7: serial input data (SID)
When chip select is not active, DB0 to DB7 may be high impedance.
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUTS
Table 7. LCD Driver Outputs Pin Description
Name
I/O
Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG1
to
SEG132
O
Display data
M
H
Segment driver output voltage
Normal display
Reverse display
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
L
V3
VSS
VSS
VSS
Power save mode
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
COM1
to
COM64
O
Scan data
M
Common driver output voltage
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
Power save mode
COMS
O
VSS
Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open.
In multi-chip (master / slave) mode, all COMS pins on both master and slave units are the
same signal.
NOTE: DUMMY - These pins should be opened (floated).
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There are CS1B and CS2 pins for Chip Selection. The KS0713 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled
and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the
counter are reset.
Parallel / Serial Interface
KS0713 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial interface is determined by PS pin as shown in table 8.
Table 8. Parallel / Serial Interface Mode
PS
Type
CS1B
CS2
H
Parallel
CS1B
CS2
L
Serial
CS1B
CS2
MI
Interface mode
H
6800-series MPU mode
L
8080-series MPU mode
*×
Serial-mode
*× : Don't care
Parallel Interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in
table 9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10.
Table 9. Microprocessor Selection for Parallel Interface
MI
CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
MPU bus
H
CS1B
CS2
RS
E
RW
DB0 to DB7
6800-series
L
CS1B
CS2
RS
/RD
/WR
DB0 to DB7
8080-series
Table 10. Parallel Data Transfer
Common
14
6800-series
8080-series
RS
E_RD
(E)
RW_WR
(RW)
E_RD
(/RD)
RW_WR
(/WR)
Description
H
H
H
L
H
Display data read out
H
H
L
H
L
Display data write
L
H
H
L
H
Register status read
L
H
L
H
L
Writes to internal register (instruction)
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Serial Interface (PS = "L")
When the KS0713 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the
internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock
going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data
when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the
external noise caused by the line length, the operation check on the actual machine is recommended.
CS1B
CS2
SID
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
SCLK
RS
Figure 3. Serial Interface Timing
Busy Flag
The Busy Flag indicates whether the KS0713 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.
15
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Data Transfer
The KS0713 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure
5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.
MPU signals
RS
/WR
DB0 to DB7
N
D(N)
D(N+1)
D(N+2)
D(N+3)
N
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
/WR
BUS HOLDER
COLUMN ADDRESS
N
N+1
Figure 4. Write Timing
16
N+2
N+3
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
MPU signals
RS
/WR
/RD
DB0 to DB7
Dummy
N
D(N)
D(N+1)
Internal signals
/WR
/RD
BUS HOLDER
COLUMN ADDRESS
N
D(N)
N
N+1
D(N+1)
D(N+2)
N+2
N+3
Figure 5. Read Timing
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8
lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page
directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD
common lines as shown in Figure 6. The microprocessor can read from and write to RAM through the I/O buffer.
Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.
DB0
0
0
1
--
0
COM1
--
DB1
1
0
0
--
1
COM2
--
DB2
0
1
1
--
0
COM3
--
DB3
1
0
1
--
0
COM4
--
DB4
0
0
0
--
1
COM5
--
Display Data RAM
LCD Display
Figure 6. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0
are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it
is impossible to access to on-chip RAM.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM1) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the
initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register
are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the
MPU can not access Line Address of icons.
18
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Column Address Circuit
Column address circuit has a 8-bit preset counter that provides column address to the Display Data RAM as
shown in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since
this address is increased by 1 each a Read or Write Data instruction, microprocessor can access the display data
continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is
unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the Column
Address counter is independent of page address register.
ADC select instruction makes it possible to invert the relationship between the Column Address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to
the following figure 7.
SEG output
SEG
1
SEG
2
SEG
3
SEG
4
... ...
SEG
129
SEG
130
SEG
131
SEG
132
Column address [Y7:Y0]
00H
01H
02H
03H
... ...
80H
81H
82H
83H
Display data
1
0
1
0
1
1
0
0
LCD panel display
( ADC = 0 )
LCD panel display
( ADC = 1 )
... ...
... ...
Figure 7. The Relationship between the Column Address and the Segment Outputs
Segment Control Circuit
This circuit controls the display data by the Display ON / OFF, Reverse display ON / OFF and entire display ON /
OFF instructions without changing the data in the display data RAM.
19
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
DB1
DB0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
ADC=0
ADC=1
Page0
Page1
Page2
Page3
Page4
Page5
Page6
Page7
Page8
7E 7F 80 81 82 83
05 04 03 02 01 00
SEG132
SEG131
SEG130
SEG129
SEG128
SEG127
SEG6
SEG5
-----
SEG4
---------
SEG3
00 01 02 03 04 05
83 82 81 80 7F 7E
SEG2
LCD Output
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
SEG1
Column
Address
Data
Figure 8. Display Data RAM Map
20
Line
Address
COM
Output
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COMS
Start
1/33
Duty
DB2
1/49
Duty
Page Address
DB3
KS0713
When the initial display
line address
is 1C[HEX]
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used
in the voltage converter and display timing generation circuit.
* Test condition: Temperature: 25°C & 85°C, TEMPS=”L”, No load
VDD vs. fosc
7.00
6.00
1/33 Duty (25°C)
1/49 Duty (25°C)
1/65 Duty (25°C)
1/33 Duty (85°C)
1/49 Duty (85°C)
1/65 Duty (85°C)
5.00
fosc 4.00
[kHz] 3.00
2.00
1.00
0.00
2.4
2.7
3.0
3.3
3.6
4.0
4.5
5.0
5.5
VDD [V]
Figure 9. VDD vs. fOSC
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD
driver, is completely independent of the access to the display data RAM from the microprocessor. The display
clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also
generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver
waveform and internal timing signal are shown in figure 9.
In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11
shows the M, CL, and DISP status.
Table 11. Master and Slave Timing Signal Status
Operation mode
Master
Slave
Oscillator
M
CL
DISP
ON (internal clock used)
Output
Output
Output
OFF (external clock used)
Output
Input
Output
-
Input
Input
Input
21
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
64
65
1
2
3
4
5
6
7
8
9
10
11
12
KS0713
58
59
60
61
62
63
64
65
1
2
3
4
5
6
CL
M
COM1
V0
V1
V2
V3
V4
VSS
COM2
V0
V1
V2
V3
V4
VSS
SEGn
V0
V1
V2
V3
V4
VSS
Figure 10. 2-frame AC Driving Waveform (Duty ratio = 1/65)
Common Output Control Circuit
This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select
Instruction specifies the scanning direction of the common output pins.
Table 12. The Relationship between Duty Ratio and Common Output
Duty
1/33
1/49
1/65
SHL
0
1
0
1
0
1
Common output pins
COM[1:16]
COM[17:24]
COM[1:16]
COM[32:17]
COM[1:24]
COM[48:25]
COM[25:40]
*NC
*NC
*NC
*NC
COM[1:64]
COM[64:1]
COM[41:48]
COM[49:64]
COM[17:32]
COM[16:1]
COM[25:48]
COM[24:1]
COMS
COMS
COMS
COMS
*NC: No Connection
22
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER CIRCUIT
This driver circuit is configured by 66-channel common drivers (including 2 COMS channels) and 132-channel
segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
VDD
COM1
M
COM2
VSS
COM3
V0
V1
V2
COM1
COM4
COM5
V3
V4
VSS
V0
V1
V2
COM6
COM2
COM7
COM8
V3
V4
VSS
V0
V1
V2
COM9
COM3
COM10
V3
V4
VSS
V0
V1
V2
COM11
SEG1
COM12
COM13
V3
V4
VSS
V0
V1
V2
COM14
SEG2
COM15
COM16
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
V3
V4
VSS
V0
V1
V2
SEG3
V3
V4
VSS
Figure 11. Segment and Common Timing
23
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low
power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits,
and voltage follower circuits. They are valid only in master operation and controlled by power control instruction.
For details, refers to "Instruction Description". Table 13 shows the referenced combinations in using power supply
circuits.
Table 13. Recommended Power Supply Combinations
User setup
Power
control
(VC VR VF)
V/C
circuits
V/R
circuits
V/F
circuits
VOUT
V0
V1 to V4
Only the internal power
supply circuits are used
111
ON
ON
ON
Open
Open
Open
Only the voltage
regulator circuits and
voltage follower circuits
are used
011
OFF
ON
ON
External
input
Open
Open
Only the voltage follower
circuits are used
001
OFF
OFF
ON
Open
External
input
Open
Only the external power
supply circuits are used
000
OFF
OFF
OFF
Open
External
input
External
input
24
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Voltage Converter Circuits
These circuits boost up the electric potential between VDD and VSS to 2, 3, 4 or 5 times toward positive side and
boosted voltage is outputted from VOUT pin.
[C1 = 1.0 to 4.7 µF]
VDD
VDD
-
VDD
VOUT
C3+
C3 C2+
C2 C1+
C1 -
+
+
-
VOUT = 2 × VDD
VDD
DCDC5B
VSS
VSS
GND
+
VOUT
C3+
C3 C2+
C2 C1+
C1 -
C1
VDD
-
VDD
C1
C1
+
C1
+
C1
VDD
DCDC5B
VSS
VOUT = 3 × VDD
VDD
VSS
GND
Figure 12. Two Times Boosting Circuit
VDD
VDD
VOUT
C3+
C3 C2+
C2 C1+
C1 -
VDD
+
+
VDD
C1
C1
+
C1
+
C1
VDD
VOUT = 4 × VDD
VDD
DCDC5B
VSS
Figure 13. Three Times Boosting Circuit
VSS
VOUT
C3+
C3 C2+
C2 C1+
C1 -
-
C1
+
+
C1
+
C1
+
C1
-
DCDC5B
VSS
VOUT = 5 × VDD
VDD
VSS
GND
GND
Figure 14. Four Times Boosting Circuit
GND
Figure 15. Five Times Boosting Circuit
25
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Voltage Regulator Circuits
The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by
adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits shown in figure 16, it is necessary to be applied internally or externally.
For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by
INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the
value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta =
25°C is shown in table 14-1.
Rb
V0 = ( 1 +  ) x VEV [V] ------ (Eq. 1)
Ra
(63 - α)
VEV = ( 1 -  ) x VREF [V] ------ (Eq. 2)
300
Table 14-1. VREF Voltage at Ta = 25 °C
TEMPS
Temp. coefficient
VREF [V]
L
-0.05% / °C
2.0
H
-0.2% / °C
2.0
Table 14-2. Reference Voltage Parameters (α
α)
26
SV5
SV4
SV3
SV2
SV1
SV0
Reference voltage parameter (α
α)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
VOUT
+
V0
VEV
Rb
VR
Ra
VSS
GND
Figure 16. Internal Voltage Regulator Circuit
27
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
In Case of Using Internal Resistors, Ra and Rb (INTRS = "H")
When INTRS pin is “H”, resistor Ra is connected internally between VR pin and VSS, and Rb is connected
between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference
Voltage".
Table 15. Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0)
3-bit data settings (R2 R1 R0)
1+(Rb / Ra)
000
001
010
011
100
101
110
111
1.90
2.19
2.55
3.02
3.61
4.35
5.29
6.48
The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit
electronic volume registers for each temperature coefficient at Ta = 25 °C.
14.00
(1 1 1)
(1 1 0)
(1 0 1)
(1 0 0)
(0 1 1)
(0 1 0)
(0 0 1)
(0 0 0)
12.00
10.00
V0 8.00
[V] 6.00
4.00
2.00
0.00
0
8
16
24
32
40
Electronic volume level
Figure 17. Electronic Volume Level
28
48
56
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
In Case of Using External Resistors, Ra and Rb. (INTRS = "L")
When INTRS pin is “L”, it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb
between V0 and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 10V
2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
3. Maximum current flowing Ra, Rb = 1 uA
From Eq. 1
Rb
10 = ( 1 +  ) x VEV [V] ------ (Eq. 3)
Ra
From Eq. 2
(63 - 32)
VEV = ( 1 -  ) x 2.0 = 1.79 [V] ------ (Eq. 4)
300
From requirement 3.
10
 = 1 [uA] ------ (Eq. 5)
Ra + Rb
From equations Eq. 3, 4 and 5
Ra = 1.79 [MΩ]
Rb = 8.21 [MΩ]
The following table shows the range of V0 depending on the above requirements.
Table 16. V0 Depending on Electronic Volume Level
Electronic volume level
V0
0
.......
32
.......
63
8.83
.......
10.00
.......
11.17
29
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Voltage Follower Circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance
are converted by the Voltage Follower for increasing drive capability. The following table shows the relationship
between V1 to V4 level and each duty ratio.
Table 17. The Relationship between V1 to V4 level and Duty Ratio
Duty Ratio
DUTY1
DUTY0
1/33
L
L
1/49
L
H
1/65
H
L/H
30
LCD Bias
V1
V2
V3
V4
1/5
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
1/6
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/6
(5/6) x V0
(4/6) x V0
(2/6) x V0
(1/6) x V0
1/8
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/7
(6/7) x V0
(5/7) x V0
(2/7) x V0
(1/7) x V0
1/9
(8/9) x V0
(7/9) x V0
(2/9) x V0
(1/9) x V0
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
REFERECE CIRCUIT EXAMPLES
When using internal regulator resistors
VDD
When not using internal regulator resistors
VDD
MS
C1
INTRS
VOUT
C3+
C3C2+
C2C1+
C1-
C1
C1
C1
MS
C1
VOUT
C3+
C3C2+
C2C1+
C1-
C1
C1
C1
Ra
VR
VR
C2
C2
C2
C2
C2
-
+
+
+
+
+
C2
C2
C2
C2
C2
V0
V1
V2
V3
V4
V SS
-
V SS
INTRS
+
+
+
+
+
Rb
V0
V1
V2
V3
V4
V SS
Figure 18. When Using all LCD Power Circuits (4-Time V/C: ON, V/R: ON, V/F: ON)
When using internal regulator resistors
V DD
When not using internal regulator resistors
V DD
External
Power
Supply
MS
INTRS
VOUT
C3+
C3C2+
C2C1+
C1-
V SS
-
+
+
+
+
+
V0
V1
V2
V3
V4
INTRS
V SS
VOUT
C3+
C3C2+
C2C1+
C1-
Ra
VR
C2
C2
C2
C2
C2
MS
External
Power
Supply
VR
C2
C2
C2
C2
C2
-
+
+
+
+
+
Rb
V0
V1
V2
V3
V4
V SS
Figure 19. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON)
31
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
VDD
MS
INTRS
VOUT
C3+
C3C2+
C2C1+
C1-
External
Power
Supply
VR
C2
C2
C2
C2
C2
-
+
+
+
+
+
V0
V1
V2
V3
V4
V SS
Figure 20. When Using some LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: ON)
V DD
MS
INTRS
VOUT
C3+
C3C2+
C2C1+
C1VR
External
Power
Supply
Value of external Capacitance
Item
Value
C1
1.0 to 4.7
C2
0.47 to 1.0
Unit
µF
V0
V1
V2
V3
V4
VSS
Figure 21. When Not Using any Internal LCD Power Supply Circuits (V/C: OFF, V/R: OFF, V/F: OFF)
32
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
RESET CIRCUIT
Setting RESETB to “L” or Reset instruction can initialize internal function.
When RESETB becomes “L”, following procedure is occurred.
Display ON / OFF: OFF
Entire display ON / OFF: OFF (normal)
ADC select: OFF (normal)
Reverse display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
LCD bias ratio: 1/7 (1/65 duty), 1/6 (1/49 duty), 1/5 (1/33 duty)
Read-modify-write: OFF
SHL select: OFF (normal)
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (0, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)
When RESET instruction is issued, following procedure is occurred.
Read-modify-write: OFF
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
SHL select: 0
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (0, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)
While RESETB is “L” or Reset instruction is executed, no instruction except read status can be accepted. Reset
status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to
the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is
essential before used.
33
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
INSTRUCTION DESCRIPTION
Table 18. Instruction Table
× : Don’t care
Description
Instruction
RS
RW
Read display data
1
1
Read data
Read data from DDRAM
Write display data
1
0
Write data
Write data into DDRAM
Read status
0
1
BUSY
ADC
ON/OFF
RESETB
0
0
0
0
Display ON / OFF
0
0
1
0
1
0
1
1
1
DON
Turn on/off LCD panel
When DON = 0: display OFF
When DON = 1: display ON
Initial display line
0
0
0
1
ST5
ST4
ST3
ST2
ST1
ST0
Specify DDRAM line for COM1
0
0
1
0
0
0
0
0
0
1
0
0
×
×
SV5
SV4
SV3
SV2
SV1
SV0
Set reference voltage
mode
Set reference voltage
register
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read the internal status
Set reference voltage Mode
Set reference voltage register
Set page address
0
0
1
0
1
1
P3
P2
P1
P0
Set page address
Set column address MSB
0
0
0
0
0
1
Y7
Y6
Y5
Y4
Set column address MSB
Set column address LSB
0
0
0
0
0
0
Y3
Y2
Y1
Y0
Set column address LSB
ADC select
0
0
1
0
1
0
0
0
0
ADC
Reverse display ON / OFF
0
0
1
0
1
0
0
1
1
REV
Entire display ON / OFF
0
0
1
0
1
0
0
1
0
EON
Select SEG output direction
When ADC = 0: normal direction
(SEG1→SEG132)
When ADC = 1: reverse direction
(SEG132→SEG1)
Select normal / reverse display
When REV = 0: normal display
When REV = 1: reverse display
Select normal / entire display ON
When EON = 0: normal display.
When EON = 1: entire display
ON
LCD bias select
0
0
1
0
1
0
0
0
1
BIAS
Set modify-read
0
0
1
1
1
0
0
0
0
0
Select LCD bias
Set modify-read mode
Reset modify-read
0
0
1
1
1
0
1
1
1
0
Release modify-read mode
Reset
0
0
1
1
1
0
0
0
1
0
Initialize the internal functions
Select COM output direction
When SHL = 0: normal direction
(COM1→COM64)
When SHL = 1: reverse direction
(COM64→COM1)
SHL select
0
0
1
1
0
0
SHL
×
×
×
Power control
0
0
0
0
1
0
1
VC
VR
VF
Control power circuit operation
Regulator resistor select
0
0
0
0
1
0
0
R2
R1
R0
Select internal resistance ratio of
the regulator resistor
Set static indicator mode
0
0
1
0
1
0
1
1
0
SM
Set static indicator mode
Set static indicator register
0
0
×
×
×
×
×
×
S1
S0
Set static indicator register
Power save
-
-
-
-
-
-
-
-
-
-
Compound instruction of display
OFF and entire display ON
Test instruction
0
0
1
1
1
1
×
×
×
×
Don't use this instruction.
34
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Read Display Data
8-bit data from Display Data RAM specified by the column address and page address can be read by this
instruction. As the column address is increased by 1 automatically after each this instruction, the
microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display Data cannot be read through the serial interface.
RS
RW
1
1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Read data
Write Display Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the
column address and page address. The column address is increased by 1 automatically so that the
microprocessor can continuously write data to the addressed page.
RS
RW
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB0
Write data
Set Page Address
Set Page Address
Set Column Address
Set Column Address
Data Write
Dummy Data Read
Column = Column + 1
Column = Column + 1
Data Write Continue ?
DB1
YES
NO
Optional Status
Data Read
Column = Column + 1
Data Read Continue ?
YES
NO
Optional Status
Figure 22. Sequence for Writing Display Data
Figure 23. Sequence for Reading Display Data
35
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Read Status
Indicates the internal status of the KS0713.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
BUSY
ADC
ON / OFF
RESETB
0
0
0
0
Flag
Description
The device is busy when internal operation or reset. Any instruction is rejected until
BUSY goes Low.
0: chip is active, 1: chip is being busy.
BUSY
Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG132 → SEG1), 1: normal direction (SEG1 → SEG132)
ADC
ON / OFF
Indicates display ON / OFF status
0: display ON, 1: display OFF
RESETB
Indicates the initialization is in progress by RESETB signal.
0: chip is active, 1: chip is being reset.
Display ON / OFF
Turns the display ON or OFF
RS
RW
0
0
DON = 1: display ON
DON = 0: display OFF
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
0
1
1
1
DON
Initial Display Line
Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed
at the top row (COM1 when SHL = L, COM64 when SHL = H) of LCD panel.
36
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
ST5
ST4
ST3
ST2
ST1
ST0
ST5
ST4
ST3
ST2
ST1
ST0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reference Voltage Select
Consists of 2-byte instruction
The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage
register. After second instruction, reference voltage mode is released.
The 1st Instruction: Set Reference Voltage Select Mode
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
The 2nd Instruction: Set Reference Voltage Register
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SV3
SV2
SV1
SV0
0
0
1
0
0
0
0
×
×
SV5
SV4
SV5
SV4
SV3
SV2
SV1
SV0
Reference voltage parameter (α
α)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Setting Reference Voltage Start
1st Instruction for Mode Setting
2nd Instruction for Register Setting
Setting Reference Voltage End
Figure 24. Sequence for Setting the Reference Voltage
37
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any
RAM data bit can be accessed when its Page Address and column address are specified. Along with the
column address, the Page Address defines the address of the display RAM to write or read display data.
Changing the Page Address doesn't effect to the display status.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
P3
P2
P1
P0
P3
P2
P1
P0
Page
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
0
1
1
1
7
1
0
0
0
8
Set Column Address
Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along
with the Column Address, the Column Address defines the address of the display RAM to write or read
display data. When the microprocessor reads or writes display data to or from display RAM, column
addresses are automatically increased.
Set Column Address MSB
RS
RW
DB7
0
0
0
Set Column Address LSB
RS
RW
DB7
38
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
Y7
Y6
Y5
Y4
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Y1
Y0
0
0
0
0
0
0
Y3
Y2
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
1
0
130
1
0
0
0
0
0
1
1
131
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
ADC Select
Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins can be reversed by software. This makes IC layout flexible in LCD module assembly.
RS
RW
DB7
DB6
DB5
0
0
1
0
1
ADC = 0: normal direction (SEG1 → SEG132)
ADC = 1: reverse direction (SEG132 → SEG1)
DB4
DB3
DB2
DB1
DB0
0
0
0
0
ADC
Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
1
1
REV
REV
RAM bit data = “1”
RAM bit data = “0”
0 (normal)
LCD pixel is illuminated
LCD pixel is not illuminated
1 (reverse)
LCD pixel is not illuminated
LCD pixel is illuminated
Entire Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF
instruction.
RS
RW
DB7
0
0
1
EON = 0: normal display
EON = 1: entire display ON
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
0
1
0
EON
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
0
0
0
1
Bias
Duty
ratio
DUTY1
DUTY0
1/33
0
1/49
1/65
LCD bias
Bias = 0
Bias = 1
0
1/5
1/6
0
1
1/6
1/8
1
0/1
1/7
1/9
39
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Set Modify-Read
This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
0
0
Reset Modify-Read
This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
1
1
1
0
Set Page Address
Set Column Address (N)
Set Modify-Read
Dummy Read
Data Read
Data Process
Data Write
NO
Change Complete ?
YES
Reset Modify-Read
Return Column Address (N)
Figure 25. Sequence for Cursor Display
40
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reset
This instruction resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the
LCD power supply which is initialized by the RESETB pin.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
0
0
0
1
0
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD driver output status.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
0
1
1
0
0
SHL
×
×
SHL = 0: normal direction (COM1 → COM64)
SHL = 1: reverse direction (COM64 → COM1)
DB0
×
× : Don’t care
Power control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of
internal power supply functions can be used simultaneously.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
1
VC
VR
VF
VC
VR
VF
0
1
Status of internal power supply circuits
Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
Internal voltage regulator circuit is OFF
Internal voltage regulator circuit is ON
0
1
0
1
Internal voltage follower circuit is OFF
Internal voltage follower circuit is ON
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Regulator Resistor Select
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator
section in power supply circuit. Refer to the table 15.
RS
RW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
0
R2
R1
R0
R2
R1
R0
1 + (Rb / Ra)
0
0
0
1.90
0
0
1
2.19
0
1
0
2.55
0
1
1
3.02
1
0
0
3.61
1
0
1
4.35
1
1
0
5.29
1
1
1
6.48
Set Static Indicator State
Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second
byte instruction (set Static Indicator register) to be valid. The first byte sets the static indicator ON / OFF.
When it is on, the second byte updates the contents of static indicator register without issuing any other
instruction and this static indicator state is released after setting the data of indicator register.
The 1st Instruction: Set Static Indicator Mode (ON / OFF)
RS
RW
DB7
DB6
DB5
DB4
0
0
1
SM = 0: static indicator OFF
SM = 1: static indicator ON
0
1
The 2nd Instruction: Set Static Indicator Register
RS
RW
DB7
DB6
DB5
0
42
0
×
×
×
DB3
DB2
DB1
DB0
0
1
1
0
SM
DB4
DB3
DB2
DB1
DB0
×
×
×
S1
S0
S1
S0
Status of static indicator output
0
0
OFF
0
1
ON (about 1 second blinking)
1
0
ON (about 0.5 second blinking )
1
1
ON (always ON)
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Power Save (Compound Instruction)
If the entire display ON / OFF instruction is issued during the display OFF state, KS0713 enters the Power
Save status to reduce the power consumption to the static power consumption value. According to the status
of static indicator mode, power save is entered to one of two modes (sleep and standby mode). When static
indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is
released by the display ON and entire display OFF instruction.
Static Indicator OFF
Static Indicator ON
Power Save (Compound Instruction)
[Display OFF]
[Entire Display ON]
Sleep Mode
[Oscillator Circuit: OFF]
[LCD Power Supply Circuit: OFF]
[All COM / SEG Outputs: VSS]
[Consumption Current: < 2µA]
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Static Indicator ON]
[Display ON]
Release Sleep Mode
Standby Mode
[Oscillator Circuit: ON]
[LCD Power Supply Circuit: OFF]
[All COM/SEG Outputs: VSS]
[Consumption Current: < 10µA]
Power Save OFF (Compound Instruction)
[Entire Display OFF]
[Display ON]
Release Standby Mode
Figure 26. Power Save Routine
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Referential Instruction Setup Flow (1)
User System Setup by External Pins
Start of Initialization
Power ON (VDD - VSS) Keeping the RESETB Pin = “L”
Waiting for Stabilizing the Power
RESETB Pin = “H”
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
User LCD Power Setup by Internal Instructions
[Voltage Converter ON]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Regulator ON]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Follower ON]
User LCD Power Setup by Internal Instructions
[Regulator Resistor Select]
[Reference Voltage Register Set]
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 27. Initializing with the Built-in Power Supply Circuits
44
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (2)
User System Setup by External pins
Start of initialization
Power On ( VDD - VSS ) keeping the RESETB pin = “L”
Waiting for stabilizing the power
RESETB pin = “H”
Set Power Save
User Application Setup by Internal Instructions
[ADC Select]
[SHL Select]
[LCD Bias Select]
User LCD Power Setup by Internal Instructions
[Regulator Resistor Select]
[Reference Voltage Register Set]
Release Power Save
Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 28. Initializing without the Built-in Power Supply Circuits
45
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (3)
End of Initialization
Display Data RAM Addressing by Instruction
[Initial Display Line]
[Set Page Address]
[Set Column Address]
Write Display ON / OFF by Instruction
[Display ON / OFF]
Turn Display ON / OFF by Instruction
[Display ON / OFF]
End of Data Display
Figure 29. Data Displaying
46
KS0713
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Referential Instruction Setup Flow (4)
Optional Status
Turn Display ON / OFF by Instruction
[Display OFF]
User LCD Power Setup by Internal Instructions
[Voltage Regulator OFF]
Waiting for ≥ 50ms
User LCD Power Setup by Internal Instructions
[Voltage Follower OFF]
Waiting for ≥ 1ms
User LCD Power Setup by Internal Instructions
[Voltage Converter OFF]
Waiting for ≥ 1ms
Power OFF (VDD - VSS)
Figure 30. Power OFF
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 19. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VDD
-0.3 to +7.0
V
VLCD
-0.3 to +17.0
V
Input voltage range
VIN
-0.3 to VDD +0.3
V
Operating temperature range
TOPR
-40 to +85
°C
Storage temperature range
TSTR
-55 to +125
°C
Supply voltage range
NOTES:
1. VDD and VLCD are based on VSS = 0V.
2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.
48
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
DC CHARACTERISTICS
Table 20. DC Characteristics
(VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C)
Item
Symbol
Operating voltage (1)
Condition
Min.
Typ.
Max
Unit
Pin used
VDD
2.4
-
3.6
V
VDD *1
Operating voltage (2)
V0
4.0
-
15.0
V
V0 *2
High
VIH
0.8VDD
-
VDD
V
*3
Low
VIL
VSS
-
0.2VDD
High
VOH
IOH = -0.5mA
0.8VDD
-
VDD
V
*4
Low
VOL
IOL = 0.5mA
VSS
-
0.2VDD
Input voltage
Output
voltage
Input leakage current
IIL
VIN = VDD or VSS
- 1.0
-
+ 1.0
µA
*5
Output leakage current
IOZ
VIN = VDD or VSS
- 3.0
-
+ 3.0
µA
*6
LCD driver ON
resistance
RON
Ta = 25°C, V0 = 8V
-
2.0
3.0
kΩ
SEGn
COMn *7
Internal
fOSC
17
22
27
External
f CL
Ta = 25°C
Duty ratio = 1/65
4.25
5.50
6.75
kHz
CL *8
Internal
fOSC
20
25
30
External
f CL
3.33
4.17
5.00
kHz
CL *8
×2
2.4
-
3.6
×3
2.4
-
3.6
×4
V
VDD
2.4
-
3.6
×5
2.4
-
3.0
×2 / ×3 / ×4 / ×5
voltage conversion
(no-load )
95
99
-
%
VOUT
Oscillator
frequency (1)
Oscillator
frequency (2)
Voltage converter
input voltage
VDD
Ta = 25°C
Duty ratio = 1/49
Voltage converter
output voltage
VOUT
Voltage regulator
operating voltage
VOUT
4.0
-
15.0
V
VOUT
Voltage follower
operating voltage
V0
4.0
-
15.0
V
V0 *9
-0.05%/°C
1.94
2.00
2.06
V
*10
-0.2%/°C
1.94
2.00
2.06
V
*10
Reference voltage
VREF0
VREF1
Ta = 25°C
49
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Dynamic Current Consumption (1) when the Built-in Power Circuit is OFF (At Operate Mode)
(Ta = 25 °C)
Item
Symbol
Dynamic current
consumption (1)
IDD1
Condition
Min.
Typ.
Max.
Unit
Pin used
VDD = 3.0V
V0 – VSS = 11.0V
1/65 duty ratio
Display pattern OFF
-
-
20
µΑ
*11
Dynamic Current Consumption (2) when the built-in power circuit is ON (At operate mode)
Item
Dynamic current
consumption (2)
Symbol
(Ta = 25 °C)
Unit Pin used
Condition
Min.
Typ.
Max.
VDD = 3.0V,
quad boosting,
V0 – VSS = 11.0V,
1/65 duty ratio,
Display pattern OFF,
Normal power mode
-
70
100
µΑ
*12
VDD = 3.0V,
quad boosting,
V0 – VSS = 11.0V,
1/65 duty ratio,
Display pattern checker,
Normal power mode
-
95
160
µΑ
*12
IDD2
Current Consumption During Power Save Mode
(Ta = 25 °C)
Item
Sleep mode
current
Standby mode
current
50
Symbol
Condition
Min.
Typ.
Max.
Unit
IDDS1
During sleep
-
-
2.0
µA
IDDS2
During standby
-
-
10.0
µA
Pin used
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 21. The Relationship between Oscillation Frequency and Frame Frequency
Duty Ratio
Item
fCL
fM
fOSC
fOSC
On-chip oscillator circuit is used


4
8 × 65
On-chip oscillator circuit is not used
External input (f CL)

fOSC
fOSC
On-chip oscillator circuit is used


1/65
fOSC
1/49
2 × 65
6
12 × 49
External input (f CL)

fOSC
fOSC
fOSC
On-chip oscillator circuit is not used
On-chip oscillator circuit is used
1/33

2 × 49

8
16 × 33
External input (f CL)

fOSC
On-chip oscillator circuit is not used
2 × 33
(f OSC: oscillation frequency, f CL: display clock frequency, f M: LCD AC signal frequency)
[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, INTRS, HPM, TEMPS, BSTS,
DCDC5B, CLS, CL, M, DISP pins.
*4. DB0 to DB7, M, FRS, DISP, CL pins.
*5. CS1B, CS2, RS, DB [7:0], E_RD, RW_WR, RESETB, MS, MI, PS, INTRS, HPM, TEMPS, BSTS, DCDC5B,
CLS, CL, M, DISP pins.
*6. Applies when the DB [7:0], M, DISP, and CL pins are in high impedance.
*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON= ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.)
*8. See table 21 for the relationship between oscillation frequency and frame frequency.
*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc.
51
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
REFERENCE DATA
IDD1 vs. VDD
* Test Condition: Temperature: 25°C & 85°C, V0 = 11V (External), TEMPS = 'L', 1/65 duty, Normal Power Mode
VDD vs. IDD1(Pattern Off)
10.00
8.00
IDD1 6.00
[uA] 4.00
11.0V, 1/65 Duty (25°C)
11.0V, 1/65 Duty (85°C)
2.00
0.00
2.4
2.7
3.0
3.3
3.6
4.0
4.5
5.0
VDD [V]
Figure 31. Display Pattern is OFF
52
5.5
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
IDD2 vs. VDD
* Test Condition: Temperature: 25°C & 85°C, 1/65 duty, Quad Boosting, RR = 6, EV = 32
VDD vs. IDD2 (Pattern Off)
80.00
70.00
60.00
50.00
IDD2
40.00
[uA]
30.00
1/65 Duty (25°C)
1/65 Duty (85°C)
20.00
10.00
0.00
2.4
2.7
3.0
3.3
3.6
4.0
4.5
5.0
VDD [V]
Figure 32. Display Pattern is OFF
VDD vs. IDD2 (Checker Pattern)
180.00
160.00
140.00
120.00
1/65 Duty (25°C)
IDD2 100.00
[uA] 80.00
1/65 Duty (85°C)
60.00
40.00
20.00
0.00
2.4
2.7
3.0
3.3
3.6
4.0
4.5
5.0
VDD [V]
Figure 33. Display Pattern is Checker
53
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
AC CHARACTERISTICS
Read / Write Characteristics (8080-series MPU)
RS
tAS80
tAH80
CS1B
(CS2=1)
tCY80
tPW80(R),
RD, WR
0.9V DD
tPW80(W)
0.1VDD
tDS80
tDH80
DB0 to DB7
(Write)
tACC80
tOD80
DB0 to DB7
(Read)
Figure 34. Read / Write Characteristics (8080-series MPU)
Item
Address setup time
Address hold time
System cycle time
Pulse width (WR)
Pulse width (RD)
Data setup time
Data hold time
Read access time
Output disable time
54
Signal
RS
RS
RW_WR
E_RD
DB7
to
DB0
Symbol
tAS80
tAH80
tCY80
tPW80 (W)
tPW80 (R)
tDS80
tDH80
tACC80
tOD80
Min.
13
17
400
55
125
35
13
10
Typ.
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Max.
Unit
Remark
-
-
ns
-
-
ns
ns
ns
-
-
ns
-
125
90
ns
CL = 100 pF
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Read / Write Characteristics (6800-series Microprocessor)
RS
tAS68
tAH68
CS1B
(CS2=1)
tCY68
tPW68(R), tPW68(W)
E
0.1VDD
0.9VDD
tDS68
tDH68
DB0 to DB7
(Write)
tACC68
tOD68
DB0 to DB7
(Read)
Figure 35. Read/Write Characteristics (6800-series Microprocessor)
Item
Address setup time
Address hold time
Signal
System cycle time
RS
Data setup time
Data hold time
Access time
Output disable time
Enable pulse
Read
width
write
RS
DB7
to
DB0
E_RD
Symbol
TAS68
TAH68
Min.
13
17
TCY68
400
TDS68
TDH68
TACC68
TOD68
TPW68 (R)
TPW68 (W)
35
13
10
125
55
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Max.
Unit
Remark
-
-
ns
-
-
ns
-
-
ns
-
125
90
ns
-
-
-
CL = 100 pF
55
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Serial Interface Characteristics
Figure 36. Serial Interface Characteristics
Item
56
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Max.
Unit
Remark
Signal
Symbol
Min.
Typ.
Serial clock cycle
SCLK high pulse width
SCLK low pulse width
DB6
(SCLK)
tCYS
tWHS
tWLS
450
180
135
-
-
ns
Address setup time
Address hold time
RS
tASS
tAHS
90
360
-
-
ns
Data setup time
Data hold time
DB7
(SID)
tDSS
tDHS
90
90
-
-
ns
CS1B setup time
CS1B hold time
CS1B
tCSS
tCHS
55
180
-
-
ns
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Reset Input Timing
Figure 37. Reset Input Timing
Item
Signal
Symbol
Min.
Reset low pulse width
RESETB
tRW
900
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Remark
Max.
Unit
-
-
ns
Display Control Output Timing
Figure 38. Display Control Output Timing
Item
Signal
Symbol
Min.
M delay time
M
tDM
-
(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)
Typ.
Remark
Max.
Unit
13
70
ns
57
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
In Case of Interfacing with 6800-series (PS = “H”, MI = “H”)
Figure 39. Interfacing with 6800-series (PS = “H”, MI = “H”)
In Case of Interfacing with 8080-series (PS = “H”, MI = “L”)
Figure 40. Interfacing with 8080-series (PS = “H”, MI = “L”)
In Case of Serial Interface (PS = “L”, MI = “H/L”)
Figure 41. Serial Interface (PS = “L”, MI = “H/L”)
58
KS0713
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
CONNECTIONS BETWEEN KS0713 AND LCD PANEL
Single Chip Configuration (1/65 Duty Configurations)
Figure 42. SHL = 0, ADC = 0
Figure 44. SHL = 1, ADC = 0
Figure 43. SHL = 0, ADC = 1
Figure 45. SHL = 1, ADC = 1
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0713
Single Chip Configuration (1/49 Duty Configurations)
60
Figure 46. SHL = 0, ADC = 0
Figure 47. SHL = 0, ADC = 1
Figure 48. SHL = 1, ADC = 0
Figure 49. SHL = 1, ADC = 1
KS0713
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Single Chip Configuration (1/33 Duty Configurations)
Figure 50. SHL = 0, ADC = 0
Figure 52. SHL = 1, ADC = 0
Figure 51. SHL = 0, ADC = 1
Figure 53. SHL = 1, ADC = 1
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Multiple Chip Configuration
-
65COM (64COM + 1COMS) × 264SEG (132SEG × 2)
Figure 54. SHL = 0, ADC = 0
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
Figure 55. SHL = 1, ADC = 1
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
62
KS0713
KS0713
-
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
130COM (128COM + 2COMS) × 132SEG
Figure 56. 130COM (128COM + 2COMS) × 132SEG
♦ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
♦ Common / Segment output direction select
- Master chip: SHL = 1, ADC = 1
- Slave chip: SHL = 0, ADC = 0
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
TCP PIN LAYOUT (SAMPLE)
Figure 57. TCP Pin Layout
64
KS0713