PC133/PC100 Unbuffered DIMM M374S6453CTS M374S6453CTS SDRAM DIMM 64Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung M374S6453CTS is a 64M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung M374S6453CTS consists of eighteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M374S6453CTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Performance range Part No. M374S6453CTS-L7C/C7C M374S6453CTS-L7A/C7A M347S6453CTS-L1H/C1H M347S6453CTS-L1L/C1L • • • • • Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,375mil), double sided component PIN CONFIGURATIONS (Front side/back side) Pin Front Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Front Pin Front Pin 29 DQM1 57 58 CS0 30 59 31 DU 60 32 VSS 61 33 A0 62 34 A2 63 35 A4 64 36 A6 65 37 A8 38 A10/AP 66 67 39 BA1 68 40 VDD 69 41 VDD 42 CLK0 70 71 43 VSS 72 44 DU 73 45 CS2 46 DQM2 74 47 DQM3 75 76 48 DU 77 49 VDD 78 50 NC 79 51 NC 80 52 CB2 81 53 CB3 82 54 VSS 55 DQ16 83 56 DQ17 84 DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC *WP **SDA **SCL VDD 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Max Freq. (Speed) 133MHz@CL=2 133MHz@CL=3 100MHz@ CL=2 100MHz@ CL=3 PIN NAMES Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC **SA0 **SA1 **SA2 VDD Pin Name Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CB0 ~ 7 Check bit (Data-in/data-out) CLK0 ~ CLK3 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS3 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground *VREF Power supply for reference SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM *WP Write protection DU Don′t use NC No connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS FUNCTIONAL BLOCK DIAGRAM CS1 CS0 DQM0 • DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 • • CS U0 DQM4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U9 • DQM5 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS3 CS2 DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS U1 CS U2 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 • DQM CS U3 CS U4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U10 DQM6 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM7 • CS DQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U12 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U5 CS U14 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U6 CS U15 • DQM U11 DQM CS • DQM CS • • • • DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U7 U16 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U8 CS CS U17 CS U13 Serial PD SCL WP A0 47KΩ A1 SDA A2 SA0 SA1 SA2 A0 ~ An, BA0 & 1 SDRAM U0 ~ U17 RAS SDRAM U0 ~ U17 CAS SDRAM U0 ~ U17 VDD 10KΩ SDRAM U0 ~ U17 CKE1 WE CKE0 • SDRAM U9 ~ U17 SDRAM U0 ~ U8 • 10Ω CLK0/1/2/3 U6/U7/U5/U8 • U10/U12/U9/U13 10Ω DQn VDD Vss • • Every DQpin of SDRAM • • Two 0.1uF Capacitors per each SDRAM U1/U3/U0/U4 • U15/U16/U14/U17 • U2/U11 1.5pF*1 To all SDRAMs *1 : For 4 loads, CLK2 & CLK3 only. REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Voltage on any pin relative to Vss Parameter VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power dissipation PD 18 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Supply voltage Input leakage current Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) CAPACITANCE Pin Address (A0 ~ A12, BA0 ~ BA1) RAS, CAS, WE Symbol Min Max Unit CADD 85 105 pF CIN 85 105 pF CKE (CKE0 ~ CKE1) CCKE 50 65 pF Clock (CLK0 ~ CLK3) CCLK 40 45 pF CS (CS0, CS2) CCS 30 40 pF DQM (DQM0 ~ DQM7) CDQM 25 30 pF DQ (DQ0 ~ DQ63) COUT1 10 15 pF CB (CB0 ~ CB7) COUT2 10 15 pF REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Burst length = 1 tRC ≥ tRC(min) IO = 0 mA -7A -1H -1L 1170 1080 1080 1080 36 CKE & CLK ≤ VIL(max), tCC = ∞ 36 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 360 Unit Note mA 1 mA mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 180 CKE ≤ VIL(max), tCC = 10ns 108 CKE & CLK ≤ VIL(max), tCC = ∞ 108 CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 540 mA CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 450 mA ICC4 IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) ICC6 -7C CKE ≤ VIL(max), tCC = 10ns Operating current (Burst mode) Self refresh current Version Test Condition CKE ≤ 0.2V 1260 1260 2250 2070 mA 1170 1170 mA 1 1980 1980 mA 2 C 54 mA L 27 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -7C -7A -1H -1L Unit Note Row active to row active delay tRRD(min) 15 15 20 20 ns 1 RAS to CAS delay tRCD(min) 15 20 20 20 ns 1 Row precharge time tRP(min) 15 20 20 20 ns 1 Row active time tRAS(min) 45 45 50 50 ns 1 tRAS(max) 100 Row cycle time tRC(min) ns 1 Last data in to row precharge tRDL(min) 2 CLK 2, 5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 tCCD(min) 1 CLK 3 2 ea 4 Col. address to col. address delay Number of valid output data CAS latency=3 60 65 us 70 70 CAS latency=2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter -7C Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 7.5 1000 7.5 tSAC CAS latency=2 CAS latency=3 -7A Max tOH CAS latency=2 Min 7.5 -1H Max 1000 10 -1L Min 10 Max 1000 10 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 5.4 5.4 6 6 5.4 6 6 7 3 3 3 3 3 3 3 3 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 2 2 ns 3 Input hold time tSH 0.8 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.4 5.4 6 6 5.4 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H H Bank active & row addr. H X Read & column address Auto precharge disable H X Write & column address Auto precharge disable L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H H L H L L X H L Exit L H Entry H L Precharge power down mode Exit L V Column address (A0 ~ A9) L X X All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 Column address (A0 ~ A9) H H Clock suspend or active power down 3 Row address H H Note 1,2 X Auto precharge enable Bank selection A12,A11 A 9 ~ A0 3 Auto precharge enable Burst stop A10/AP L L Precharge BA0,1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS PACKAGE DIMENSIONS Units : Inches (Millimeters) 5.250 (133.350) R 0.079 (R 2.000) 0.157 ± 0.004 (4.000 ± 0.100) 0.350 (8.890) B A .118DIA ± 0.004 (3.000DIA ± 0.100) 0.250 (6.350) .450 (11.430) 0.100 Min (2.540 Min) 0.700 (17.780) 0.118 (3.000) 1.375 (34.925) 0.089 (2.26) 5.014 (127.350) 0.118 (3.000) C 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) 0.200 Min (5.08 Min) 0.150 Max (3.81 Max) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail A (2.540 Min) 0.050 ± 0.0039 (1.270 ± 0.10) 0.039 ± 0.002 (1.000 ± 0.050) 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) Detail B 0.008 ± 0.006 (0.200 ± 0.150) 0.050 (1.270) Detail C Tolerances : ± 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOP SDRAM Part No. : K4S560832C REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS M374S6453CTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L • Organization : 64MX64 • Composition : 32MX8 *18 • Used component part # : K4S560832C-TL7C/7A/1H/1L,TC7C/7A/1H/1L • # of rows in module : 2row • # of banks in component : 4 banks • Feature : 1,375 mil height & double sided component • Refresh : 8K/64ms • Contents : Byte#. Function Supported Function described -7C -7A -1H Hex value -1L -7C -7A -1H 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 # of module Rows on this assembly 6 Data width of this assembly 72 bits 48h 7 ...... Data width of this assembly - 00h 8 Voltage interface standard of this assembly 9 SDRAM cycle time from clock @CAS latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h 5.4ns 5.4ns 6ns 6ns 54h 54h 10 SDRAM access time from clock @CAS latency of 3 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 19 SDRAM device attributes : CS latency 20 SDRAM device attributes : Write latency 21 SDRAM module attributes 22 SDRAM device attributes : General 128bytes 80h 256bytes (2K-bit) 08h Note -1L SDRAM 04h 13 0Dh 1 10 0Ah 1 2 Row 02h LVTTL 01h ECC 02h 7.8us, support self refresh self 82h x8 08h x8 08h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 2&3 06h 0 CLK 01h 0 CLK 01h Non-buffered/Non-Registered & A0h A0h 2 60h 60h 2 00h redundant addressing +/- 10% voltage tolerance, 0Eh Burst Read Single bit Write precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 10ns 12ns 75h A0h A0h C0h 2 24 SDRAM access time @CAS latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2 25 SDRAM cycle time @CAS latency of 1 - 00h 2 26 SDRAM access time @CAS latency of 1 - 00h 2 27 Minimum row precharge time (=tRP) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 15ns 15ns 20ns 20ns 0Fh 0Fh 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 45ns 45ns 50ns 50ns 2Dh 2Dh 32h 32h 31 Module Row density 32 Command and Address signal input setup time 2ns 15h 15h 20h 20h 2 Row of 256MB 1.5ns 1.5ns 2ns 40h 33 Command and Address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 34 Data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h REV. 0.1 Sept. 2001 PC133/PC100 Unbuffered DIMM M374S6453CTS SERIAL PRESENCE DETECT INFORMATION Byte # 35 36~61 Data signal input hold time -7C -7A 0.8ns 0.8ns Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 Function Supported Function described Manufacturing location 73 Manufacturer part # (Memory module) 74 Manufacturer part # (DIMM configuration) 75 Manufacturer part # (Data bits) 76 77 -1L -7C -7A 1ns 1ns 08h 08h - Note -1H -1L 10h 10h 4Ch 7Ch 00h Current release Intel spd 1.2B/A - ...... Manufacturer JEDEC ID code 72 Hex value -1H 12h A4h E5h Samsung CEh Samsung 00h Onyang Korea 01h M 4Dh 3 33h Blank 20h ...... Manufacturer part # (Data bits) 7 37h ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 6 36h 80 ...... Manufacturer part # (Module depth) 4 34h 81 Manufacturer part # (Refresh, # of banks in Comp. & inter- 5 35h 82 Manufacturer part # (Composition component) 3 33h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) S 53h 86 Manufacturer part # (Hyphen) "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 7 7 L/C 1 1 37h 37h 4Ch / 43h 31h 31h 89 Manufacturer part # (Minimum cycle time) C A H L 43h 41h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 Manufacturing date (Year) 94 Blank 20h S 53h C-die (4th Gen.) 43h - - 3 Manufacturing date (Week) - - 3 95~98 Assembly serial # - - 4 99~12 Manufacturer specific data (may be used in future) Undefined - 5 100MHz 64h 126 System frequency for 100MHz 127 Intel Specification details Detailed 100MHz Information 128+ Unused storage locations Undefined FFh FFh FFh - FDh 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung ′s own purpose. REV. 0.1 Sept. 2001