M464S0924DTS PC133/PC100 SODIMM M464S0924DTS SDRAM SODIMM 8Mx64 SDRAM SODIMM based on 8Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung M464S0924DTS is a 8M bit x 64 Synchronous • Performance range Dynamic RAM high density memory module. The Samsung M464S0924DTS consists of four CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glassepoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S0924DTS is a Small Outline Dual In-line Part No. Max Freq. (Speed) M464S0924DTS-L7C/C7C M464S0924DTS-L7A/C7A 133MHz (7.5ns @ CL=2) 133MHz (7.5ns @ CL=3) M464S0924DTS-L1H/C1H 100MHz (10ns @ CL=2) M464S0924DTS-L1L/C1L 100MHz (10ns @ CL=3) • • • • • Burst mode operation Auto & self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,000mil) , double sided component Memory Module and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Back Pin Front Pin Back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 V SS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 V SS DQM0 DQM1 V DD A0 A1 A2 V SS DQ8 DQ9 DQ10 DQ11 V DD DQ12 DQ13 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 V SS DQ32 DQ33 DQ34 DQ35 V DD DQ36 DQ37 DQ38 DQ39 V SS DQM4 DQM5 V DD A3 A4 A5 V SS DQ40 DQ41 DQ42 DQ43 V DD DQ44 DQ45 51 53 55 57 59 DQ14 DQ15 V SS NC NC 52 54 56 58 60 DQ46 DQ47 V SS NC NC 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 Pin 95 97 99 101 103 105 Voltage Key 107 109 CLK0 62 CKE0 111 V DD 64 V DD 113 RAS 66 CAS 115 WE 68 *CKE1 117 CS0 70 *A12 119 *CS1 72 *A13 121 DU 74 *CLK1 123 V SS 76 V SS 125 NC 78 NC 127 NC 80 NC 129 V DD 82 V DD 131 DQ16 84 DQ48 133 DQ17 86 DQ49 135 DQ18 88 DQ50 137 DQ19 90 DQ51 139 V SS 92 V SS 141 DQ20 94 DQ52 143 Front DQ21 DQ22 DQ23 V DD A6 A8 V SS A9 A10/AP V DD DQM2 DQM3 V SS DQ24 DQ25 DQ26 DQ27 V DD DQ28 DQ29 DQ30 DQ31 V SS **SDA V DD PIN NAMES Pin Back 96 DQ53 98 DQ54 100 DQ55 102 V DD 104 A7 106 BA0 108 V SS 110 BA1 112 A11 114 V DD 116 DQM6 118 DQM7 120 V SS 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 V DD 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 V SS 142 **SCL 144 V DD Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 Clock input CKE0 Clock enable input CS0 Chip select input RAS Row address storbe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM V DD Power supply (3.3V) V SS Ground SDA Serial data I/O SCL Serial clock DU Don′t use NC No connection * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) D Q0 ~ Data input/output Data inputs/outputs are multiplexed on the same pins. Power supply/ground Power and ground for the input buffers and the core logic. 63 V DD /VSS Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM FUNCTIONAL BLOCK DIAGRAM CS0 DQM0 DQM4 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 CS U0 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM5 DQM2 CS U2 DQM6 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS U1 UDQM DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 A0 ~ A11, BA0 & 1 SDRAM U0 ~ U3 RAS SDRAM U0 ~ U3 SCL CAS SDRAM U0 ~ U3 47KΩ WE SDRAM U0 ~ U3 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Serial PD CKE0 SDRAM U0 ~ U3 WP SA0 SA1 SA2 SDA U0 10Ω DQn U3 UDQM DQM7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS Every DQ pin of SDRAM CLK0 U1 U2 V DD Three 0.1uF X7R 0603Capacitors per each SDRAM Vss U3 To all SDRAMs 10Ω CLK1 10pF Note : Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs. Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V I N, VOUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss V DD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Storage temperature Power dissipation PD 4 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C) Symbol Min Typ Max Unit Supply voltage Parameter V DD 3.0 3.3 3.6 V Input high voltage V IH 2.0 3.0 V DDQ +0.3 V 1 Input low voltage V IL -0.3 0 0.8 V 2 Output high voltage VO H 2.4 - - V IOH = -2mA Output low voltage V OL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note Notes : 1. V I H (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ V IN ≤ V DDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Symbol Min Max Unit Input capacitance (A 0 ~ A 11, BA0 ~ BA1) CIN1 15 25 pF Input capacitance (RAS , CAS, WE) CIN2 15 25 pF Input capacitance (CKE0) CIN3 15 25 pF Input capacitance (CLK0) CIN4 15 21 pF Input capacitance (CS0 ) CIN5 15 25 pF Input capacitance (DQM0 ~ DQM7) CIN6 10 12 pF Data input/output capacitance (DQ0 ~ DQ63) C OUT 10 12 pF Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70°C) Parameter Operating current (One bank active) Precharge standby current in power-down mode ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA -7C -7A -1H -1L 440 400 400 400 Unit Note mA 1 CKE ≤ V IL(max), tCC = 10ns 8 ICC2PS CKE & CLK ≤ V IL (max), tCC = ∞ 8 ICC2 N CKE ≥ V I H(min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 80 CKE ≥ V I H(min), CLK ≤ V IL (max), t CC =∞ Input signals are stable 40 ICC3 P CKE ≤ V IL(max), tCC = 10ns 20 ICC3PS CKE & CLK ≤ V IL (max), tCC = ∞ 20 ICC3 N CKE ≥ V I H(min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 120 mA CKE ≥ V I H(min), CLK ≤ V IL (max), t CC =∞ Input signals are stable 100 mA ICC2 NS Active standby current in non power-down mode (One bank active) Test Condition ICC2 P Precharge standby current in non power-down mode Active standby current in power-down mode Version Symbol ICC3 NS mA mA mA ICC4 IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs 560 560 520 520 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 880 800 760 760 mA 2 Self refresh current ICC6 CKE ≤ 0.2V Operating current (Burst mode) Notes : C 8 mA L 3.2 mA 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(V IH /VIL=VDDQ /VSSQ) Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200Ω 50Ω V OH (DC) = 2.4V, I O H = -2mA V OL (DC) = 0.4V, I OL = 2mA Output 870Ω Output Z0 = 50Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol - 7C - 7A - 1H -1L Unit Note Row active to row active delay tRRD(min) 15 15 20 20 ns 1 RAS to CAS delay tRCD(min) 15 20 20 20 ns 1 Row precharge time tRP (min) 15 20 20 20 ns 1 tRAS(min) 45 45 50 50 ns 1 Row active time tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL (min) Last data in to Active delay 100 ns 1 2 CLK 2,5 tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL (min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 Number of valid output data 60 65 us 70 CAS latency=3 2 CAS latency=2 1 70 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Parameter - 7C Symbol Min CLK cycle time CAS latency=3 CLK to valid output delay CAS latency=3 Output data hold time CAS latency=3 tCC CAS latency=2 7.5 - 7A Max 1000 7.5 tSAC CAS latency=2 tO H CAS latency=2 Min 7.5 - 1H Max 1000 10 Min 10 - 1L Max 1000 10 Min 10 Unit Note ns 1 ns 1,2 ns 2 Max 1000 12 5.4 5.4 6 6 5.4 6 6 7 3 3 3 3 3 3 3 3 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 2 2 ns 3 Input hold time tSH 0.8 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 CAS latency=2 tSHZ 5.4 5.4 6 6 5.4 6 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh (V=Valid, X=Don′t care, H=Logic high, L=Logic low) CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H H Bank active & row addr. H X Read & column address Auto precharge disable H X Write & column address Auto precharge disable L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H H L H L L X Exit Entry H L H L H L Precharge power down mode Exit L V Column address (A0 ~ A8 ) L X X All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 Column address (A0 ~ A8 ) H H Clock suspend or active power down 3 Row address H H Note 1,2 X Auto precharge enable Bank selection A 11, A9 ~ A 0 3 Auto precharge enable Burst stop A 10/AP L L Precharge BA 0,1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 Notes : 1. OP Code : Operand code A 0 ~ A 11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10 /AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.66 (67.56) 2.50 (63.60) 0.13 (3.30) 59 61 0.91 (23.20) 143 2 -φ 0.07 (1.80) 1.29 (32.80) 0.18 (4.60) 0.083 (2.10) 0.10 (2.50) 1 .0 0 0.79 0.24 (6.0) 1 (20 .0 0) 0.16 ± 0.039 (4.00 ± 0.10) ( 25.40 ) 2-R 0.078 Min (2.00 Min) Z Y 0.15 (3.70) 62 144 0.157 Min (4.00 Min ) (3.20 Min ) 0 .1 25 Min 0.150 Max (3.80 Max) 0.16 ± 0.0039 (4.00 ± 0.10) 0.06 ± 0.0039 (1.50 ± 0.1) 0.04 ± 0.0039 (1.00 ± 0.10) Detail Z 0 .1 00 Min 60 (2 .5 40 Min) 2 0.024 ± 0.001 (0.600 ± 0.050) 0.008 ± 0.006 (0.200 ± 0.150) 0.03 TYP (0.80 TYP) Detail Y Tolerances : ± 0.006(.15) unless otherwise specified The used device is 8Mx16 SDRAM, TSOP SDRAM Part No. : K4S281632D Rev. 0.1 Sept. 2001 M464S0924DTS PC133/PC100 SODIMM M464S0924DTS-C7C/L7C/C7A/L7A/C1H/L1H/C1L/L1H • • • • • • • • Organization : 8Mx64 Composition : 8Mx16 * 4 Used component part # : K4S281632D-TC7C/TL7C/TC75/TL75/TC1H/TL1H/TC1L/TL1L # of rows in module : 1 Row # of banks in component : 4 banks Feature : 1,000mil height & double sided component Refresh : 4K/64ms Contents ; Byte # Function Supported Function Described -7C -7A -1H Hex value -1L -7C -7A -1H 128bytes 80h 256bytes (2K-bit) 08h Note -1L 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 # of row address on this assembly 4 # of column address on this assembly 5 6 7 ...... Data width of this assembly 8 Voltage interface standard of this assembly 9 SDRAM cycle time @CAS latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 5.4ns 6ns 6ns 54h 54h 60h 60h 2 11 DIMM configuraion type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 06h 06h 19 SDRAM device attributes : CS latency 0 CLK 01h 20 SDRAM device attributes : Write latency 0 CLK 01h 21 SDRAM module attributes 22 SDRAM device attributes : General SDRAM 04h 12 0Ch 1 9 09h 1 # of module Rows on this assembly 1 row 01h Data width of this assembly 64 bits 40h - 00h LVTTL 01h Non parity 00h 15.625us, support self refresh 80h x16 10h None 00h t CCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 04h 4 banks 2&3 2&3 2&3 2&3 06h 06h Non-buffered, non-registered 00h & redundant addressing +/- 10% voltage tolerance, 0Eh Burst Read Single bit Write precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 10ns 12ns 75h A0h A0h C0h 2 24 SDRAM access time from clock @CAS latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2 25 SDRAM cycle time @CAS latency of 1 - - - - 00h 00h 00h 00h 26 SDRAM access time from clock @CAS latency of 1 - - - - 00h 00h 00h 00h 27 Minimum row precharge time (=t RP) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 15ns 15ns 20ns 20ns 0Fh 0Fh 14h 14h 29 Minimum RAS to CAS delay (=t RCD) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h 30 Minimum activate precharge time (=tRAS ) 45ns 45ns 50ns 50ns 2Dh 2Dh 32h 32h 31 Module Row density 32 Command and address signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h 33 Command and address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 34 Data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h 10h 1 row of 64MB Rev. 0.1 Sept. 2001 M464S0924DTS Byte # 35 Function Supported Function Described Data signal input hold time 36~61 PC133/PC100 SODIMM -7C -7A 0.8ns 0.8ns Superset information (maybe used in future) 62 SPD data revision code 63 Checksum for bytes 0 ~ 62 64 Manufacturer JEDEC ID code 65~71 Manufacturing location 73 -1L -7C -7A 10ns 10ns 08h 08h - 00h Intel Rev 1.2B 12h - ...... Manufacturer JEDEC ID code 72 Hex value -1H 65h A6h Samsung CEh Samsung 00h Note -1H -1L 10h 10h 0Dh 3Dh Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh 74 Manufacturer part # (DIMM Configuration) 4 34h 75 Manufacturer part # (Data bits) Blank 20h 76 ...... Manufacturer part # (Data bits) 6 36h 77 ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 9 39h 81 Manufacturer part # (Refresh, #of banks in Comp. & Interface) 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) 86 Manufacturer part # (Hyphen) 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 7 7 1 1 37h 37h 31h 31h 89 Manufacturer part # (Minimum cycle time) C A H L 43h 41h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 94 95~98 99~125 53h 2Dh L/C 4Ch / 43h Blank 20h S 53h D-die (5th Gen.) 44h Manufacturing date (Year) - - 3 Manufacturing date (Week) - - 3 Assembly serial # - - 4 Manufacturer specific data (may be used in future) 126 System frequency for 100MHz 127 PC100 specification details 128+ S "-" Unused storage locations Undefined - 100MHz 64h Detailed PC100 Information Undefined 8Fh 8Fh 8Fh 8Dh - Note : 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. Rev. 0.1 Sept. 2001