SAMSUNG M470L3224BTO

M470L3224BT0
200pin DDR SDRAM SODIMM
256MB DDR SDRAM MODULE
(32Mx64 based on 16Mx16 DDR SDRAM)
200pin SODIMM
64-bit Non-ECC/Parity
Revision 0.1
June. 2001
Rev. 0.1 June. 2001
M470L3224BT0
200pin DDR SDRAM SODIMM
Revision History
Revision 0.0 (Apr. 2001)
1. First release.
Revision 0.1 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
M470L3224BT0 200pin DDR SDRAM SODIMM
32Mx64 200pin DDR SDRAM SODIMM based on 16Mx16
FEATURE
GENERAL DESCRIPTION
The Samsung M470L3224BT0 is 32M bit x 64 Double Data
• Performance range
Part No.
Rate SDRAM high density memory modules based on first gen
Max Freq.
Interface
of 256Mb DDR SDRAM respectively.
M470L3224BT0-C(L)A2 133MHz([email protected]=2)
The Samsung M470L3224BT0 consists of eight CMOS 16M x
M470L3224BT0-C(L)B0 133MHz([email protected]=2.5)
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
M470L3224BT0-C(L)A0 100MHz([email protected]=2)
II(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M470L3224BT0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 (mil), double sided component
PIN DESCRIPTION
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
Key
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
41
43
45
47
49
51
53
55
57
59
61
63
65
Pin
Front
Pin
Front
DQ34
DQ27 135
67
VSS
137
VDD
69
DQ35
139
CB0
71
DQ40
141
CB1
73
VDD
143
VSS
75
DQ41
DQS8 145
77
DQS5
147
CB2
79
VSS
149
VDD
81
DQ42
151
CB3
83
DQ43
153
DU
85
VDD
155
VSS
87
VDD
157
CK2
89
VSS
159
/CK2
91
VSS
161
VDD
93
DQ48
CKE1 163
95
DQ49
97 DU(A13) 165
VDD
167
A12
99
DQS6
169
A9
101
DQ50
171
VSS
103
VSS
173
A7
105
DQ51
175
A5
107
DQ56
177
A3
109
VDD
179
A1
111
DQ57
181
VDD
113
DQS7
115 A10/AP 183
VSS
185
BA0
117
DQ58
187
/WE
119
DQ59
189
/S0
121
VDD
191
DU
123
SDA
193
VSS
125
SCL
127 DQ32 195
129 DQ33 197 VDDSPD
199 VDDID
VDD
131
133 DQS4
Pin
Back
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
Key
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
42
44
46
48
50
52
54
56
58
60
62
64
66
Pin
Back
SSTL_2
Pin
Back
136
DQ31
68
138
VDD
70
140
CB4
72
142
CB5
74
144
VSS
76
146
DM8
78
148
CB6
80
150
VDD
82
152
CB7
84
86 DU/(RESET) 154
156
VSS
88
158
VSS
90
160
VDD
92
162
VDD
94
164
CKE0
96
166
DU(BA2)
98
168
A11
100
170
A8
102
172
VSS
104
174
A6
106
176
A4
108
178
A2
110
180
A0
112
182
VDD
114
184
BA1
116
186
/RAS
118
188
/CAS
120
190
/S1
122
192
DU
124
194
VSS
126
196
DQ36
128
198
DQ37
130
200
VDD
132
DM4
134
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Pin Name
*
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS7
Data Strobe input/output
CK0~ CK2,
CK0~ CK2
Clock input
CKE0
Clock enable input
CS0
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DM0 ~ DM7
Data - in mask
VDD
Power supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD identification flag
NC
No connection
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
FUNCTIONAL BLOCK DIAGRAM
S1
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS1
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS2
DM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS3
DM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
S
D0
S
D1
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D7
A0 - A13
A0-A13: DDR SDRAMs D0 - D7
RAS
RAS: SDRAMs D0 - D7
CAS
CAS: SDRAMs D0 - D7
CKE0
CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D7
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
LDQS
S
LDM
I/0 0
I/0 1
I/0 2
D4
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS5
DM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
LDQS
S
LDM
I/0 0
I/0 1
I/0 2
D5
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS6
DM6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS7
DM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
LDQS
S
LDM
I/0 0
I/0 1
I/0 2
D7
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
D3
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
R=120Ω
± 5%
SDRAMs
CK
CK
4 SDRAMs
4 SDRAMs
NC
Card
Edge
*Clock Net Wiring
Serial PD
SCL
D0 - D7
WP
D0 - D7
UDQS
UDM
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
S
Clock Wiring
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
SPD
Strap: see Note 4
D2
Dram1
D0 - D7
D0 - D7
LDQS
S
LDM
I/0 0
I/0 1
I/0 2
D6
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
S
SDA
A0
A1
A2
SA0
SA1
SA2
Dram2
Dram3
Dram4
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Symbol
Value
Unit
VIN, VOUT
-0.5 ~ 3.6
V
VDD
-1.0 ~ 3.6
V
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
8
W
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
2.7
I/O Supply voltage
VDDQ
2.3
2.7
I/O Reference voltage
VREF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination voltage(system)
VTT
VREF-0.04
VREF+0.04
V
2
Input logic high voltage
VIH(DC)
VREF+0.15
VDDQ+0.3
V
4
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
4
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.3
VDDQ+0.6
V
3
Input crossing point voltage, CK and CK inputs
VIX(DC)
1.15
1.35
V
5
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Normal strengh driver)
;VOUT = VTT + 0.84V
IOH
-16.8
mA
Output High Current(Normal strengh driver)
;VOUT = VTT - 0.84V
IOL
16.8
mA
Output High Current(Half strengh driver)
;VOUT = VTT + 0.45V
IOH
-9
mA
Output High Current(Half strengh driver)
;VOUT = VTT - 0.45V
IOL
9
mA
Input leakage current
Unit
Note
V
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on V REF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 June. 2001
M470L3224BT0
200pin DDR SDRAM SODIMM
DDR SDRAM SPEC Items and Test Conditions
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C)
Conditions
Symbol
Typical
Worst
Operating current - One bank Active-Precharge;
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
IDD0
-
-
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
-
-
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD2P
-
-
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
-
-
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
IDD2Q
-
-
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD3P
-
-
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
IDD3N
-
-
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
IDD4R
-
-
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
IDD4W
-
-
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
IDD5
-
-
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
IDD6
-
-
Orerating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7A
-
-
Typical case: VDD = 2.5V, T = 25’C
Worst case : VDD = 2.7V, T = 10’C
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
DDR SDRAM module IDD spec table
Symbol
IDD6
typical
worst
B0([email protected]=2.5)
typical
worst
A0([email protected]=2)
typical
worst
Unit
IDD0
620
680
620
680
540
600
mA
IDD1
760
840
760
840
680
760
mA
IDD2P
320
340
320
340
260
280
mA
mA
IDD2F
380
420
380
420
320
340
IDD2Q
360
380
360
380
300
320
mA
IDD3P
380
400
380
400
320
340
mA
IDD3N
440
480
440
480
360
380
mA
IDD4R
1080
1240
1080
1240
900
1040
mA
IDD4W
1280
1460
1280
1460
1000
1140
mA
IDD5
960
1080
960
1080
880
960
mA
24
24
24
24
24
24
mA
Normal
Low power
IDD7A
* Module
A2([email protected]=2)
12
12
12
12
12
12
mA
1700
1940
1700
1940
1420
1640
mA
IDD was calculated on the basis of component IDD and
Notes
Optional
can be differently measured according to DQ loading cap.
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
IDD7A : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
AC Operating Conditions
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
Max
VREF + 0.31
Unit
Note
V
3
VREF - 0.31
V
3
VDDQ+0.6
V
1
0.5*VDDQ+0.2
V
2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
VREF+0.31/VREF-0.31
V
VREF
V
Vtt
V
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Note
See Load Circuit
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )
CIN1
36
44
pF
Input capacitance(CKE0)
CIN2
36
44
pF
Input capacitance( CS0, CS1)
CIN3
26
30
pF
Input capacitance( CLK0, CLK1)
CIN4
34
38
pF
Data & DQS input/output capacitance(DQ0~DQ63)
COUT
12
14
pF
Input capacitance(DM0~DM8)
CIN5
12
14
pF
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
Parameter
Symbol
Row cycle time
-TCA2(DDR266A) -TCB0(DDR266B)
Min
Max
Min
Max
-TCA0 (DDR200)
Min
Max
Unit
tRC
65
65
70
Refresh row cycle time
tRFC
75
75
80
Row active time
tRAS
45
RAS to CAS delay
tRCD
20
20
20
ns
tRP
20
20
20
ns
Row active to Row active delay
tRRD
15
15
15
ns
Write recovery time
tWR
2
2
2
tCK
tCDLR
1
1
1
tCK
Row precharge time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
tCCD
CL=2.0
CL=2.5
tCK
120K
1
45
120K
1
ns
ns
48
120K
1
7.5
12
10
12
7.5
12
7.5
12
ns
tCK
10
12
ns
5
12
ns
5
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
ns
DQS-out access time from CK/CK
tDQSCK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
Output data access time from CK/CK
tAC
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
Data strobe edge to ouput data edge
tDQSQ
-
+0.5
-
+0.5
-
+0.6
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
0.9
1.1
0.9
tIS
0.9
0.9
1.1
ns
6
Address and Control Input hold time
tIH
0.9
0.9
1.1
ns
6
Data-out high impedence time from CK/CK
tHZ
tACmin 400ps
tACmax
- 400ps
tACmin
- 400ps
tACmax
- 400ps
tACmin
- 400ps
tACmax
- 400ps
ps
Data-out low impedence time from CK/CK
tLZ
tACmin 400ps
tACmax
- 400ps
tACmin
- 400ps
tACmax
- 400ps
tACmin
- 400ps
tACmax
- 400ps
ps
tSL(I)
0.5
Input Slew Rate(for I/O pins)
tSL(IO)
0.5
Output Slew Rate(x4,x8)
tSL(O)
1.0
Output Slew Rate(x16)
tSL(O)
0.7
5
0.7
5
Output Slew Rate Matching Ratio(rise to fall)
tSLMR
0.67
1.5
0.67
1.5
0.5
0.5
4.5
1.0
1.1
2
tDSC
0.5
0.9
5
Address and Control Input setup time
Input Slew Rate(for input only pins)
1.1
Note
V/ns
0.5
4.5
tCK
6
V/ns
7
4.5
V/ns
10
0.7
5
V/ns
10
0.67
1.5
1.0
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
Parameter
Mode register set cycle time
Symbol
-TCA2(DDR266A)
Min
Max
-TCB0(DDR266B)
Min
Max
-TCA0 (DDR200)
Min
Max
Unit
Note
tMRD
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.5
0.5
0.6
ns
7,8,9
DQ & DM hold time to DQS
tDH
0.5
0.5
0.6
ns
7,8,9
DQ & DM input pulse width
tDIPW
1.75
1.75
2
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
95
116
ns
Exit self refresh to bank active command
tXSA
75
75
80
ns
Exit self refresh to read command
tXSR
200
200
200
Cycle
tREF
15.6
15.6
15.6
us
1
7.8
7.8
7.8
us
1
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns
5
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
Refresh interval time
64Mb, 128Mb
256Mb
Output DQS valid window
tQH
tHPmin
-tQHS
Clock half period
tHP
tCLmin
or tCHmin
Data hold skew factor
DQS write postamble time
tQHS
tWPST
0.75
0.25
0.75
0.25
0.8
0.25
4
ns
tCK
3
Note : 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DINNs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half
period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
∆tIS
∆tIH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+50
+50
0.3
+100
+100
This derating table is used to increase tIS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
∆tDS
∆tDH
(V/ns)
(ps)
(ps)
0.5
0
0
0.4
+75
+75
0.3
+150
+150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
based on the lesser of AC-AC slew rate and DC-DC slew rate.
8. I/O Setup/Hold Plateau Derating
I/O Input Level
∆tDS
∆tDH
(mV)
(ps)
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
∆tDS
∆tDH
(ns/V)
(ps)
(ps)
0
0
0
±0.25
+50
+50
±0.5
+100
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
A12, A11
A9 ~ A0
Note
Register
Extended MRS
H
X
L
L
L
L
OP CODE
1, 2
Register
Mode Register Set
H
X
L
L
L
L
OP CODE
1, 2
L
L
L
H
X
L
H
H
H
Auto Refresh
Refresh
Entry
Self
Refresh
H
L
L
H
H
X
X
X
Bank Active & Row Addr.
H
X
L
L
H
H
V
Read &
Column Address
H
X
L
H
L
H
V
Write &
Column Address
Exit
H
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
All Banks
Active Power Down
H
X
L
H
L
L
H
X
L
H
H
L
H
X
L
L
H
L
H
X
X
X
Entry
H
L
Exit
L
H
Entry
H
L
Precharge Power Down Mode
Exit
L
DM
H
No operation (NOP) : Not defined
H
H
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
V
V
V
L
X
X
X
X
X
L
H
H
H
3
3
X
V
3
Row Address
L
H
L
H
Column
Address
(A0~A8)
4
Column
Address
(A0~A8)
4
X
V
L
X
H
4
4, 6
7
X
5
X
X
X
H
3
X
8
9
9
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L3224BT0
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
1
39 41
0.456
11.40
0.086
2.15
199
2-φ 0.07
(1.80)
1.896
(47.40)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
0.79
(20.00)
0.24
(6.0)
0.16 ± 0.039
(4.00 ± 0.10)
1.25
(31.75)
Full R 2x
Z
Y
0.098
2.45
200
0.157 Min
(4.00 Min)
0.157 Min
(4.00 Min)
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.04 ± 0.0039
(1.00 ± 0.1)
Detail Z
0.102 Min
40 42
(2.55 Min)
2
0.018 ± 0.001
(0.45 ± 0.03)
0.01
(0.25)
0.024 TYP
(0.60 TYP)
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 16Mx16 SDRAM, TSOP
SDRAM Part No. : K4H561638B-TC/L
Rev. 0.1 June. 2001