SAMSUNG S3P9648

S3C9644/C9648/P9648
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM87RI microcontrollers have
an external interface that provides access to external memory and other peripheral devices.
S3C9644/C9648/P9648 Microcontroller
The S3C9644/C9648/P9648 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87RI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9644 has 4K-bytes of program
memory on-chip and S3C9648 has 8K-bytes.
Using the SAM87RI design approach, the following peripherals were integrated with the SAM87RI core:
— Five configurable I/O ports (32 pins)
— 20 bit-programmable pins for external interrupts
— 8-bit timer/counter with three operating modes
— Low speed USB function
The S3C9644/C9648/P9648 is a versatile microcontroller that can be used in a wide range of low speed USB
support general purpose applications. It is especially suitable for use as a keyboard controller and is available in
a 42-pin SDIP and a 44-pin QFP package.
OTP
The S3C9644/C9648 microcontroller is also available in OTP (One Time Programmable) version, S3P9648.
S3P9648 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The
S3P9648 is comparable to S3C9644/C9648, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9644/C9648/P9648
FEATURES
CPU
Timer/Counter
•
•
One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval
generation function
•
One 8-bit timer/counter with Compare/Overflow
SAM87RI CPU core
Memory
•
4/8K-byte internal program memory (ROM)
•
208-byte RAM
Instruction Set
•
41 instructions
•
IDLE and STOP instructions added for powerdown modes
USB Serial Bus
•
Compatible to USB low speed (1.5 Mbps) device
1.0 specification.
•
1 Control endpoint and 2 Data endpoint
•
Serial bus interface engine (SIE)
— Packet decoding/generation
Instruction Execution Time
•
— CRC generation and checking
1.0 µs at 6 MHz fOSC
Interrupts
•
25 interrupt sources with one vector, each
source has its pending bit
•
One level, one vector interrupt structure
— NRZI encoding/decoding and bit-stuffing
•
8 bytes each receive/transmit USB buffer
Operating Temperature Range
•
– 40 _C to + 85 _C
Operating Voltage Range
Oscillation Circuit
•
6 MHz crystal/ceramic oscillator
•
External clock source (6 MHz)
General I/O
•
1-2
Bit programmable five I/O ports (34 pins total)
— (D+/PS2, D-/PS2 Included)
•
4.0 V to 5.25 V
Package Types
•
42-pin SDIP
•
44-pin QFP
S3C9644/C9648/P9648
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7/INT2
P1.0-P1.7
P2.0-P2.7 / INT0
Port 0
Port 1
Port 2
SAM87RI BUS
Port 3
P3.0
P3.1
P3.2
P3.3/CLO
Port 4
P4.0 / INT1
P4.1 / INT1
P4.2 / INT1
P4.3 / INT1
XIN
OSC
XOUT
Basic
Timer
I/O Port And
Interrupt Control
SAM87RI CPU
USB
TIMER 0
4/8-KB ROM
208-Byte
Register
D+/PS2
D-/PS2
3.3 V OUT
16 bytes
USB
Buffer
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9644/C9648/P9648
PIN ASSIGNMENTS
P3.1
1
42
P3.2
P3.0
2
41
P3.3/CLO
INT0 / P2.0
3
40
D+/PS2
INT0 / P2.1
4
39
D-/PS2
INT0 / P2.2
5
38
3.3 V OUT
INT0 / P2.3
6
37
NC
INT0 / P2.4
7
36
P0.0 / INT
INT0 / P2.5
8
35
P0.1 / INT
INT0 / P2.6
9
34
P0.2 / INT
INT0 / P2.7
10
33
P0.3 / INT
32
P0.4 / INT
31
P0.5 / INT
VDD
11
VSS
12
S3C9644
S3C9648
42-SDIP
XOUT
13
(Top View)
30
P0.6 / INT
XIN
14
29
P0.7 / INT
TEST
15
28
P1.0
INT1 / P4.0
16
27
P1.1
INT1 / P4.1
17
26
P1.2
RESET
INT1 / P4.2
18
25
P1.3
19
24
P1.4
INT1 / P4.3
20
23
P1.5
21
22
P1.6
P1/7
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
1-4
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4 /INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
32
31
29
28
27
26
25
24
23
30
NC
PRODUCT OVERVIEW
33
S3C9644/C9648/P9648
34
22
P1.0
D-/PS2
35
21
P1.1
D+/PS2
36
20
P1.2
P3.3/CLO
37
19
P1.3
18
P1.4
17
P1.5
16
P1.6
15
P1.7
3.3 V OUT
10
11
P4.0/INT1
P4.1/INT1
VSS
9
RESET
TEST
12
8
44
XIN
P2.3/INT0
XOUT
P4.2/INT1
7
13
5
6
43
VDD
P2.2/INT0
4
P4.3/INT1
3
14
2
42
INT0 / P2.6
INT0 / P2.7
P2.1/INT0
39
P3.0
INT0 / P2.5
41
P3.1
1
P2.0/INT0
(Top View)
38
INT0 / P2.4
40
S3C9644
S3C9648
44-QFP
P3.2
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
1-5
PRODUCT OVERVIEW
S3C9644/C9648/P9648
PIN DESCRIPTIONS
Table 1-1. S3C9644/C9648/P6408 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Number
Pin
Numbers
Share
Pins
P0.0-P0.7
I/O
B
36-29
(30-23)
INT2
P1.0-P1.7
I/O
B
28-21
(22-15)
–
P2.0-P2.7
I/O
B
3-10
(41-44, 1-4)
INT0
P3.0-P3.3
I/O
C
2, 1, 42, 41
(40-37)
P3.3/CL
O
P4.0-P4.3
I/O
D
16, 17, 19, 20
(10, 11, 13,
14)
INT1
D+/PS2
D-/PS2
3.3 VOUT
I/O
Bit-programmable I/O port for Schmitt trigger input
or open-drain output. Port0 can be individually
configured as external interrupt inputs. Pull-up
resistors are assignable by software.
Bit-programmable I/O port for Schmitt trigger input
or open-drain output. Pull-up resistors are
assignable by software.
Bit-programmable I/O port for Schmitt trigger input
or open-drain output. Port2 can be individually
configured as external interrupt inputs. Pull-up
resistors are assignable by software.
Bit-programmable I/O port for Schmitt trigger input,
open-drain or push-pull output. P3.3 can be used to
system clock output(CLO) pin.
Bit-programmable I/O port for Schmitt trigger input
or open-drain output or push-pull output. Port4 can
be individually configured as external interrupt
inputs. In output mode, pull-up resistors are
assignable by software. But in input mode, pull-up
resistors are fixed.
Programmable port for
USB
interface or PS2 interface.
3.3 V output from internal voltage regulator
–
40-39 (36-35)
–
–
38 (34)
–
XIN, XOUT
–
–
I
RESET
I
A
TEST
I
RESET signal input pin. Input with internal pull-up
resistor.
Test signal input pin (for factory use only;
connected to VSS)
14, 13
(8, 7)
3-10, 16,17,
19, 20, 29-36
(30-23, 41-44,
1-4, 10, 11,
13, 14)
18 (12)
–
INT0
INT1
INT2
System clock input and output pin (crystal/ceramic
oscillator, or external clock source)
External interrupt for bit-programmable port0, port2
and port4 pins when set to input mode.
–
15 (9)
–
VDD
–
Power input pin
–
11 (5)
–
VSS
–
Ground input pin
–
12, (6)
–
NC
–
No connection
–
37
(31,32, 33)
–
–
–
NOTE: Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.
1-6
PORT2/
PORT4/
PORT0
–
S3C9644/C9648/P9648
PRODUCT OVERVIEW
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C9644/C9648/P6408
Circuit Number
Circuit Type
S3C9644/C9648/P6408 Assignments
A
I
B
I/O
Ports 0, 1, and 2
C
I/O
Port 3
D
I/O
Port 4
RESET signal input
V DD
Pull-Up
Resistor
VDD
Pull-Up Enable
PULL-UP
RESISTOR
IN
Output
Disable
Noise
Filter
VSS
Input
Data
Figure 1-4. Pin Circuit Type A (RESET)
I/O
Output
Data
MUX
D0
D1
Mode
Input Data
Output
D0
Input
D1
Figure 1-5. Pin Circuit Type B (Ports 0, 1 and 2)
1-7
PRODUCT OVERVIEW
S3C9644/C9648/P9648
VDD
Output
Data
Open
Drain
I/O
Output
Disable
VSS
Input
Data
MUX
D0
D1
Mode
Input Data
Output
D0
Input
D1
Figure 1-6. Pin Circuit Type C (Port 3)
1-8
S3C9644/C9648/P9648
PRODUCT OVERVIEW
V DD
Pull-Up
Resistor
Pull-Up
Enable
V DD
Output
Data
Open
Drain
I/O
Output
Disable
VSS
Input
Data
MUX
D0
D1
Mode
Input Data
Output
D0
Input
D1
Figure 1-7. Pin Circuit Type D (Port 4)
1-9
PRODUCT OVERVIEW
S3C9644/C9648/P9648
APPLICATION CIRCUIT
5V
5V
VDD
0
Port 0
Port 3
1
2
Port 1
3
15
XIN
XOUT
S3C9644
S3C9648
S3P9648
0
1
2
Port 2
RESET
DP
DM
D+/PS2
D-/PS2
7
Port 4
H
O
S
T
3
KEYBOARD
MATRIX
VSS1
NOTE:
Port4 can use expend keyboard MATRIX.
D+/PS2, D-/PS2 can use PS2 keyboard interface (see PS2CONINT, page 4-25).
Port 4.2, 4.3 can use PS2 mouse interface.
Port 3 can use LED direct drive.
Figure 1-8. Keyboard Application Circuit Diagram
1-10
S3C9644/C9648/P9648
12
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9644/C9648/P9648 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— Input/Output capacitance
— A.C. electrical characteristics
— Input timing for external interrupt (Ports 0, 2 and 4) D+/PS2, D-/PS2 : PS2 Mode Only
— Input timing for RESET
— Oscillator characteristics
— Oscillation stabilization time
— Clock timing measurement points at XIN
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a reset
— Stop mode release timing when initiated by an external interrupt
— Characteristic curves
12-1
ELECTRICAL DATA
S3C9644/C9648/P9648
Table 12-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Symbol
Conditions
Rating
Unit
Supply Voltage
VDD
–
– 0.3 to + 6.5
V
Input Voltage
VIN
All input ports
– 0.3 to VDD + 0.3
V
Output Voltage
VO
All output ports
– 0.3 to VDD + 0.3
V
Output Current High
IOH
One I/O pin active
– 18
mA
All I/O pins active
– 60
One I/O pin active
+ 30
Total pin current for ports 3
+ 100
Total pin current for ports 0, 1, 2, 4
+ 100
Output Current Low
IOL
mA
Operating
Temperature
TA
–
– 40 to + 85
°C
Storage
Temperature
TSTG
–
– 65 to + 150
°C
12-2
S3C9644/C9648/P9648
ELECTRICAL DATA
Table 12-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.25 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
4.0
5.0
5.25
V
0.8 VDD
–
VDD
V
Operating Voltage
VDD
f OSC = 6 MHz
(instruction clock = 1 MHz)
Input High Voltage
VIH1
All input pins except VIH2
VIH2
XIN
VIH3
RESET
VIL1
All input pins except VIL2
VIL2
XIN
VIL2
RESET
Output High
Voltage
VOH
IOH = – 200 µA; All output
ports except ports 0, 1 and 2,
D+, D–
VDD – 1.0
–
–
V
Output Low Voltage
VOL
IOL = 1 mA
All output port except D+, D–
–
–
0.4
V
Output Low Current
IOL
VOL = 3V
8
15
23
mA
Input Low Voltage
VDD – 0.5
VDD
0.5VDD
–
–
0.2 VDD
V
0.4
0.5VDD
Port 3 only
Input High
Leakage Current
Input Low
Leakage Current
ILIH1 (3)
VIN = VDD
All inputs except ILIH2
except D+, D–
–
–
3
µA
ILIH2 (3)
VIN = VDD
XIN, XOUT, RESET
–
–
20
µA
ILIL1 (3)
VIN = 0 V
All inputs except ILIL2
except D+, D–
–
–
–3
µA
ILIL2 (3)
VIN = 0 V
XIN, XOUT, RESET
–
–
– 20
µA
12-3
ELECTRICAL DATA
S3C9644/C9648/P9648
Table 12-2. D.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.25 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Output High
Leakage Current
ILOH (1)
VOUT = VDD
All I/O pins and output pins
except D+, D–
–
–
3
µA
Output Low
Leakage Current
ILOL (1)
VOUT = 0 V
All I/O pins and output pins
except D+, D–
–
–
–3
µA
Pull-up Resistors
RL1
VIN = 0 V
Ports 0, 1, 2, 4.2-3, Reset
25
50
100
kΩ
RL2
VIN = 0 V; P4.0-1
IDD1
Normal operation mode
6 MHz CPU clock
5.5
12
mA
IDD2
Idle mode; 6 MHz oscillator
2.2
5
mA
IDD3
Stop mode
180
300
µA
Supply Current (2)
2.4
–
NOTES:
1. Except XIN and XOUT.
2.
3.
Supply current does not include current drawn through internal pull-up resistors or external output current loads.
When USB Mode Only in 4.2 V to 5.25 V, D+ and D– satisfy the USB spec 1.0.
12-4
S3C9644/C9648/P9648
ELECTRICAL DATA
Table 12-3. Input/Output Capacitance
(TA = – 40 °C to + 85 °C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are connected to VSS
–
–
10
pF
Output
Capacitance
COUT
Min
Typ
Max
Unit
P0, P2 and P4
–
200
–
ns
RESET
10
–
–
µs
CIO
I/O Capacitance
Table 12-4. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.25 V)
Parameter
Interrupt Input
High, Low Width
Symbol
tINTH, tINTL
tRSL
RESET Input
Low Width
Conditions
t INTL
t INTH
0.8 V DD
0.2 VDD
Figure 12-1. Input timing for external interrupt (Ports 0, 2, and 4)
t RSL
RESET
0.5V DD
Figure 12-2. Input Timing for RESET
12-5
ELECTRICAL DATA
S3C9644/C9648/P9648
Table 12-5. Oscillator Characteristics
(TA = – 40°C + 85°C, VDD = 4.0 V to 5.25 V)
Oscillator
Main crystal Main
ceramic (fOSC)
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
–
6.0
–
MHz
Oscillation frequency
–
6.0
–
Min
Typ
Max
Unit
–
–
10
ms
XIN
C1
C2
XOUT
External clock
XIN
XOUT
Table 12-6. Oscillation Stabilization Time
(TA = – 40°C + 85°C, VDD = 4.0 V to 5.25 V)
Oscillator
Test Condition
Main Crystal
f OSC = 6.0 MHz
Main Ceramic
(Oscillation stabilization occurs when VDD is equal to
the minimum oscillator voltage range.)
Oscillator
Stabilization Wait
Time
tWAIT stop mode release time by a reset
–
216/
f OSC
–
tWAIT stop mode release time by an interrupt
–
(note)
–
NOTE: The oscillator stabilization wait time, tWAIT, is determined by the setting in the basic timer control register, BTCON.
12-6
S3C9644/C9648/P9648
ELECTRICAL DATA
Table 12-7. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C to + 85°C)
Parameter
Symbol
Conditions
Data Retention
Supply Voltage
VDDDR
Stop mode
Data Retention
Supply Current
IDDDR
Stop mode; VDDDR = 2.0 V
Min
Typ
Max
Unit
2.0
–
6
V
–
–
300
µA
1/f OSC
t XL
XIN
t XH
VDD 0.5V
0.4V
Figure 12-3. Clock Timing Measurement Points at XIN
12-7
ELECTRICAL DATA
S3C9644/C9648/P9648
Internal Reset
Operation
∼∼
Stop Mode
Data Retention
Mode
∼∼
VDD
Idle Mode
(Basic Timer
Active)
Normal
Operating
Mode
V DDDR
Execution Of
Stop Instruction
RESET
0.5 V DD
0.5 V DD
t WAIT
∼
Figure 12-4. Stop Mode Release Timing When Initiated by a Reset
Idle Mode
(Basic Timer
Active)
Stop Mode
VDD
∼∼
Data Retention Mode
Normal
Operating
Mode
VDDDR
External
Interrupt
Execution Of
Stop Instruction
0.8 V DD
0.2 V DD
tWAIT
Figure 12-5. Stop Mode Release Timing When Initiated by an External Interrupt
12-8
S3C9644/C9648/P9648
ELECTRICAL DATA
Table 12-8. Low Speed USB Electrical Characteristics
(TA = – 40°C to + 85°C, Voltage Regulator Output V33out = 2.8 V to 3.5 V, typ 3,3 V)
Parameter
Symbol
Conditions
Min
Max
Unit
Tr
CL = 50 pF
75
–
ns
CL = 350 pF
–
300
CL = 50 pF
75
–
CL = 350 pF
–
300
Transition Time:
Rise Time
Fall Time
Tf
Rise/Fall Time Matching
Trfm
(Tr/Tf) CL = 50 pF
80
120
%
Output Signal Crossover Voltage
Vcrs
CL = 50 pF
1.3
2.0
V
Voltage Regulator Output Voltage
V33OUT
with V33OUT to GND 0.1 µF
capacitor
2.8
3.5
V
Test
Point
2.8V
S/W
90%
R2
90%
Measurement
Points
10%
10%
D.U.T
R1
CL
Tr
R1 = 15 K Ω
R2 = 1.5 K Ω
CL = 50pF-350pF
Tf
DM: S/W ON
DP: S/W OFF
Figure 12-6. USB Data Signal Rise and Fall Time
3.3 V
DP
MAX: 2.0 V
Vcrs
MIN: 1.3 V
DM
0V
Figure 12-7. USB Output Signal Crossover Point Voltage
12-9
S3C9644/C9648/P9648
MECHANICAL DATA
13
MECHANICAL DATA
OVERVIEW
The S3C9644/C9648/P9648 is available in a 42-pin SDIP package (Samsung: 42-SDIP-600) and a 44-pin QFP
package (44-QFP-1010B). Package dimensions are shown in Figures 13-1 and 13-2.
#22
+0.1
– 0.0
5
0.25
40-SDIP-600
0.50 ± 0.1
1.00 ± 0.1
1.778
5.08MAX
39.10 ± 0.2
3.30 ± 0.3
39.50 MAX
3.50 ± 0.2
#21
0.51MIN
#1
(1.77)
0-15 °
15.24
14.00 ³ 0.2
#42
Figure 13-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600 )
13-1
MECHANICAL DATA
S3C9644/C9648/P9648
13.20 ± 0.3
0−8°
+0.10
0.15 - 0.05
10.00 ± 0.2
13.20 ± 0.3
0.80 ±0.20
10.00 ± 0.2
44-QFP-1010B
0.10 MAX
#44
0.05 MIN
2.05 ± 0.10
#1
0.35
+0.10
- 0.05
(1.00)
2.30 MAX
0.80
NOTE: Dimensions are in millimeters.
Figure 13-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
13-2
S3C9644/C9648/P9648
14
S3P9648 OTP
S3P9648 OTP
OVERVIEW
The S3P9648 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9644/C9648 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9648 is fully compatible with the S3C9644/C9648, both in function and in pin configuration. Because of
its simple programming requirements, the S3P9648 is ideal for use as an evaluation chip for the
S3C9644/C9648.
P3.1
1
42
P3.2
P3.0
2
41
P3.3/CLO
INT0 / P2.0
3
40
D+
INT0 / P2.1
4
39
D-
INT0 / P2.2
5
38
3.3 V OUT
INT0 / P2.3
6
37
NC
INT0 / P2.4
7
36
P0.0 / INT2
INT0 / P2.5
8
35
P0.1 / INT2
SDAT/INT0 / P2.6
9
34
P0.2 / INT2
S3P9648
42-SDIP
33
P0.3 / INT2
32
P0.4 / INT2
(Top View)
31
P0.5 / INT2
SCLK /INT0 / P2.7
10
VDD/VDD
11
VSS /V SS
12
XOUT/XOUT
13
30
P0.6 / INT2
XIN /XIN
14
29
P0.7 / INT2
TEST/TEST
15
28
P1.0
INT1 / P4.0
16
27
P1.1
INT1 / P4.1
17
26
P1.2
18
25
P1.3
19
24
P1.4
20
23
P1.5
21
22
P1.6
RESET / RESET
INT1 / P4.2
INT1 / P4.3
P1/7
Figure 14-1. S3P9648 Pin Assignments (42-SDIP Package)
14-1
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4 /INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
31
29
28
27
26
25
24
23
30
NC
32
S3C9644/C9648/P9648
33
S3P9648 OTP
3.3 V OUT
34
22
P1.0
D-/PS2
35
21
P1.1
D+/PS2
36
20
P1.2
P3.3/CLO
37
19
P1.3
P3.2
38
18
P1.4
P3.1
39
17
P1.5
P3.0
S3C9648
44-QFP
40
(Top View)
16
P1.6
P1.7
P2.0/INT0
41
15
P2.1/INT0
8
9
10
11
XIN/XIN
TEST/TEST
P4.0/INT1
P4.1/INT1
7
XOUT/XOUT
VSS/ VSS
5
6
VDD/VDD
4
12
3
44
P2.6/INT0/ SDAT
P2.7/INT0/ SCLK
P2.3/INT0
P4.2/INT1
RESET/ RESET
P2.5/INT0
43
2
P4.3/INT1
13
1
14
P2.4/INT0
42
P2.2/INT0
Figure 14-2. S3P9648 Pin Assignments (44-QFP Package)
14-2
S3C9644/C9648/P9648
S3P9648 OTP
Table 14-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P2.6
SDAT
9 (3)
I/O
Serial DATa Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned
P2.7
SCLK
10 (4)
I/O
Serial CLocK Pin (Input Only Pin)
TEST
TEST
15 (9)
I
Chip Initialization and EPROM Cell Writing
Power Supply Pin (Indicates OTP Mode
Entering) When writing 12.5 V is applied and
when reading.
RESET
RESET
18 (12)
I
0 V: OTP write and test mode
5 V: Operating mode
VDD / VSS
VDD / VSS
11(5)/12(6)
–
Logic Power Supply Pin.
NOTE: ( ) means 44 QFP package.
Table 14-2. Comparison of S3P9648 and S3C9644/C9648 Features
Characteristic
S3P9648
S3C9644/C9648
Program Memory
8-Kbyte EPROM
8-Kbyte mask ROM
Operating Voltage (VDD)
4.0 V to 5.25 V
4.0 V to 5.25 V
OTP Programming Mode
VDD = 5 V, VPP (RESET) = 12.5 V
Pin Configuration
42 SDIP/44 QFP
42 SDIP/44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (RESET) pin of the S3P9648, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 14-3. Operating Mode Selection Criteria
VDD
5V
REG/
MEM
ADDRESS
(RESET)
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
VPP
R/W
MODE
(A15-A0)
NOTE: "0" means Low level; "1" means High level.
14-3
S3P9648 OTP
S3C9644/C9648/P9648
START
Address= First Location
VDD =5V, VPP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 14-3. OTP Programming Algorithm
14-4
Increment Address
S3C9644/C9648/P9648
S3P9648 OTP
Table 14-4. D.C. Electrical Characteristics
(TA = – 40_C to + 85_C, VDD = 4.0 V to 5.25 V)
Parameter
Supply Current
Symbol
Conditions
Min
Typ
Max
Unit
–
5.5
12
mA
IDD1
Normal mode;
6 MHz CPU clock
IDD2
Idle mode;
6 MHz CPU clock
2.2
5
IDD3
Stop mode
180
300
(note)
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
14-5