S524C20D11/20D21/80D41/80D81 1K/2K/4K/8K-bit Serial EEPROM Data Sheet OVERVIEW The S524C20D11/20D21/80D41/80D81 serial EEPROM has a 1,024/2,048/4,096/8,192-bit (128/256/512/1,024byte) capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsung’s most advanced CMOS technology. One of its major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using onepage write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524C20D11/20D21/80D41/80D81 is its support for fast mode and standard mode. FEATURES I2C-Bus Interface Operating Characteristics • Two-wire serial interface • • Automatic word address increment Operating voltage — 2.5 V to 5.5 V (write) — 2.2 V to 5.5 V (read) EEPROM • • 1K/2K/4K/8K-bit (128/256/512/1,024-byte) storage area • 16-byte page buffer • — Maximum read current: < 200 µA at 5.5 V Typical 3.5 ms write cycle time with auto-erase function — Maximum stand-by current: < 5 µA at 3.3 V • Hardware-based write protection for the entire EEPROM (using the WP pin) • EEPROM programming voltage generated on chip • 1,000,000 erase/write cycles — 100 kHz at standard mode • 100 years data retention — 400 kHz at fast mode Operating current — Maximum write current: < 3 mA at 5.5 V • Operating temperature range — – 25°C to + 70°C (commercial) — – 40°C to + 85°C (industrial) • • Operating clock frequencies Electrostatic discharge (ESD) — 3,000 V (HBM) — 300 V (MM) Packages • 8-pin DIP, SOP, and TSSOP 3-1 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM SDA Start/Stop Logic HV Generation Timing Control Control Logic WP SCL DATA SHEET Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits A0 A1 A2 Column Decoder Data Register DOUT and ACK Figure 3-1. S524C20D11/20D21/80D41/80D81 Block Diagram 3-2 DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM VCC WP SCL SDA S524C20D11/20D21/ 80D41/80D81 A0 NOTE: A1 A2 VSS The S524C20D11/20D21/80D41/80D81 is available in 8-pin DIP, SOP, and TSSOP package. Figure 3-2. Pin Assignment Diagram Table 3-1. S524C20D11/20D21/80D41/80D81 Pin Descriptions Name Type Description Circuit Type A0, A1, A2 Input Input pins for device address selection. To configure a device address, these pins should be connected to the VCC or VSS of the device. 1 Ground pin. – Bi-directional data pin for the I2C-bus serial data interface. Schmitt trigger input and open-drain output. An external pull-up resistor must be connected to VCC. Typical values for this pull-up resistor are 4.7 kΩ (100 kHz) and 1 kΩ (400 kHz). 3 VSS – SDA I/O SCL Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to VCC, the write function is disabled to protect previously written data in the entire memory; if you tie it to VSS, the write function is enabled. 1 VCC – Single power supply. – NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3. 3-3 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET A0, A1, A2, WP Noise Filter SCL Figure 3-4. Pin Circuit Type 2 Figure 3-3. Pin Circuit Type 1 SDA Data Out VSS Noise Filter Figure 3-5. Pin Circuit Type 3 3-4 Data In DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM FUNCTION DESCRIPTION I2C-BUS INTERFACE The S524C20D11/20D21/80D41/80D81 supports the I2C-bus serial interface data transmission protocol. The twowire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a pull-up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524C20D11/20D21 (four S524C80D41, two for S524C80D81) devices can be connected to the same I2C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus operating mode would be active. VCC VCC R R SDA SCL Slave 1 Bus Master (Transmitter/ Receiver) Slave 2 Slave 3 Slave 8 S524C20D21 Tx/Rx A0 A1 A2 S524C20D21 Tx/Rx A0 A1 A2 S524C20D21 Tx/Rx A0 A1 A2 S524C20D21 Tx/Rx A0 A1 A2 To VCC or V SS To VCC or V SS To VCC or V SS To VCC or V SS MCU NOTES: 1. The A0 does not affect the device address of the S524C80D41. 2. The A0, A1 do not affect the device address of the S524C80D81. 2 Figure 3-6. Typical Configuration (16 Kbits of Memory on the I C-Bus) 3-5 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET I2C-BUS PROTOCOLS Here are several rules for I2C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I2C-bus interface supports the following communication protocols: • Bus not busy: The SDA and the SCL lines remain High level when the bus is not active. • Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition. • Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 3-7). ~ ~ SCL ~ ~ SDA Start Condition Data or Data ACK Valid Change Stop Condition Figure 3-7. Data Transmission Sequence • Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. • ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 3-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. 3-6 DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM Master SCL Line Bit 1 Bit 9 Data from Transmitter ACK from Receiver ACK Figure 3-8. Acknowledge Response From Receiver • Slave Address: After the master initiates a Start condition, it must output the address of the device to be accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier for the S524C20D11/20D21/80D41/80D81 is “1010B”. The next three bits comprise the addr ess of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight S524C20D11/20D21 or four S524C80D41 or two S524C80D81 on the bus (see Table 3-2 below). The b1 for the S524C80D41 or the b1, b2 for S524C80D81 are used by the master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits are in effect the most significant bits of the word address. • Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed. Table 3-2. Slave Device Addressing Device Device Identifier Device Address R/W Bit b7 b6 b5 b4 b3 b2 b1 b0 S524C20D11/20D21 1 0 1 0 A2 A1 A0 R/W S524C80D41 1 0 1 0 A2 A1 B0 R/W S524C80D81 1 0 1 0 A2 B1 B0 R/W NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word. 3-7 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the S524C20D11/20D21/80D41/80D81 slave device (see Figure 3-9). Start Slave Address Word Address A C K Data A C K Stop A C K Figure 3-9. Byte Write Operation Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an R/W bit set to “0” onto the bus. Then the addressed S524C20D11/20D21/80D41/80D81 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into the word address pointer of the S524C20D11/20D21/80D41/80D81. When the S524C20D11/20D21/80D41/80D81 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit data. When it receives the data byte, the S524C20D11/20D21/80D41/80D81 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the S524C20D11/20D21/80D41/80D81 begins the internal write cycle. While the internal write cycle is in progress, all S524C20D11/20D21/80D41/80D81 inputs are disabled and the S524C20D11/20D21/80D41/80D81 does not respond to additional requests from the master. 3-8 DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM PAGE WRITE OPERATION The S524C20D11/20D21/80D41/80D81 can also perform 16-byte page write operation. A page write operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred, the master can transmit up to 15 additional bytes. The S524C20D11/20D21/80D41/80D81 responds with an ACK each time it receives a complete byte of data (see Figure 3-10). Start Slave Address Word Address (n) A C K Data (n) A C K Data (≤ n + 15) A C K A C K Stop A C K Figure 3-10. Page Write Operation The S524C20D11/20D21/80D41/80D81 automatically increments the word address pointer each time it receives a complete data byte. When one byte has been received, the internal word address pointer increments to the next address and the next data byte can be received. If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation, the S524C20D11/20D21/80D41/80D81 word address pointer value “rolls over” and the previously received data is overwritten. If the master transmits less than 16 bytes and generates a stop condition, the S524C20D11/20D21/80D41/80D81 writes the received data to the corresponding EEPROM address. During a page write operation, all inputs are disabled and there is no response to additional requests from the master until the internal write cycle is completed. 3-9 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET POLLING FOR AN ACK SIGNAL When the master issues a stop condition to initiate a write cycle, the S524C20D11/20D21/80D41/80D81 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address. As long as the S524C20D11/20D21/80D41/80D81 remains busy with the write operation, no ACK is returned. When the S524C20D11/20D21/80D41/80D81 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 3-11). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/W bit = "0" No ACK = "0" ? Yes Start Next Operation Figure 3-11. Master Polling for an ACK Signal from a Slave Device 3-10 DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM HARDWARE-BASED WRITE PROTECTION You can also write-protect the entire memory area of the S524C20D11/20D21/80D41/80D81. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored. The S524C20D11/20D21/80D41/80D81 will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged. CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access data at address “n+1”. When the S524C20D11/20D21/80D41/80D81 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the S524C20D11/20D21/80D41/80D81 effectively stops the transmission (see Figure 312). Start Slave Address Data A C K Stop N O A C K Figure 3-12. Current Address Byte Read Operation 3-11 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R/W bit set to “1”, the master must first perform a “ dummy” write operation. This operation is performed in the following steps: 1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the S524C20D11/20D21/80D41/80D81 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed by another slave address, with the R/W bit set to “1”. 3. The S524C20D11/20D21/80D41/80D81 then sends an ACK and the 8-bit data stored at the desired address. 4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead. 5. In response, the S524C20D11/20D21/80D41/80D81 stops transmitting data and reverts to its stand-by mode (see Figure 3-13). Start Slave Address Word Address A C K Start A C K Slave Address Data (n) A C K Stop N O A C K Figure 3-13. Random Address Byte Read Operation 3-12 DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM SEQUENTIAL READ OPERATION Sequential read operations can be performed in two ways: as a series of current address reads or as random address reads. The first data is sent in the same way as the previous read mode used on the bus. The next time, however, the master responds with an ACK, indicating that it requires additional data. The S524C20D11/20D21/80D41/80D81 continues to output data for each ACK it receives. To stop the sequential read operation, the master does not respond with an ACK, but instead issues a Stop condition. Using this method, data is output sequentially with the data from address “n” followed by the data from “n+1”. The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the S524C20D11/20D21/80D41/80D81 continues to transmit data for each ACK it receives from the master (see Figure 3-14). Start Slave Address Data (n) Data (n + x) ~ ~ A C K A C K A C K N O A C K Figure 3-14. Sequential Read Operation 3-13 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET ELECTRICAL DATA Table 3-3. Absolute Maximum Ratings (TA = 25°C) Symbol Conditions Rating Unit Supply voltage VCC – – 0.3 to + 7.0 V Input voltage VIN – – 0.3 to + 7.0 V Output voltage VO – – 0.3 to + 7.0 V Operating temperature TA – – 40 to + 85 °C Storage temperature TSTG – – 65 to + 150 °C Electrostatic discharge VESD HBM 3000 V MM 300 Parameter Table 3-4. D.C. Electrical Characteristics (TA = – 25°C to + 70°C (C), – 40°C to + 85°C (I), VCC = 2.2 V to 5.5 V when reading, 2.5 V to 5.5 V when writing) Parameter Symbol Conditions Min Typ Max Unit – – 0.3 VCC V 0.7 VCC – – V Input low voltage VIL Input high voltage VIH Input leakage current ILI VIN = 0 to VCC – – 10 µA Output leakage current ILO VO = 0 to VCC – – 10 µA Output low voltage VOL IOL = 3 mA, VCC = 2.5 V – – 0.4 V VCC = 5.5 V, 400 kHz – – 3 mA VCC = 3.3 V, 100 kHz – – 1.5 VCC = 5.5 V, 400 kHz – – 0.2 VCC = 3.3 V, 100 kHz – – 0.1 VCC = SDA = SCL = 5.5 V, all other inputs = 0 V – – 10 VCC = SDA = SCL = 3.3 V, all other inputs = 0 V – – 5 Supply current Stand-by current ICC1 (write) ICC2 (write) ICC3 (read) ICC4 (read) ICC5 ICC6 3-14 SCL, SDA, A0, A1, A2 µA DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM Table 3-4. D.C. Electrical Characteristics (Continued) (TA = – 25°C to + 70°C (C), – 40°C to + 85°C (I), VCC = 2.2 V to 5.5 V when reading, 2.5 V to 5.5 V when writing) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN 25°C, 1MHz, VCC = 5 V, VIN = 0 V, A0, A1, A2, SCL and WP pin – – 10 pF Input/output capacitance CI/O 25°C, 1MHz, VCC = 5 V, VI/O = 0 V, SDA pin – – 10 Table 3-5. A.C. Electrical Characteristics (TA = – 25°C to + 70°C (C), – 40°C to + 85°C (I), VCC = 2.2 V to 5.5 V when reading, 2.5 V to 5.5 V when writing) Parameter Symbol Conditions VCC = 2.2 to 5.5 V (Standard Mode) VCC = 4.5 to 5.5 V (Fast Mode) Min Max Min Max Unit External clock frequency FCLK – 0 100 0 400 kHz Clock high time tHIGH – 4 – 0.6 – µs Clock low time tLOW – 4.7 – 1.3 – Rising time tR SDA, SCL – 1 – 0.3 Falling time tF SDA, SCL – 0.3 – 0.3 Start condition hold time tHD:STA – 4 – 0.6 – Start condition setup time tSU:STA – 4.7 – 0.6 – Data input hold time tHD:DAT – 0 – 0 – Data input setup time tSU:DAT – 0.25 – 0.1 – Stop condition setup time tSU:STO – 4 – 0.6 – Bus free time tBUF Before new transmission 4.7 – 1.3 – Data output valid from clock low (note) tAA – 0.3 3.5 – 0.9 Noise spike width tSP – – 100 – 50 ns Write cycle time tWR – – 10 – 10 ms NOTE: When acting as a transmitter, the S524C20D11/20D21/80D41/80D81 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition. 3-15 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM tF DATA SHEET tHIGH tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA In tAA tBUF SDA Out Figure 3-16. Timing Diagram for Bus Operations ~ ~ SCL ~ ~ ~ ~ SDA 8th Bit ACK ~ ~ WORDn tWR Stop Condition Figure 3-17. Write Cycle Timing Diagram 3-16 Start Condition DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM CHARACTERISTIC CURVES NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. (Frequency = 100 kHz) 2.0 1.6 Temp = - 40 °C Temp = - 25 °C 1.2 Temp = 0 °C ICC (mA) Temp = 25 °C 0.8 Temp = 70 °C Temp = 85 °C 0.4 0 2 3 4 5 6 VCC (V) Figure 3-18. ICC (Write Current) vs. VCC 3-17 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET (Frequency = 100 kHz) 120 100 Temp = - 40 °C 80 ICC (µA) Temp = - 25 °C 60 Temp = 0 °C 40 Temp = 70 °C Temp = 25 °C Temp = 85 °C 20 0 2 3 4 5 VCC (V) Figure 3-19. ICC (Read Current) vs. VCC 3-18 6 DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM (Frequency = 100 kHz) 10 8 Temp = - 40 °C Temp = - 25 °C 6 Temp = 0 °C ICC (µA) Temp = 25 °C 4 Temp = 70 °C Temp = 85 °C 2 0 2 3 4 5 6 VCC (V) Figure 3-20. ICC (Stand-by Current) vs. VCC 3-19 S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET (TA = 25 °C) 50 VDD = 5.5 V 40 VDD = 5.0 V VDD = 4.5 V 30 VDD = 4.0 V VDD = 3.5 V IOL (mA) VDD = 3.0 V 20 10 0 0 1 2 3 4 5 VOL (V) Figure 3-21. IOL (Output Low Voltage) vs. VOL 3-20 6