DECODER FOR CD-MP3/CD-ROM S5L9274 INTRODUCTION 64-LQFP-1010 S5L9274 is a single chip ISO/IEC 11172-3 Layer III audio decoder, capable of decoding compressed elementary bit stream as specified in ISO/IEC standard. As a decoder for the DISC-MAN, it can provide you more small and cheaper solution for MP3 player application. S5L9274 is low voltage IC that can read MP3 and CD-ROM format discs and can be applied to various products. FEATURES • Single-chip ISO/IEC 11172-3 Layer III Audio Decoder • Support All MPEG Bit Rates including free format • Support 32/44.1/48 kHz Sampling Frequency for MPEG Bit Stream • Support Single Channel, Dual Channel, Stereo and Joint Stereo • Any Combination of Intensity Stereo & MS Stereo is supported • Serial Host Interface • Simple Software for Micom • Support Off-chip DAC interface • Anti Shock Memory Controller • Power Save Mode : POWER-DOWN, SLEEP (when paused) • Use of Standard Crystal 16.9344MHz • 16.9344MHz Clock Output Port • Soft Mute Function • CDFS(CD-ROM File System) Decoding • Low Power Dissipation : 171mW @3.0 volts ORDERING INFORMATION Device Package Supply Voltage Operating Temperature S5L9274X01-E0R0 64-LQFP-1010 2.8V 3.3V -20°C +75°C 1 S5L9274 DECODER FOR CD-MP3/CD-ROM FUNCTIONAL BLOCK DIAGRAM dspUnit CD-MP3 Decoder Chip cdrUnit (CD-ROM Decoder) Register Set IB read Channel OB write Channel ssp1611 Core + PROM, CROM0,RAM0, CROM1,RAM1 OBL read Channel OBR read Channel memUnit (Memory Management Unit) ckgUnit Host Channel hifUnit (Host Interface) DRAM Controller DRAM Bandwidth Estimated - 1.9M words/sec 1M x 4 bits DRAM Figure1. Functional Block Diagram of S5L9274 2 difUnit (DAC I/F) Host MCU DECODER FOR CD-MP3/CD-ROM S5L9274 APPLICATION DIAGRAM 40pF 16.9344MHz 40pF 2 XI 3 XO 4 XOUT 5 CLK 1K 820pF 10 FILTER0 GND 940pF 14 FILTER1 15 PLL_BYPASS Test Pin Connection 40 SCAN_EN 41 TEST2 42 TEST1 43 TEST0 GND 3 S5L9274 DECODER FOR CD-MP3/CD-ROM VSS OEB DA03 DA02 DA01 DA00 DA09 DA04 DA05 DA06 DA07 DA08 CASB DDAT3 DDAT2 VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN CONFIGURATION VDD 1 48 VSS XI 2 47 RASB XO 3 46 WEB XOUT 4 45 DDAT1 CLK 5 44 DDAT0 RESETB 6 43 TEST0 PLL0 VDDA 7 42 TEST1 PLL0 VSSA 8 41 TEST2 PLL0 VBBA 9 40 SCAN_EN 10 39 MINT PLL1 VDDA 11 38 MDOUT PLL1 VSSA 12 37 MLAT PLL1 VBBA 13 36 MCK FILTER_1 14 35 MDAT PLL_BYPASS 15 34 MCU_CLK VSS 16 33 VDD 25 26 27 28 29 30 31 32 BCLK LRCK ADAT EMP ETYPE N.C N.C VSS 24 ACLK 21 CD LRCK 23 20 CD DATA 22 19 CDP CLK CD BCK 18 ACLK EXT CD C2PO 17 VDD FILTER_0 S5L9274X Figure 2. 64 pin Low profile Quad Flat Package (LQFP) 4 DECODER FOR CD-MP3/CD-ROM S5L9274 PIN DESCRIPTION Pin No Symbol I/O Description 1 VDD P Digital Power 2 XI I X'tal Oscillator input(16.9344MHz) 3 XO O X'tal Oscillator output 4 XOUT O Buffered Output of XO 5 CLK I System Clock input 6 RESETB I System Reset Active LOW 7 PLL0 VDDA P Analog Power for PLL0 8 PLL0 VSSA G Analog Ground for PLL0 9 PLL0 VBBA G Analog Ground for PLL0 10 FILTER_0 O External Capacitor port for PLL0 11 PLL1 VDDA P Analog Power for PLL1 12 PLL1 VSSA G Analog Ground for PLL1 13 PLL1 VBBA G Analog Ground for PLL1 14 FILTER_1 O External Capacitor port for PLL0 15 PLL_BYPASS I Tied to GROUND. 16 VSS G Digital Ground 17 VDD P Digital Power 18 ACLK EXT I External Audio Clock source 19 CD CLK O Clock Output for CD DSP IC 20 CD DATA I Data from CD DSP IC 21 CD LRCK I LRCK from CD DSP IC 22 CD BCK I BCK from CD DSP IC 23 CD C2PO I C2PO from CD DSP IC 24 ACLK O Audio clock to DAC clock input 25 BCLK O BCLK to DAC 26 LRCK O LRCK to DAC 27 ADAT O Data to DAC 28 EMP O Emphasis On/Off 29 ETYPE O Indicates emphasis type 30 N.C - No used 31 N.C - No used 32 VSS G Digital Ground 5 S5L9274 DECODER FOR CD-MP3/CD-ROM PIN DESCRIPTION (Continued) 6 Pin No Symbol I/O Description 33 VDD P Digital Power 34 MCU_CLK O Clock Output for External MCU 35 MDAT I Data input pin 36 MCK I Micom Clock pin 37 MLAT I Data Latch input pin 38 MDOUT O Data from CD-MP3 to MCU 39 MINT O Interrupt output to MCU 40 SCAN_EN I Scan Test enable 41 TEST2 I Tied to GROUND. 42 TEST1 I Tied to GROUND. 43 TEST0 I Tied to GROUND. 44 DDAT0 B Data0 BUS for External DRAM 45 DDAT1 B Data1 BUS for External DRAM 46 WEB O Write Enable for External DRAM 47 RASB O Row Address for External DRAM 48 VSS G Digital Ground 49 VDD P Digital Power 50 DDAT2 B Data2 BUS for External DRAM 51 DDAT3 B Data3 BUS for External DRAM 52 CASB O Column Address for External DRAM 53 DA08 O Address Output8 for DRAM 54 DA07 O Address Output7 for DRAM 55 DA06 O Address Output6 for DRAM 56 DA05 O Address Output5 for DRAM 57 DA04 O Address Output4 for DRAM 58 DA09 O Address Output9 for DRAM 59 DA00 O Address Output0 for DRAM 60 DA01 O Address Output1 for DRAM 61 DA02 O Address Output2 for DRAM 62 DA03 O Address Output3 for DRAM 63 OEB O Output to make data output to " Hi-Z" at DRAM 64 VSS G Digital Ground DECODER FOR CD-MP3/CD-ROM S5L9274 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit power supply voltage VDD -0.3 + 3.8 V Input supply voltage VI 3.3V I/O -0.3 VDD + 0.3 5V-tolerant -0.3 5.5 V Operating temperature TOPR 0 70 °C Storage temperature TSTG -40 125 °C ELECTRICAL CHARACTERISTICS Pin Number Description Pin 10, Pin11 Analog Normal Output Pad with Resistor 50ohm and Separate Bulk Bias Pin2, Pin3 Oscillator Cell with Enable and 1Mohm Resistor Pin4,Pin19,Pin34,Pin38,Pin39,Pin28,Pin29 LVCMOS Normal Output Buffer Pin18,Pin5 LVCMOS-Schmit Trigger Level Input Clock Driver Pin20,Pin21,Pin22,Pin23 5V-tolerant LVCMOS Level Input Buffer Pin6,Pin15,Pin40,Pin41,Pin42,Pin43 5V-tolerant LVCMOS Schmitt Trigger Level Input Buffer Pin35,Pin36,Pin37 LVCMOS Schmitt Trigger Level Input Buffer Pin44,Pin45,Pin50,Pin51 LVCMOS Tri-State Bi-Directional buffer with Pull-Up Pin24,Pin25,Pin26,Pin27,Pin46,Pin47,Pin52,Pin53,Pin Tri-State Output Buffer 54,Pin55,Pin56,Pin57,Pin58,Pin59,Pin60,Pin61,Pin62, Pin63 7 S5L9274 DECODER FOR CD-MP3/CD-ROM VDD = 3.3 ± 0.3V, TA = 0 to 70°C ( In case of normal IO) Symbol Parameter Condition Min VIH High level input voltage (LVCMOS interface) VIL Low level input voltage (LVCMOS interface) VT Switching threshold LVCMOS VT+ Schmitt trigger, positive-going threshold LVCMOS VT- Schmitt trigger, negative-going threshold LVCMOS 0.8 VIN = VDD -10 Type Max 2.0 Unit V 0.8 V 2.0 V 10 uA 1.4 High level input current IIH Input buffer Input buffer with pull-up 10 30 60 Low level input current IIL input buffer Input buffer with pull-up -10 VIN = VSS -60 10 -30 uA -10 High level output voltage VOH Type B1 to B24 Note2 IOH = -1uA VDD-0.05 Type B1 IOH = -1mA 2.4 Type B2 IOH = -2mA V Low level output voltage VOL Type B1 to B24Note2 IOH = 1uA 0.05 Type B1 IOH = 1mA 0.4 V Type B2 IOH = 2mA IOZ Tri-state output leakage current VOUT = VSS or VDD 10 uA IOS Output short circuit current VDD = 3.6V, VO = VDD 210 mA 100note3 uA VDD = 3.6V, VO = VSS -170 IDD Quiescent supply current VIN = VSS or VDD CIN Input capacitanceNote4 Any Input and Bidirectional Buffers 4 pF Output capacitanceNote4 Any Output Buffer 4 pF COUT 8 -10 DECODER FOR CD-MP3/CD-ROM S5L9274 VDD = 3.3 ± 0.3V, VEXT = 5+ 0.25V, TA = 0 to 70°C ( In case of 5V-tolerant IO) Symbol VIH Note1 VIL Note1 VT Parameter Condition High level input voltage (LVCMOS interface) Min Type Max 2.0 V Low level input voltage (LVCMOS interface) Switching threshold LVCMOS VT+ Schmitt trigger, positive-going threshold LVCMOS VT- Schmitt trigger, negative-going threshold LVCMOS 0.8 VIN = VDD -10 Unit 0.8 V 2.0 V 10 uA 1.4 High level input current IIH Input buffer Input buffer with pull-up 10 30 60 Low level input current IIL input buffer -10 Input buffer with pull-up VIN = VSS -60 IOZ Tri-state output leakage current VOUT = VSS or VEXT -10 IOS Output short circuit current VDD=3.6V, VO=VDD VDD =3.6V, VO=VSS 10 -30 uA -10 10 uA 55 mA 100Note3 uA -55 IDD Quiescent supply current VIN = VSS or VDD CIN Input capacitance Any Input and Bidirectional Buffers 4 pF Output capacitance Any Output Buffer 4 pF COUT NOTES: 1. All 5V-tolerant input have less than 0.2V hyterisis. 2. Type B1 means 1mA output driver cells, and Type B6/24 means 6mA/24mA output driver cells. 3. This value depends on the customer design. 4. This value exclude package parasitics. 9 S5L9274 DECODER FOR CD-MP3/CD-ROM OPERATION DESCRIPTION IO TIMING SPECIFICATION MCU Interface D1 D2 D3 D4 D5 D6 D7 D8 C1 C2 C3 C4 C5 C6 C7 C8 MCK MLT MDAT Write data Write address Register write protocol C1 C2 C3 C4 C5 C6 C7 C8 D8 D7 D6 D5 D4 D3 D2 D1 MCK MLT MDAT Read address Read data MDOUT Register read protocol BL * 16 C1 C2 C3 C4 C5 C6 C7 C8 MCK MLT MDAT Memory read command (8'h50) Read MEM data MDOUT Memory read protocol Description for the memory read protocol 1. Write Start Address to H_MEM_ADDR_HIGH (8'hf0), H_MEM_ADDR_MID (8'hf1), and _MEM_ADDR_LOW (8'hf2). 2. Write BL(Burst Length) to H_MEM_ADDR_BL (8'hf3). The BL is programmable between and 63. The default value of the H_MEM_ADDR_BL when reset is 1. 3. Send command 8'h50 (i.e. Transfer address of the H_MEM_READ). 4. Read MDOUT as many bits as the " BL*16 ". (16bits per 1 burst, each burst is MSB first.) 10 DECODER FOR CD-MP3/CD-ROM S5L9274 POWER MANAGEMENT Power Save Modes Down : Master Clock Disabled. Whole chip is in reset state and clocking is disabled. (Host Interface ?, Clocks for CD-DSP chip ?) Mode : All units suspended except hifUnit and DRAM Controller Block to refresh DRAM. M P3 Pl ay e us Pa Power Down y pla Re St op Running Sleep System Power ON Power down mode Power down mode is implemented using MLAT, MCK, and MDAT. When the MLAT is low the MDAT is goes to low, the CD-MP3 goes to "power down reset" mode. It means power ON state. When the MLAT is low and the MCK goes to LOW, the CD-MP3 the "power down mode". The default value of MLAT, MCK, and MDAT is HIGH. the system power becomes ON and the master reset comes, Micom should set the of MLAT, MCK, and MDAT to HIGH. And should reset the power down mode of -MP3 using MLAT and MDAT LOW. Finally should send the S/W reset to CD-MP3 H_SOFT_RST (8'hE0) register. Sleep mode In sleep mode, the minimal power is supplied which is needed just for DRAM refresh, host command, and etc. There is a register H_SLEEP_CR to control Sleep . To enter sleep mode write "1xxxxxxx" into the H_SLEEP_CR. To wake up from mode write "0xxxxxxx" into the H_SLEEP_CR. _SLEEP_CR 8'hdf 11 S5L9274 DECODER FOR CD-MP3/CD-ROM HOST MCU CONTROL SPACE Registers to control CD-ROM sector decoding // Read only registers (8'h20 8'h2F reserved for cdrUnit - Read) H_MIN_R 8'h24 "minute" in the header of the sector being currently decoded. H_SEC_R 8'h25 "second" in the header of the sector being currently decoded. H_FRM_R 8'h26 "frame" in the header of the sector being currently decoded. H_MODB_R 8'h27 CD-ROM Mode information in the header of the sector being currently decoded. H_FN_R 8'h28 The file number information in the sub header of the current frame. This is valid for Mode-2 format. H_CN_R 8'h29 The channel number information in the sub header of the current frame. This is valid for Mode-2 format. H_SM_R 8'h2a The sub-mode information in the sub header of the current frame. This is valid for Mode-2 format. H_CI_R 8'h2b The coding information in the sub header of the current frame. This is valid for Mode-2 format. H_ERR_R 8'h2c The Header Error flags in the sub header of the current frame. bit7 M_EMIN (Error in MIN) bit6 M_ESEC (Error in SEC) bit5 M_EFRM (Error in FRM) bit4 M_EMOD (Error in MODB) bit3 M_EFN (Error in FN) bit2 M_ECN (Error in CN) bit1 M_ESM (Error in SM) bit0 M_ECI (Error in CI) H_BLKST_R 8'h2d Indicates that unexpected Sync has been detected. bit7 Long Block 0 : Normal case. 1 : The CD-ROM decoder detects the Internal Synchronization pattern but does not detect the External Synchronization pattern. The previous frame has longer bytes of data than expect. bit6 Short Block 0 : Normal case. 1 : The CD-ROM decoder detects the External Synchronization pattern but does not detect the Internal Synchronization pattern. The previous frame has shorter bytes of data than expect. bit5 Invalid Block 0 : Normal case. 1 : The CD-ROM decoder does not detect either External or Internal Synchronization pattern when Internal or External Synchronization pattern is detected. Current frame data is invalid. bit4:0 not used // Write only registers (8'hB0 8'hBF reserved for cdrUnit - Write) H_INPIF_W 8'hB1 bit7 M_BCKS1 bit6 M_BCKS0 bit7:6 Indicate the number of BCKs per 16-bit word 00 = 16 BCKs, Data valid at every BCK 01 = 24 BCKs. Data valid for the last 16 BCKs 10 = 24 BCKs. Data valid for the first 16 BCKs 12 DECODER FOR CD-MP3/CD-ROM bit5 bit4 bit3 bit2 bit1 bit0 H_HEAD_W 8'hB2 bit7 bit6 bit5 bit4 bit3:0 S5L9274 11 = 32 BCKs. Data valid for the last 16 BCKs M_DATMF Must be set equal to '1' for the input data with MSB first M_C2PMF Must be set equal to '1' for the input C2PO with MSB first M_LRB. Must be set equal to '1' if HIGH of LRCK indicates the left channel. M_LATCH( not enable ) 1 : Input data is latched on the rising edge of BCK, 0 : Input data is latched on the falling edge of BCK. M_C2PEN 1 : C2PO data is input with other data, 0 : No C2PO data is input with other data. M_PHILIPS. When the CD-DSP data format is as PHILIPS', this bit should be a logical '1' 1: Supports PHILIPS' IIS DSP interface format. 0 : Do not supports PHILIPS' IIS DSP interface format. default value : 0x00 MODE1, MODE2-Form1, MODE2-Form2 Mode2/Mode1 1 : Mode2 0 : Mode1 Form2/Form1 1 : Form2 0 : Form1 AC. Auto correction 1 : CD-ROM decoder acts as according to the value of mode/form bits in the header/sub header 0 : CD-ROM decoder acts as according to the value of bit7:6 of this register DSCR .Descrambling Enable/Disable 1 : Descrambling Enable 0 : Descrambling Disable not used H_OPSR_W 8'hB3 H_START_M H_START_S H_START_F H_ECC_EN 0x00: Set CDROM decoding mode to IDLE mode. CDROM decoder discards all input bitstream and does no decoding. All registers containing decoded header information is not valid in this mode. 0x90: Set CDROM decoding mode to MONITORING mode. Decodes Header only. 0x91: Set CDROM decoding mode to DECODING mode. This causes S5L9274 starts to decode the following sector and store to DRAM. 8'hB4 Not Used 8'hB5 Not Used 8'hB6 Not Used 8'hB7 Control register for ECC enable/disable. bit7:1 not used bit0 H : Ecc Enable default value : 0x00 13 S5L9274 DECODER FOR CD-MP3/CD-ROM Registers to communicate with embedded DSP core // Read only registers (8'h00 8'h0F reserved for dspUnit - Read) H_OUT1_LOW 8'h01 Low byte of OUT1 register. H_OUT1_HIGH 8'h02 High byte of OUT1 register. H_OUT2_LOW 8'h03 Low byte of OUT2 register. H_OUT2_HIGH 8'h04 High byte of OUT2 register. H_OUT_XTRA 8'h05 Extra byte of OUT register. H_EMPH 8'h06 Indicate Emphasis ON/OFF and Emphasis Type. bit[7:2] : not used. bit[1] : If "1", Emphasis ON. If "0", emphasis OFF. bit[0] : Emphasis Type // Write only registers (8'h80 8'h8F reserved for dspUnit - Write) H_SSPINT 8'h80 Micom command register. Micom writes a command to this register. H_IN_LOW 8'h81 Low byte of in register H_IN_HIGH 8'h82 High byte of in register H_IN_XTRA 8'h83 Extra byte of in register Registers for configuration and status of DRAM // Read only registers (8'h10 8'h1F reserved for memUnit - Read) H_DUMP_CNT 8'h11 Total number of CD frames currently been dumped to DRAM since 0x91 was written to OPSR register. Once all frames as many as specified in the H_FRAME_NO register are dumped into DRAM, OPSR value will be changed to 90 automatically after completion of dump. At every time after 0x91 was written to OPSR and 1 frame has been dumped, the H_DUMP_CNT reset to "1". H_IB_STATE 8'h12 Input Buffer Occupancy bit0 : Empty bit1 : Low bit2 : High 14 DECODER FOR CD-MP3/CD-ROM S5L9274 // Write only registers (8'h90 8'hAF reserved for memUnit - Write) H_CD_START_H 8'h90 H_CD_START_L 8'h91 H_CD_END_H 8'h92 H_CD_END_L 8'h93 H_IB_START_H 8'h94 H_IB_START_M 8'h95 H_IB_START_L 8'h96 H_IB_END_H 8'h97 H_IB_END_M 8'h98 H_IB_END_L 8'h99 H_OBL_START_H 8'h9a H_OBL_START_M 8'h9b H_OBL_START_L 8'h9c H_OBL_END_H 8'h9d H_OBL_END_M 8'h9e H_OBL_END_L 8'h9f H_OBR_START_H 8'ha0 H_OBR_START_M 8'ha1 H_OBR_START_L 8'ha2 H_OBR_END_H 8'ha3 H_OBR_END_M 8'ha4 H_OBR_END_L 8'ha5 H_REFRESH_INTERVAL 8'ha6 DRAM refresh interval rate bit1:0 00: 624 cycles 01: 608 cycles 10: 576 cycles 11: 480 cycles H_DRAMIF_NOE 8'ha7 DRAM Interface Output Enable Control Register bit7 : DRAM Interface Outputs Enable (Active Low.) bit6 0 : don't care H_FRAME_NO 8'ha8 The frames as many as specified in this H_FRAME_NO register are dumped into DRAM after every 0x91 is written in the OPSR. OPSR value will be changed to 90 automatically after completion of dump. The maximum value allowed for the H_FRAME_NO is IBsize/1024. H_SHOCK 8'ha9 When Micom detects shock, it sets this register with the value of "xxxxxxx1". This causes to stop dump operation and deletes frames as many as specified in the H_RETURN_SECTOR register from the Input Buffer. When there's no shock, Micom sets H_SHOCK register with the value of "xxxxxxx0". H_IB_WR_OFFSET 8'haa Input Buffer is in LOW state when the condition below is met : " Input Buffer Vacancy is equal to or less than (Size of Input Buffer - the value in the H_IB_WR_OFFSET) " H_RETURN_SECTOR 8'hab When occurred shock, before detect shock, data cause to dump in dram. It set deletes frames as may as specified from the shock. 15 S5L9274 DECODER FOR CD-MP3/CD-ROM Registers to control DAC interface // Read only registers (8'h30 8'h3F reserved for difUnit - Read) // Write only register (8`hB0) H_DAC_TYPE 8'hB0 // Write only registers (8'hC0 8'hCF reserved for difUnit - Write) H_DACIF_nOE 8'hC0 To control Tri-State Output of difUnit. bit7 : If "1", DAC Interface outputs goes high impedance state. If "0", DAC Interface outputs enabled. bit6 0 : don't care Registers for configuration of clock // Read only registers (8'h40 8'h4F reserved for ckgUnit - Read) // Write only registers (8'hD0 8'hDF reserved for ckgUnit) H_PLL0_P0 8'hd0 P register for PLL0 (See setting system clock frequency) H_PLL0_M0 8'hd1 M register for PLL0 (See setting system clock frequency) H_PLL0_S0 8'hd2 S register for PLL0 (See setting system clock frequency) H_PLL1_P1 8'hd3 P register for PLL1 (See setting system clock frequency) H_PLL1_M1 8'hd4 M register for PLL1 (See setting system clock frequency) H_PLL1_S1 8'hd5 S register for PLL1 (See setting system clock frequency) H_CKG_DIV_XY 8'hd6 (See setting system clock frequency) H_CKG_CMD_0 8'hd7 (See setting system clock frequency) H_SLEEP_CR 8'hdf SLEEP control register bit7 1 : don't care bit0 : If "1", Set S5L9274 to SLEEP mode. If "0", set S5L9274 to RUNNING mode. Registers for reset control // Write only registers (8'hE0 8'hEF reserved for rstUnit - Write) H_SOFT_RST 8'hE0 Master reset by software control Registers for DRAM access and Interrupt Source Register // Read only registers (8'h50 8'h5F reserved for hifUnit - Read) H_MEM_READ 8'h50 Buffer Register for DRAM burst read H_INT_READ 8'h51 Interrupt Source Register // Write only registers (8'hF0 8'hFF reserved for hifUnit - Write) H_MEM_ADDR_HIGH 8'hf0 High byte of start address for DRAM burst read H_MEM_ADDR_MID 8'hf1 Middle byte of start address for DRAM burst read H_MEM_ADDR_LOW 8'hf2 High byte of start address for DRAM burst read H_MEM_ADDR_BL 8'hf3 Burst Length for DRAM burst read (1 63, default is 1.) 16 DECODER FOR CD-MP3/CD-ROM S5L9274 SETTING SYSTEM CLOCK FREQUENCY NOTE : ACLK : audio clock of BI9274X internal. CLK : system clock of BI9274X internal. MODE 1 - Dual PLL Mode A ( H_CKG_CMD0[2:1] = 01 or 00 , PLL_BYPASS = LOW) Host Control aclk = 12.288MHz clk = 38.7MHz aclk = 16.9344MHz clk =38.7MHz aclk = 18.432MHz clk = 38.7MHz H_PLL0_P0 19 (D) 19 (D) 19 (D) H_PLL0_M0 40 (D) 40 (D) 40 (D) H_PLL0_S0 0 (D) 0 (D) 0 (D) H_PLL0_P1 5 (D) xxxx xxxx (B) 5 (D) H_PLL0_M1 12 (D) xxxx xxxx (B) 22 (D) H_PLL0_S1 0 (D) xxxx xxxx (B) 0 (D) H_CKG_DIV_XY xx11 xx00 (B) xxxx xxxx (B) xx11 xx00 (B) H_CKG_CMD0 0000 0010 (B) 0000 0000 (B) 0000 0010 (B) CLK (I) PIN SETTING CONNECTED TO XOUT ACLK_EXT (I) TIED TO GND XI 16.9344MHz X-tal XO 16.9344MHz X-tal MODE 2 - Dual PLL Mode B ( H_CKG_CMD0[2:1] = 01 or 00 , PLL_BYPASS = LOW) Host Control aclk = 12.2919MHz clk = 32.33MHz aclk = 16.9344MHz clk = 32.33MHz aclk = 18.4378MHz clk = 32.33MHz H_PLL0_P0 20 (D) 20 (D) 20 (D) H_PLL0_M0 34 (D) 34 (D) 34 (D) H_PLL0_S0 0 (D) 0 (D) 0 (D) H_PLL0_P1 10 (D) xxxx xxxx (B) 14 (D) H_PLL0_M1 65 (D) xxxx xxxx (B) 65 (D) H_PLL0_S1 3 (D) xxxx xxxx (B) 2 (D) H_CKG_DIV_XY xx01 xx00 (B) xxxx xxxx (B) xx01 xx00 (B) H_CKG_CMD0 0000 0010 (B) 0000 0000 (B) 0000 0010 (B) CLK (I) PIN SETTING ACLK_EXT (I) CONNECTED TO XOUT TIED TO GND XI 16.9344MHz X-tal XO 16.9344MHz X-tal 17 S5L9274 DECODER FOR CD-MP3/CD-ROM MODE 3 - Single PLL Mode ( H_CKG_CMD0[2:1] = 10 or 00 , PLL_BYPASS = LOW) Host Control aclk = 12.3159MHz clk = 36.9MHz aclk = 16.9344MHz clk =38.7MHz aclk = 18.407MHz clk = 36.8MHz H_PLL0_P0 20 (D) 19 (D) 21 (D) H_PLL0_M0 40 (D) 40 (D) 42 (D) H_PLL0_S0 0 (D) 0 (D) 0 (D) H_PLL0_P1 xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) H_PLL0_M1 xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) H_PLL0_S1 xxxx xxxx (B) xxxx xxxx (B) xxxx xxxx (B) H_CKG_DIV_XY xx10 xxxx (B) xxxx xxxx (B) xx01 xxxx (B) H_CKG_CMD0 0000 0100 (B) 0000 0000 (B) 0000 0100 (B) CLK (I) PIN SETTING CONNECTED TO XOUT ACLK_EXT (I) TIED TO GND XI 16.9344MHz X-tal XO 16.9344MHz X-tal MODE 4 - PLL BYPASS Mode (PLL_BYPASS = HIGH) aclk = External Source (ACLK_EXT) clk = External Source (CLK) Host Control H_PLL0_P0 xxxx xxxx (B) H_PLL0_M0 xxxx xxxx (B) H_PLL0_S0 xxxx xxxx (B) H_PLL0_P1 xxxx xxxx (B) H_PLL0_M1 xxxx xxxx (B) H_PLL0_S1 xxxx xxxx (B) H_CKG_DIV_XY xxxx xxxx (B) H_CKG_CMD0 xxxx xxxx (B) CLK (I) PIN SETTING 18 ACLK_EXT (I) System Clock Frequency Audio Clock Frequency (384Fs) XI TIED TO GND XO OPEN DECODER FOR CD-MP3/CD-ROM S5L9274 MICOM PROGRAMMING GUIDELINE Transferring Input Bitstream to S5L9274 Micom is allowed to initiate the transfer when the Input Buffer is in LOW state which is by the "Input Buffer State" Interrupt (See section skip function) from CD-MP3 IC. Burst Transfer with the number of sectors being transferred. Verify the Input Buffer is in LOW state. The register H_IB_STATE tells Input Buffer (Empty, Low, or High). When there is any change in the H_IB_STATE, "Input Buffer " Interrupt arises, and External MCU can read the H_IB_STATE to know the Input State. When Input Buffer is in lower than the "Input Buffer Low Threshold" we say is in LOW state. Input Buffer Low Threshold is determined by the value of the register _IB_WR_OFFSET. It has the following relationship. Low Threshold = (Input Buffer Size in number of words) - (H_IB_WR_OFFSET)*1024 Micom decides the start sector address from which the CD-ROM sectors are transferred S5L9274. Write number of sectors being transferred into H_FRAME_NO register. Micom initiate to transfer CD-ROM sectors from CDP subsystem to S5L9274 starting the address (MSF) which is several sectors ahead the start sector address. Micom gets sector address information (MSF) from CDP subsystem while CDP transfers CD-ROM sectors to S5L9274. Micom checks continuously if the MSF received from CDP subsystem is reached at the MSF from which Micom wants to put the corresponding sector in S5L9274. If the MSF received from CDP subsystem is reached at (the start MSF - 1), Micom "0x91" to H_OPSR_W in S5L9274 to allow for S5L9274 to start decode sectors when sector boundary is reached. When "Dump-End" interrupt encountered during sector transfer, read the H_DUMP_CNT and check if the content of the H_DUMP_CNT is equal to the content of _FRAME_NO. If they are equal, it indicates all sectors have been transferred successfully if they are not, it indicates that Input Buffer High condition were met in the middle of transfer and the remaining transfer has been discarded after that condition. If that n has occurred, Micom should transfer again from the sector which was cancelled. new start sector address can be calculated with the previous start sector address and content of the H_DUMP_CNT register. * S5L9274 set the "Dump-End" interrupt when the content of the H_DUMP_CNT is equal to content of H_FRAME_NO and also when Input Buffer High condition were met during transfer. 19 S5L9274 DECODER FOR CD-MP3/CD-ROM Burst Transfer without the number of sectors being transferred. Verify the Input Buffer is in LOW state. The register H_IB_STATE tells Input Buffer (Empty, Low, or High). When there is any change in the H_IB_STATE, "Input Buffer " Interrupt arises, and External MCU can read the H_IB_STATE to know the Input State. When Input Buffer is in lower than the "Input Buffer Low Threshold" we say is in LOW state. Input Buffer Low Threshold is determined by the value of the register _IB_WR_OFFSET. It has the following relationship. Low Threshold = (Input Buffer Size in number of words) - (H_IB_WR_OFFSET)*1024 Micom decides the start sector address from which the CD-ROM sectors are transferred S5L9274. Write 0 to the H_FRAME_NO. (The default value after reset this is 0 therefore, this would not be necessary.) Micom initiate to transfer CD-ROM sectors from CDP subsystem to S5L9274 starting the address (MSF) which is several sectors ahead the start sector address. Micom gets sector address information (MSF) from CDP subsystem while CDP transfers CD-ROM sectors to S5L9274. Micom checks continuously if the MSF received from CDP subsystem is reached at the MSF from which Micom wants to put the corresponding sector in S5L9274. If the MSF received from CDP subsystem is reached at (the start MSF - 1), Micom "0x91" to H_OPSR_W in S5L9274 to allow for S5L9274 to start decode sectors when sector boundary is reached. When "Dump-End" interrupt encountered during sector transfer, it indicates the input is in BUFFER-HIGH state and any more transfer is discarded to avoid input buffer . Read the H_DUMP_CNT register which represents the number of sectors that have successfully transferred. Micom calculate new start sector address which is the one for the next to the last which has been transferred before. Repeat the whole process. 20 DECODER FOR CD-MP3/CD-ROM S5L9274 CDFS Table Read BI9274X decodes File Allocation Table of CD-ROM and stores it to DRAM. Micom can DRAM to read the CDFS Table using register read protocol. (See Section MCU interface.) Setting DRAM Refresh Rate Micom can change DRAM refresh rate by change a code in the H_REFRESH_INTERVAL as following : H_REFRESH_INTERVAL(8'ha2) VALUE Maximum Refresh Interval 8'bxxxxxx00 624 cycles 8'bxxxxxx01 608 cycles 8'bxxxxxx10 576 cycles 8'bxxxxxx11 480 cycles Configuration of DRAM Memory Map When S5L9274 is reset the DRAM is configured to the default memory map as shown . H_CD_START 0x00000 CD-ROM Decoder H_CD_END 0x00DB6 Working Buffer Not used H_IB_START 0x01000 Input Buffer H_IB_END 0x19FFF H_OBL_START 0x1A000 Output Buffer L_CH H_OBL_END 0x280FF H_OBR_START 0x28100 Output Buffer R_CH H_OBR_END 0x361FF 0x36200 Reserved 0x3FFFF 21 S5L9274 DECODER FOR CD-MP3/CD-ROM REGISTER ADDRESS (HEX) ADDRESS (DEC) SIZE H_CD_START 0x00000 0 Size = 3511 H_CD_END 0x00DB6 3510 0x00DB7 3511 585 words 0x00FFF 4095 Not Used H_IB_START 0x01000 4096 IB_Size = 100K H_IB_END 0x19FFF 106495 H_OBL_START 0x1A000 106496 H_OBL_END 0x280FF 164095 H_OBR_START 0x28100 164096 H_OBR_END 0x361FF 221695 0x36200 221696 40448 Words 0x3FFFF 262143 Reserved OBL_Size = 57600 OBR Size = 57600 A storage for CDFS Table which is decoded by S5L9274 is needed for Micom to access. CDFS Table also stored in OBR(Output Buffer Right Channel) and OBL(Output Buffer Channel). S5L9274 provides memory map switching mechanism which enables of the OBR(Output Buffer Right Channel) Map between CDFS decoding and decoding modes. In CDFS decoding mode OBR and OBL are allocated outside of location of them in MP3 decoding mode to keep the CDFS table does not overlap the audio output buffer. Micom can access CDFS Table any time if necessary. Memory Map for CDFS Decoding H_CD_START 0x00000 H_CD_END H_IB_START Memory Map for MP3 Decoding CD_ROM Decoder H_CD_START 0x00000 CD-ROM Decoder Working Buffer H_CD_END 0x01000 Working Buffer 0x01000 H_IB_START Input Buffer H_IB_END Input Buffer 0x19FFF H_IB_END 0x19FFF 0x1A000 H_OBL_START 0x1A000 Output Buffer L_CH Reserved H_OBL_END 0x280FF H_OBR_START 0x28100 0x361FF H_OBR_START 0x36200 L_CH Output Buffer H_OBR_END R_CH H_OBL_START Output Buffer H_OBL_END 0x3FFFF H_OBR_END 0x361FF 0x36200 Reserved L_CH 0x3FFFF 22 Output Buffer DECODER FOR CD-MP3/CD-ROM S5L9274 Data Structure of CDFS Table in DRAM Structure of CDFS Table divided into four areas : The Introduction Table Area, Table Area, File Table Area and Identifier Table Area. According to Figure , is a typical configuration of DRAM, Output Buffer R-CH and Output Buffer L-CH are to store all CDFS Tables when S5L9274 is in the CDFS decoding mode. The Area, Directory Table Area and File Table Area are located in the Output R-CH. The Identifier Table Area is located in the Output Buffer L-CH. H_OBR_START 0x36200 Introduction table Directory table File table H_OBR_END 0x36FFF H_OBL_START 0x37000 Identifier table Output Buffer R_CH Output Buffer L_CH H_OBL_END 0x3FFFF Introduction Table Table consists of 4 words (1 word = 16bits). This Table is located in the top the Output Buffer R-CH. Address Contents (16 bits) 36200 Total number of directories in a CD 36201 Total number of MP3 files in a CD 36202 Total number of directories which contains any MP3 file in a CD 36203 The directory number which contains the 1'st MP3 file in the whole directory path. The directory number is assigned for each directory in the order of sequence in the file system structure. 23 S5L9274 DECODER FOR CD-MP3/CD-ROM Directory Table Directory Table follows the Introduction Table and comprises of consecutive directory records. There are as many directory records as the total number of directories in a table. Each directory record consists of 6 words as following. Address 36204+6i Contents (16 bits) The 1'st MP3 file number in this directory. (if there is no MP3 files in this directory, this represents the 1'st MP3 file number in next directory) 36205+6i The total number of MP3 files in this directory (Zero if there is no MP3 files in this directory.) 36206+6i Directory identifier length 36207+6i Parent directory number 36208+6i Sub directory number 36209+6i Next directory number i : 0 (total number of directories-1) directories in a CD are given directory number which is a series of number from 1 to number of the total directory count. Directories which has no MP3 files also given number and included in the directory table. Therefore root directory is always directory number 1. An explanation is given below about the relationship between directory, sub directory and next directory with an example : /2 /1 /4 /5 /8 /9 /3 /6 /A /C /D /7 /B directory number 1 2 3 4 5 6 7 8 9 A B C D parent directory 1 1 1 2 2 3 3 5 5 6 6 A A sub directory 1 4 6 4 8 A 7 8 9 C B C D next directory 1 3 2 5 4 7 6 9 8 B A D C 24 DECODER FOR CD-MP3/CD-ROM S5L9274 File Table File Table follows the Directory Table and comprises of consecutive file records. In the table, there are as many file records as the total number of MP3 file. Each file record of 6 words as following. Address Contents 36204 + Nd*6 +6j 36204 + Nd*6 +6j +1 M S 0x00 F 36204 + Nd*6 +6j +2 L8 L7 L6 L5 36204 + Nd*6 +6j +3 L4 L3 L2 L1 36204 + Nd*6 +6j +4 MP3 file identifier length 36204 + Nd*6 +6j +5 MP3 file type Nd : total number of directories j: 0 (Nf-1) , Nf = total number of MP3 files There is no file record for a non-MP3 file. M, S, and F are the values indicating 1 sector before to the actual sector address begining of a file. A file length is described as 8 hex digits (L8 L1). The length represented is FFFFFFFF. The value of M, S, and F which are all 0xAA or 0xBB indicates End of File Table data. Identifier Table Table is stored in the Output Buffer CH-L. Because the maximum length of or file identifier is 128 bytes both of the identifiers occupy 64(40h) words in . The directory identifiers comes first and file identifiers follow the directory . The first directory identifier occupies address 37000h 3703Fh in DRAM. The addresses of each directory identifier (=X) are calulated as following : X = 37000h + i * 40h , i : 0 (Nd - 1) The start addresses of each file identifiers (=Y) are calulated as following : Y = 37000h + (nd * 40h) + j * 40h , j = 0 (Nf - 1) Boot Process Programming 1. Power on CD-MP3 IC #initial #25ns(min) #25ns(min) #25ns(min) #25ns(min) i_MLT=i_MDAT=i_MCK=HIGH i_MLT <= LOW i_MDAT <= LOW i_MDAT <= HIGH i_MLT <= HIGH When the system is powered-on and the "power-on reset" comes, Micom should set the of MLT, MCK, and MDAT to 1'b1. When the MLT is low and the MDAT goes to , the CD-MP3 goes to "power-on" mode. After power-on at initial, the S/W reset is . The power-on process shown above is the very initial process required when the system powered on. After that you can switch between power-on and power-off mode using _MCK signal. 25 S5L9274 #initial #25ns(min) #25ns(min) #25ns(min) #25ns(min) DECODER FOR CD-MP3/CD-ROM i_MLT=i_MDAT=i_MCK=HIGH i_MLT <= LOW i_MCK <= LOW i_MCK <= HIGH i_MLT <= HIGH At every supply of MCK pulse (active LOW) the mode is toggled between power-on and -off. 2. S/W Reset Software Reset to CD-MP3 by writing to H_SOFT_RST(8'hE0) with 8'bxxxxxx01. After ? system cycles Software Reset automatically cleared. 3. Configuration of ckgUnit (Refer to Product Specification Chapter ? -Setting System Clock Frequency) To configure ckgUnit to Mode1 44.1kHz, H_PLL0_P0 H_PLL0_M0 H_PLL0_S0 H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD_0 (8'hD0) (8'hD1) (8'hD2) (8'hD3) (8'hD4) (8'hD5) (8'hD6) (8'hD7) * 8d'19 * 8d'40 * 8d'0 * don't care * don't care * don't care * don't care * 8d'0 4. Set DAC Type H_DAC_TYPE (8'hB0) *8'h91 for DAC in 9288 5. Set CDP Type H_INPIF_W H_HEAD_W H_ECC_EN (8'hB1) (8'hB2) (8'hB7) * 8'h72 // for SAMSUNG CD-DSP chip * 8'h18 // for MODE1 FORM1 * 8'bxxxxxxx1 // Enable ecc 6. Enable DRAM Interface Output Drivers H_DRAMIF_NOE (8'hA7) * 8'b0xxxxxxx 7. Enable DAC Interface Output Drivers H_DACIF_nOE (8'hC0) * 8'b0xxxxxxx 8. Set DRAM Refresh Interval H_REFRESH_INTERVAL (8'hA6) * 8'bxxxxxx00 Can select one of the four preset refresh interval value. 26 DECODER FOR CD-MP3/CD-ROM S5L9274 CDFS Decode Process Programming 1. Boot Process 2. Set Memory Map Address for File Table (Use default memory map for Input Buffer, and set map for output buffers as following :) H_OBL_START_L H_OBL_START_M H_OBL_START_H (8'h9C) (8'h9B) (8'h9A) *8'h00 *8'h70 *8'hX3 H_OBL_END_L H_OBL_END_M H_OBL_END_H (8'h9F) (8'h9E) (8'h9D) *8'hFF *8'hFF *8'hX3 H_OBR_START_L H_OBR_START_M H_OBR_START_H (8'hA2) (8'hA1) (8'hA0) *8'h00 *8'h62 *8'hx3 H_OBR_END_L H_OBR_END_M H_OBR_END_H (8'hA5) (8'hA4) (8'hA3) *8'hff *8'hff *8'hf3 We must note that upper 4 bits of H_OBR_END_H should be 1111 to indicate end of map transmission. 3. Wait for Interrupt When interrupted read H_INT_READ register to identify interrupt type. H_INT_READ (8'h51) * 8'bxxx010xx that indicates remap done successfully. 4. Check CD-ROM format and if it is mode2-form2 send a command "8'h0D" . H_SSPINT (8'h80 ) * 8'h0D Mode2Form2 S5L9274 regards files with extension of ".mp2" or ".mp3" as MP3 audio files by default and generates File System Table which includes information of files with those file extensions only. But files with the extension of ".mpg" may also be regarded as MP3 audio files by sending a command "8'h0F". H_SSPINT 5. (8'h80 ) * 8'h0F FATmpgOK Send a Command DECODE_CDFS. H_SSPINT (8'h80 ) * 8'h02 is DECODE_CDFS This causes interrupting ssp1611 for ssp1611 to know CD-ROM sectors with CDFS Table will be put into the input buffer. 6. Transfer CD-ROM sectors to S5L9274 in the way described in Section transferring input bit stream. 7. During the sector transfer in step 5, check if "Sending MSF" Interrupt has been received. H_INT_READ (8'h51) *8'bxxx001xx : Sending MSF Interrupt (See section skip function) After receiving interrupt, Micom should get next sector address by reading the registers below : 27 S5L9274 H_OUT1_LOW H_OUT1_HIGH H_OUT2_LOW DECODER FOR CD-MP3/CD-ROM (8'h01) (8'h02) (8'h03) *S *M *F If M, S and F read are all AAh or BBh, it indicates CDFS decoding has been completed. If they are all AAh it indicates that this CD is not in a juliet format. If they are all BBh it indicates that CD is in juliet format CD. If M, S and F are not all AAh or BBh go to step 8. 8. Transfer CD-ROM sectors to S5L9274 in the way described in Section transferring input bit stream with the start sector address MSF. 9. Repeat 6,7,8. 10. During step 9, When there is an error in the sector received i.g. if the file system is not in accordance with ISO9660, S5L9274 asks the sector again to the Micom. if this happens repeatedly, this means that there is a non-recoverable error in the . In this case micom sends FATnextDIR command for S5L9274 to give up decoding the file system information for the current search path and it's sub-tree. Receiving this command, S5L9274 asks Micom new sector for the next search path of the file system. H_SSPINT (8'h80 ) * 8'h0E FATnextDIR When CDFS decoding is completed successfully, decoded CDFS tables are stored in such a way described in Section. Data Structure of CDFS Table in DRAM . Micom can read the tables any time. In the Identifier Table, 64 words are allocated to directory or file identifiers. Because 2 bytes are required to represent 1 character Joliet format, maximum 64 characters can be stored in each 64 words of an identifier. in DOS format, because 1 character is represented by 1 byte code, maximum 128 can be stored in each 64 words of identifier. Micom should know if a CD is Joliet format or not to recognize the identifier correctly. 28 DECODER FOR CD-MP3/CD-ROM S5L9274 TAG DECODE PROCESS ID3 TAG Version 1.xx 1. Boot Process 2. Remap : Configure Memory Map 3. Transfer the last sector of an MP3 file to S5L9274. 4. Write a sector size to registers IN1. 5. Issue the command DECODE_TAG. 6. Waits interrupt 8'bxxx001xx H_INT_READ (8'h51) *8'bxxx001xx : DECODE_TAG Acknowledge 7. Read OUT1. If the content of OUT1 is 0xDD01, it indicates there is no TAG in the sector. If the TAG information is found, the content of OUT1 is DRAM of the start of TAG information. 8. If TAG is found, Micom reads DRAM to decode the TAG information. ID3 TAG Version 2.xx 1. Boot Process 2. Remap : Configure Memory Map 3. Transfer the first sector of an MP3 file to S5L9274. 4. TAG Information follows ID3 characters therefore Micom can read 3 bytes of the first to decide if there is TAG information in the MP3 file. 5. Micom reads DRAM to decode TAG information. MP3 decode process 1. Boot Process 2. Remap : set memory map address for output buffer ( returns memory map to MP3 mode from CDFS decode mode by writing back the default value for output buffer channel. ) H_OBR_START_L H_OBR_START_M H_OBR_START_H (8'hA2) (8'hA1) (8'hA0) *8'h00 *8'h81 *8'hx2 H_OBR_END_L H_OBR_END_M H_OBR_END_H (8'hA5) (8'hA4) (8'hA3) *8'hff *8'h61 *8'hf3 We must note that upper 4 bits of H_OBR_END_H should be 1111 to indicate end of map transmition. 3. Wait for Interrupt H_INT_READ (8'h51) * 8'bxxx010xx that indicates remap done successfully. wait for interrupt from ssp1611 that indicates CD-MP3 chip has successfully the remap sequence. When Micom reads H_INT_READ register the interrupt be cleared automatically. 29 S5L9274 DECODER FOR CD-MP3/CD-ROM 4. Send Command DECODE_MP3. H_SSPINT (8'h80 ) * 8'h03 is DECODE_MP3 5. Micom reads CDFS Table and select a music to be play. 6. Micom set Total_Sector_Number as follows. Total_Sector_Number ia a value with 20bit range. H_IN_XTRA (8'h83) H_IN_HIGH H_IN_LOW (8'h82) (8'h81) : XYZW XXXX Y : if FF(Fast Forward) state when going to next song, set Y=1 Z : if FB(Fast Backrward) state when going to next song, set Z=1 W: if CD-ROM format is Form2, W=1 XXXX: Total_Sector_Number[19:16] : Total_Sector_Number[15:8] : Total_Sector_Number[7:0] 7. Transfer CD-ROM sectors to S5L9274 in the way described in Section transferring input bitstream. 8. S5L9274 starts decoding of input bitstream. When audio sampling frequency information the bitstream header S5L9274 writes it to the register H_OUT1_LOW and interrupt . And then S5L9274 stops it's decoding. S5L9274 will resume it's decoding after configures audio clock frequency. When interrupted from S5L9274 for audio frequency information transfer, Micom reads the sampling frequency information in H_OUT1_LOW (8'h01) and set audio clock in S5L9274. H_INT_READ (8'h51) H_OUT1_LOW (8'h01) * 8'bxxx011xx that indicates sending audio sampling frequency code * frequency code Sampling Frequency Information 000 : 44.1 kHz 001 : 48 kHz 010 : 32 kHz 011 : Not Used 100 : 22.05 kHz 101 : 24 kHz 110 : 16 kHz After setting audio clock frequency Micom send a command (0x23) to S5L9274 to indicate clock frequency setting completed successfully. H_SSPINT (8'h80) * 8'h23 is completion of frequency setting 9. When both of input buffer and output buffer are empty it means that end-of-song S5L9274 is in IDLE state. Micom can see when input buffer becomes empty S5L9274 interrupts Micom when input buffer state has been changed. Micom can a certain time until output buffer becomes empty when Micom can conclude that of-song reached. Therefore Micom should keep in mind the last sector has been sent S5L9274 and from that time it checks input buffer state at each interrupts. 30 DECODER FOR CD-MP3/CD-ROM S5L9274 Skip Function 1. Micom controls servo system to stop feeding CD data to S5L9274. 2. Micom send a command "Pause". (This is for the purpose of audio fade-out.) H_SSPINT (8'h80) * 8'h07 (Pause) 3. Follow the sequence from step2 (Remap) of the "MP3 decode process" in section 8.8. Fast Forward Function 1. Micom writes "number of frame to be skipped" to H_IN_LOW , and "number of frames be decoded" to H_IN_HIGH. 2. Micom send a command FAST FORWARD. 3. Micom send a command REPLAY to return to normal play. Fast Backward Function At starting Fast Backward, Input Buffer could contain less than 10 sec of input bitstream. Input Buffer should be empty to reverse without delay caused by this input bitstream. 1. Micom send a command "Input Buffer Clear" H_SSPINT (8'h80 ) * 8'h06 is Input Buffer Clear 2. Micom determine Skip_Sector_Number and Dump_Sector_Number applied to 8-10.7. Micom writes ratio of Skip_Sector_Number and Dump_Sector_Number to H_IN_LOW ( that is Skip_Sector_Number/Dump_Sector_Number) and writes 0 to H_IN_HIGH. 3. Micom send a command "FAST BACKWARD". H_SSPINT (8'h80 ) 4. Micom waits for interrupt * 8'h0A is FAST BACKWARD. H_INT_READ (8'h51) * 8'bxxx110xx that indicates input buffer cleared. After receiving interrupt, Micom should get Rewinded_Sector_Number by reading the shown below : H_OUT1_LOW (8'h01) * H_OUT1_HIGH (8'h02) * 5. Micom convert Rewind_Sector_Num to Rewind_MSF 6. Micom update Dump_Start_MSF by subtracting Dump_Curr_MSF with Rewind_MSF 7. Micom start to dump at Dump_Start_MSF repeating dump and skip. dump as much as Dump_Sector_Number and skip as much as Skip_Sector_Number. 8. Micom send a command REPLAY to return to normal play. 31 S5L9274 DECODER FOR CD-MP3/CD-ROM Get Decoding Time for Display wait interrupt continuously during decoding process for time display. H_INT_READ (8'h51) *8'bxxx111xx that indicates S5L9274 send Current_Decoding_Sec S5L9274 send this interrupt about twice or three times per second. The exact period is determined by sampling frequency. but Micom doesn't need to know the period becase send Current_Decoding_Sec (in second) when interrupt. Micom only have to Current_Decoding_Sec. After receiving interrupt, Micom should get Current_Decoding_Sec (hexa value) by reading the registers shown below : H_OUT1_LOW H_OUT1_HIGH (8'h01) (8'h02) * * Micom would better display Current_Decoding_Sec in the format of minute: second than second. Set Current Decoding Time with Current Sector Number During Fast Forward or Fast Backward, S5L9274 cannot send correct decoding time of skipped frames. But Micom can update decoding time correctly by sending number currently being decoded. 1. Micom writes lower byte of "sector number currently decoded" to H_IN_LOW and higher byte of "sector number currently decoded" to H_IN_HIGH. 2. Micom send a command "Set Current Decoding Time with Sector Number". H_SSPINT (8'h80 ) * 8'h11 is "Set Current Decoding Time with Sector Number". Form that time, S5L9274 send new Current_Decoding_Sec converted from "the sector currently decoded" set by Micom. Compute Total Time Total_Sector_Number was set in the way described in 8-8.7, Micom can call "Compute Time" to get total play time. 1. Micom send command "Compute Total Time" whenever finishing 8-11 once. H_SSPINT (8'h80 ) 2. Micom wait interrupt. H_INT_READ (8'h51) * 8'h10 (Compute Total Time) *8'bxxx110xx that indicates S5L9274 send total time in second After receiving interrupt, Micom should get Total_Sec (hexa value) by reading the shown below : H_OUT1_LOW (8'h01) H_OUT1_HIGH (8'h02) * * Micom would better display Total_Sec in the format of minute: second than second. 32 DECODER FOR CD-MP3/CD-ROM S5L9274 Interrupt handling There is one signal line for interrupt from BI9274X to Micom (MINT). When Micom is by BI9274X, it should read the interrupt source register in CD-MP3 (H_INT_READ 8'h51) which indicates the interrupt type to idendify which interrupt service should be done. H_INT_READ b7 b6 b5 b4 b3 b2 b1 b0 b7 : Not Used. (always LOW.) b6-b5 : cdrUnit Interrupt Source b4-b2 : dspUnit Interrupt Source b1-b0 : memUnit Interrupt Source cdrUnit Interrupt Source Description : 01 : Header Error When S5L9274 detects error in header of a CD-ROM sector this interrupt is set. 10 : Sector Address Decoded Out of Range Discard this in current version of S5L9274 11 : reserved for future use. dspUnit Interrupt Source Description : 001 : Sending M.F.S This interrupt bits are set when S5L9274 expects to get CD-ROM sectors which is in address from the current sector address during the CDFS decoding. (End Of CDFS Decoding is indicated by M.F.S = all zero.) 010 : End Of REMAP 011 : Sending Audio Sampling Frequency Code 100 : reserved 101 : Sending Output Buffer Left Channel Empty Signal 110 : End of Input Buffer Clear / Sending Total Time in second 111 : Sending Decoding Time for Display memUnit Interrupt Source Description : 01 : Dump-End 10 : Input Buffer State 11 : reserved for future use. 33 S5L9274 DECODER FOR CD-MP3/CD-ROM Command Set Description Micom can send a command to S5L9274 by writing a command ID to H_SSPINT register. _SSPINT (8'h80) b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 : Host Command ID Command IDs --------------------------0x01 : DECODE_TAG 0x02 : DECODE_CDFS 0x03 : DECODE_MP3 0x04 : End of Input, indicates last data of MP3 bitstream for current music has been supplied. 0x05 : An Interrupt indicating that Micom completed audio clock frequency setting in of audio sampling frequency information which is sent to Micom by ssp1611 should wait this interrupt to continue decoding after audio frequency has been changed. In addition to this interrupt, ssp1611 also wait until the output buffer becomes empty to ensure audio DAC correctly at the boundary of different sampling frequency boundary. 0x06 : Clear Input Buffer (This command shoud be issued before Fast Backward .) 0x07 : Pause (ssp1611 stop reading by setting Flag for difUnit interrupt service routine not to read OBrChannel and send MUTE data to difUnit. When Paused ssp1611 need to fade out the audio.) 0x08 : Replay (ssp1611 clears the Flag for difUnit interrupt service routine resume to read the OBrChannel. ssp1611 need to fade in the audio.) 0x09 : Fast Forward 0x0A : Fast Backward 0x0B : Soft Mute (ssp1611 keeps enabling OBrChannel read but discard the data. Send MUTE data to difUnit. Needs to fade out. ) 0x0C : Soft Mute Off 0x0D : Mode2Form2 0x0E : FATnextDir 0x0F : FATmpgOK 0x10 : Compute Total Time 0x11 : Set current decoding time with sector number 34 DECODER FOR CD-MP3/CD-ROM S5L9274 DRAM Interface 4Mbit(1M x 4 bit) DRAM 3.3V, 70ns, 1K refresh KM44V1000D (FP) KM44V1004D (EDO) S5L9274 DA0 - 9 A0 - 9 DDAT0 - 3 DQ0 - 3 RASB RAS CASB CAS OEB OE WEB W Figure 3. Interface with 1Mx4bit DRAM 16Mbit(4M x 4 bit) DRAM 3.3V, 60ns, 2K refresh KM44V4100C (FP) KM44V4104C (EDO) S5L9274 GND DA0 - 9 DDAT0 - 3 A10 A0 - 9 DQ0 - 3 RASB RAS CASB CAS OEB OE WEB W Figure 4. Interface with 4Mx4bit DRAM 35 S5L9274 DECODER FOR CD-MP3/CD-ROM 16Mbit(2M x 8 bit) DRAM 3.3V, 70ns, 2K refresh KM48V2100C (FP) KM48V2104C (EDO) S5L9274 GND DA0 - 9 A10 A0 - 9 DQ4 100K Pull Up DQ0 - 3 DQ5 100K Pull Up RASB RAS DQ6 100K Pull Up CASB CAS DQ7 100K Pull Up DDAT0 - 3 OEB OE WEB W Figure 5. Interface with 2Mx8bit DRAM 16Mbit(1M x 16 bit) DRAM 3.3V, 70ns, 1K refresh KM416V1200C S5L9274 DA0 - 9 DDAT0 - 3 A0 - 9 DQ4 100K Pull Up DQ15 100K Pull Up DQ0 - 3 RASB RAS CASB LCAS UCAS OEB OE WEB W Figure 6. Interface with 1Mx16bit DRAM 36