S5N8950 G.dmt ADSL Transceiver for CO and CPE Preliminary Information Rev.1.2 Nov. 2000. SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY Copyright ¨ Ï2000 Samsung Electronics, Inc. All Rights Reserved. S5N8950 G.dmt ADSL Transceiver for CO and CPE 1 General Description The S5N8950 is an optimized chip of ADSL transceiver supporting G.992.1, G.992.2 and T1.413, and provides a total chipset solution with AFE chip (S5N8951) for both CO and CPE applications. The S5N8950 consists of the ATM framer, DMT modem, and DSP core. It supports various interfaces of UTOPIA level 2 for ATM data and serial interface for Non-ATM data, and host controller compatible with Motorola and Intel. It is fully compatible with G.Lite and G.dmt standards to satisfy interoperability with compatible other chipsets. For CO/CPE application, evaluation tool kit shall be provided. S5N8950 Telephone Line ATM or STM DI DMT AI Host DSP RAM PLL S5N8951 Hybrid Figure 1: ADSL Transceiver configuration for S5N8950. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 2 Main Features l Power and performance optimized single port DMT. l Supports ITU-T G.992.1 (G.dmt) , G.992.2 (G.Lite) and T1.413 standards. l STM serial interface and ATM UTOPIA level 1 and level 2 interface. l Supports both the FDM-based and EC-based DMT line coding. l Analog and digital PLL modes. l Adaptive frequency and time domain equalizing. l Provides over 10 Mbps downstream data rate and over 640 Kbps upstream data rate l Flexible host interface for Motorola and Intel Controller l Reed-Solomon Forward Error Correction with Interleaving. l 3-D trellis coding and Viterbi algorithm. l Supports all of the framing modes. l Supports Rate Adaptive Mode. l 12-Bit ADC and DAC with Over-sampling l Downloadable coefficients of rate-conversion filter banks. l Low power consumption ( less than 0.5 Watt ). l Power management l Self-diagnostics l 0.18 um 1.8 V CMOS technology. l 3.3 V external interface. l Operation Temperature : -40 C to 85 C l Low Cost & Compact Package (160 QFP) CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 3 External Pin Description S5N8950 ATM interface U_TX_ADDR[4:0] U_TX_DATA[7:0] U_TX_ENB U_TX_SOC U_TX_CLK U_TX_CLAV U_RX_ADDR[4:0] U_RX_DATA[7:0] U_RX_ENB U_RX_SOC U_RX_CLK U_RX_CLAV ⇒ ⇒ → → → ← ⇒ ⇐ → ← → ← STM interface S1_TX_DAV S1_TX_CLK S1_TX_DATA S1_RX_DAV S1_RX_CLK S1_RX_DATA S2_TX_DAV S2_TX_CLK S2_TX_DATA S2_RX_DAV S2_RX_CLK S2_RX_DATA ← ← → ← ← ← ← ← → ← ← ← TeakLite interface T_MS T_CLK T_DI T_DO T_INTP → → → ← ← UART interface UA_TX_DATA UA_RX_DATA ← → ⇐ ← ← ⇒ → → ← ← ← → → → ← → → → AFE interface A_AD_DATA[6:0] A_AD_REF_CLK A_AD_AUX_CLK A_DA_DATA[6:0] A_DA_REF_CLK A_DA_AUX_CLK A_SDI A_AND A_BUSY A_SCLK A_SDO A_SEN A_PME A_TX_PWR A_RX_PWR A_RSTN ← ⇒ ⇐ ← ← ↔ ← ← → → Board/PLL interface B_RSTN B_GP_OUT[1:0] B_BMODE[1:0] B_TMODE B_NMODE B_NTR B_EXT_CLK P_XTAL_IN P_XTAL_OUT P_PLL_FILTER ← ⇒ ⇔ ← ← ← → → → Host interface H_SEL H_ADDR[9:0] H_DATA[7:0] H_CSN H_RDN H_WRN H_READY H_INT H_WAKEUP Figure 2: Pin diagram CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 U_RX_DATA_4 U_RX_DATA_3 U_RX_DATA_2 U_RX_DATA_1 U_TX_CLK VDD1I U_TX_CLAV VSS1I U_TX_DATA_7 U_RX_DATA_0 U_TX_DATA_6 U_TX_SOC U_TX_DATA_4 U_TX_DATA_5 T_INTP U_TX_DATA_3 T_MS U_TX_ENB U_TX_DATA_2 VDD3P T_DO VSS3P H_INT U_TX_DATA_1 U_TX_DATA_0 U_TX_ADDR_4 U_TX_ADDR_3 VSS1I U_TX_ADDR_2 VDD1I U_TX_ADDR_1 B_EXT_CLK U_TX_ADDR_0 VSS3O B_NTR VDD3O T_CLK B_GP_OUT_1 T_DI B_GP_OUT_0 G.dmt ADSL Transceiver for CO and CPE 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 S5N8950 G.dmt ADSL Transceiver for CO and CPE 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 A_SDI A_AND A_SEN VSS1I VDD1I A_SDO A_SCLK A_BUSY A_RX_PWR A_TX_PWR A_PME VSS3P VDD3P A_RSTN A_AD_AUX_CLK A_AD_REF_CLK A_AD_DATA_6 A_AD_DATA_5 A_AD_DATA_4 VSS1I VDD1I A_AD_DATA_3 A_AD_DATA_2 A_AD_DATA_1 A_AD_DATA_0 A_DA_AUX_CLK A_DA_REF_CLK VSS3O VDD3O A_DA_DATA_6 A_DA_DATA_5 A_DA_DATA_4 A_DA_DATA_3 A_DA_DATA_2 A_DA_DATA_1 VSS1I VDD1I A_AD_DATA_0 UA_RX_DATA UA_TX_DATA H_SEL H_CSN H_RDN VDD3O H_WRN VSS3O H_ADDR_0 H_ADDR_1 B_NMODE H_ADDR_2 H_ADDR_3 VDD1I H_ADDR_4 VSS1I H_ADDR_5 H_ADDR_6 B_TMODE H_ADDR_7 H_ADDR_8 VDD3OP H_ADDR_9 VSS3OP H_DATA_0 H_DATA_1 B_RSTN H_DATA_2 H_DATA_3 VDD1I H_DATA_4 VSS1I H_DATA_5 B_MSC_CLK H_DATA_6 B_BMODE_0 H_DATA_7 VDD3P H_READY VSS3P H_WAKEUP B_BMODE_1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 U_RX_DATA_5 U_RX_DATA_6 U_RX_DATA_7 U_RX_ADDR_0 VDD3O VSS3O U_RX_ADDR_1 U_RX_ADDR_2 U_RX_ADDR_3 U_RX_ADDR_4 U_RX_ENB U_RX_SOC U_RX_CLK U_RX_CLAV VDD1I VSS1I P_VDD18A2 P_VSS18A2 P_PLL_FILTER P_VDD18A1 P_VSS18A1 P_VBBA S1_TX_DAV S1_TX_CLK VDD3P VSS3P S1_RX_DATA S1_RX_DAV P_XTAL_IN P_XTAL_OUT S1_TX_DATA S1_RX_CLK S2_TX_DATA S2_TX_DAV VDD1I VSS1I S2_TX_CLK S2_RX_DATA S2_RX_DAV S2_RX_CLK Figure 3: Pin configuration CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE Interface Type Mnemonic Type ATM interface U_TX_ADDR[4:0] U_TX_DATA[7:0] U_TX_ENB U_TX_SOC U_TX_CLK U_TX_CLAV U_RX_ADDR[4:0] U_RX_DATA[7:0] U_RX_ENB U_RX_SOC U_RX_CLK U_RX_CLAV I I I I I OZ I OZ I OZ I OZ PHTICD PHTICD PHTICD PHTICD PHTICD PHTOT4 PHTICD PHTOT4 PHTICD PHTOT4 PHTICD PHTOT4 Utopia Tx Address Utopia Tx Data Utopia Tx Enable Utopia Tx Start of Cell Utopia Tx Clock. 25 MHz Utopia Tx Cell Available Utopia Rx Address[4:0] Utopia Rx Data[7:0] Utopia Rx Enable Utopia Rx Start of Cell Utopia Rx Clock. 25 MHz Utopia Rx Cell Available STM interface S1_TX_DAV S1_TX_CLK S1_TX_DATA S1_RX_DAV S1_RX_CLK S1_RX_DATA S2_TX_DAV S2_TX_CLK S2_TX_DATA S2_RX_DAV S2_RX_CLK S2_RX_DATA O O I O O O O O I O O O PHOB4 PHOB4 PHTICD PHOB4 PHOB4 PHOB4 PHOB4 PHOB4 PHTICD PHOB4 PHOB4 PHOB4 Serial Tx data valid signal in the 1-st STM Serial Tx clock in the 1-st STM Serial Tx data in the 1-st STM Serial Rx data valid signal in the 1-st STM Serial Rx clock in the 1-st STM Serial Rx data in the 1-st STM Serial Tx data valid signal in the 2-nd STM Serial Tx clock in the 2-nd STM Serial Tx data in the 2-nd STM Serial Rx data valid in the 2-nd STM Serial Rx clock in the 2-nd STM Serial Rx data in the 2-nd STM H_SEL H_ADDR[9:0] H_DATA[7:0] H_CSN I I B I PHTICD PHTICD PHTBCDT6SM PHTICD H_RDN I PHTICD H_WRN I PHTICD OZ PHTOT4 H_INT O PHOB4 H_WAKEUP O PHOB4 Host type : [0]=Motorola / [1]= Intel Host address bus Host data bus Chip selection Motorola Not used. Intel Read enable ( active low ) Motorola [0]=write enable / [1]=read enable Intel Write Enable ( active low ) Motorola Host CPU DTACK ( active low ) Intel Host CPU Ready (active high ) Motorola Interrupt IRQ ( active low ) Intel Interrupt INT ( active high ) Host Wakeup Host Interface H_READY CONFIDENTIAL Driver Function Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE AFE interface Board / PLL interface TeakLite Interface A_AD_DATA[6:0] A_AD_REF_CLK A_AD_AUX_CLK A_DA_DATA[6:0] A_DA_REF_CLK A_DA_AUX_CLK A_SDI A_AND A_BUSY A_SCLK A_SDO A_SEN A_PME A_TX_PWR A_RX_PWR A_RSTN I I I O O O I I I O O O O O O O PHICD PHICD PHICD PHOB2 PHOB2 PHOB2 PHICU PHICD PHICD PHOB2 PHOB2 PHOB2 PHICD PHOB2 PHOB2 PHOB2 ADC data for 2 phase. ADC data reference clock for DMT b2b test ADC data strobe clock for DMT b2b test DAC data for 2 phase DAC data reference clock DAC data strobe clock AFE serial input data Audible noise detection (active high) AFE busy ( active high) AFE serial clock AFE serial output data AFE serial enable ( active low ) AFE power management enable TX line driver power enable ( active high ) RX line driver power enable ( active high ) AFE reset ( active low ) B_RSTN B_GP_OUT[1:0] I O PHIS PHOB2 B_BMODE[1:0] I PHIC B_TMODE I PHIC B_NMODE I PHIC B_NTR B_EXT_CLK B_MSC_CLK P_XTAL_IN P_XTAL_OUT P_PLL_FILTER B I I I O O PHTBCT4 PHIC PHIC POAR50_ABB System reset ( active low ) General purpose output TeakLite boot mode selection [0] = simple reset [1] = boot from Host CPU ( normal mode ) [2] = boot from JTAG ( emulation mode ) [3] = self-booting ( test mode ) Test Mode Enable (DSP view, Scan Test, Memory BIST, PLL Test) [0] Normal, [1] Test Mode NAND tree test mode [0] Normal, [1] NAND tree test mode ATM Network Timing Reference external clock misc. clock for BIRA test XTAL input for clock. XTAL output for clock. Internal PLL pump out connected to filter. T_MS T_CLK T_DI T_DO T_INTP I I I OZ O PHTICD PHTICD PHTICD PHTOT4 PHOB4 TeakLite JTAG test mode select TeakLite JTAG test clock TeakLite JTAG test input data TeakLite JTAG test output data TeakLite TJAM interrupt to host CONFIDENTIAL PHSOSCM26 Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE UART interface UA_TX_DATA UA_RX_DATA O I Power interface P_VDD18A2 P_VSS18A2 P_VDD18A1 P_VSS18A1 P_VBBA P_VDD1I P_VSS1I P_VDD3O P_VSS3O P_VDD3P P_VSS3P P_VDD3OP P_VSS3OP I I I I I I I I I I I I I PHOB4 PHTICD VDD1T_ABB VSS1T_ABB VDD1T_ADD VSS1T_ABB VBB1_ABB VDD1I VSS1I VDD3O VSS3O VDD3P VSS3P VDD3OP VSS3OP UART Rx data UART Rx data Digital power supply Digital ground Analog power supply Analog ground bulk ground 1.8 V internal power. 1.8 V internal ground 3.3 V output-driver power 3.3 V output-driver ground 3.3 V pre-driver power 3.3 V pre-driver ground 3.3 V output driver and pre-driver power 3.3 V output driver and pre-driver ground Table 1: Pin configuration CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE Pad PHTIC PHTICD PHTOT4 PHOB4 PHOB2 PHIC PHICD PHICU PHICD PHIS PHTBCT4 I/O I I OZ O O I I I I I B PHTBCT6SM B PHTBCDT6SM B POAR50_ABB O PHSOSCM26 VDD1T_ABB VSS1T_ABB VBB1_ABB VDD1I VSS1I VDD3O VSS3O VDD3P VSS3P VDD3OP VSS3OP I/O I I I I I I I I I I I Description 5V tolerant for 3.3 V interface LVCMOS level input buffer 5V tolerant for 3.3 V interface LVCMOS level input buffer with pull-down register. 5V tolerant for 3.3 V interface tri-state output buffer driving 4 mA 3.3 V LVCMOS normal output buffer driving 4 mA 3.3 V LVCMOS normal output buffer driving 2 mA 3.3 V interface LVCMOS level input buffer 3.3 V interface LVCMOS level input buffer with pull-down register. 3.3 V interface LVCMOS level input buffer with pull-up resister 3.3 V interface LVCMOS level input buffer with pull-down resister 3.3 V interface LVCMOS Schmitt-trigger level input buffer 3.3 V interface 5 V tolerant LVCMOS level tri-state bi-directional buffer driving 4 mA 3.3 V interface 5 V tolerant LVCMOS level tri-state bi-directional buffer driving 6 mA medium slew rate control 3.3 V interface 5 V tolerant LVCMOS level tri-state bi-directional buffer driving 6 mA medium slew rate control with pull-down register. Analog normal output pad for 1.8 V interface with resister 50 Ohm and separated bulk bias Oscillator cell with enable and feedback resistor. Power, 1.8 V total with separate bulk bias Ground, 1.8 V total with separate bulk bias Ground, 1.8 V bulk bias VDD for 1.8 V internal power VSS for 1.8 V internal power VDD for 3.3 V output driver power VSS for 3.3 V output driver power VDD for 3.3 V pre- driver power VSS for 3.3 V pre- driver power VDD for 3.3 V output driver and pre- driver power VSS for 3.3 V output driver and pre- driver power Table 2: Pad description CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 4 Functional Description The G.dmt ADSL transceiver consists of two main chips; G.dmt ADSL transceiver chip (S5N8950) and Analog Front End chip (S5N8951). The AFE provides an analog interface with line driver and hybrid components to connect the PSTN. The G.dmt ADSL transceiver provides all the digital functional as DMT Modulator Channel Encoder Interpolator AFE Tx interface DMT Demodulator Echo canceller Channel Decoder Serial interface Framer/de-Framer UTOPIA interface TC depicted in Figure 4. Decimator AFE Rx interface Control Bus Host interface JTAG interface PLL TeakLite DSP core SRAM for Program & Data UART interface Figure 4: Block diagram The input bit stream is divided into bit slices and they are fed into the QAM, which are allocated to 256 sub-channels according to the bit loading table. The bit slices are then converted to frequency-domain complex samples by the QAM encoder. The 256 complex samples are changed to 512 time-domain samples by IFFT. The Tx filter performs band separation and interpolation functions. The received signals are attenuated and distorted in terms of both phase and amplitude. PLL fixes the phase errors within 4 samples using the 276 kHz pilot tone transmitted from the CO side. The ones over 4 CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE samples are fixed by the sync recovery algorithm using a known synchronization symbol. The TEQ is a filter that adaptively alters the channel so that the impulse response is reduced to the length of the cyclic prefix which will be removed prior to FFT. The FEQ is a one tap complex adaptive filter for each subchannel, which adjusts the gains and phases of the received signals. The equalizers are adaptively updated due to the transmission channel environment. In FDM-based DMT modulation, the frequency band, 0 to 1.104 MHz, is divided into 256 equi-spaced sub-channels, of which 26 KHz (#6) to 134 KHz (#31) is allocated for the upstream, and 142 KHz (#33) to 1.100 MHz (#255) for the downstream. The Nyquist rate, therefore, should be 2.208 MHz (276kHz). DMT inherently transmits an optimized time-variable spectrum. This spectrum is adjusted according to the desired data rate and the transmission characteristics (transfer function and noise spectrum) on each and every sub-channel. For this, CO and CPE transmit 128.4 KHz wide tone downstream and upstream respectively to each other during initialization. They measure the quality of each of these received tones and then decided whether a tone has sufficient quality to be used for further transmission and, if so, how much data this tone should carry relative to the other tones that are used. They inform the bit lo9ading result to each other. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 5 I/O Timing Description 5.1 AFE Data Interface Timing Information t1 t2 t3 A_DA_REF_CLK (8.832 MHz) A_DA_AUX_CLK (4.416 MHz) A_DA_DATA[6:0] N-1 N-1 N N phase1(LSB) phase2(MSB) phase1(LSB) phase2(MSB) A_AD_DATA[6:0] N-1 N-1 N N phase1(LSB) phase2(MSB) phase1(LSB) phase2(MSB) Table 3: AFE data interface timing diagram. Parameter t1 t2 t3 Description A_DA_AUX_CLK setup to A_DA_REF_CLK ↑ DATA delay after A_DA_REF_CLK ↓ A_DA_AUX_CLK hold to A_DA_REF_CLK ↑ Min Max 10 10 10 Unit § À § À § À Table 4: AFE data interface timing table. 5.2 AFE Control Interface Timing Information t2 t3 A_SEN A_SCLK (1.104 MHz) A_SDO CS1 CS0 A4 ... A0 RW D15 ... D0 D15 ... D0 t1 A_SDI A_BUSY Figure 5: AFE control interface timing diagram. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE Parameter t1 t2 t3 Description A_SDI setup to A_SCLK ↑ A_SEN ↓ before A_SCLK ↑ A_SEN ↓ from A_SCLK ↑ Min 30 30 15 Max Unit § À § À § À Max Unit § À § À § À § À § À Table 5: AFE control interface timing table. 5.3 Motorola Read Cycle Timing Information H_ADDR[9:0] H_DATA[15:0] VALID t1 H_CSN t5 H_WRN t2 t3 t4 H_READY (DTACKN) Figure 6: Motorola read cycle timing diagram. Parameter t1 t2 t3 t4 t5 Description H_ADDR setup to H_CSN ↓ H_WRN ↑ before H_CSN ↓ H_DATA valid from H_READY ↓ H_READY hi-Z from H_CSN ↑ H_DATA hold after H_CSN ↑ Min 0 0 1 10 5 5 Table 6: Motorola read cycle timing table. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 5.4 Motorola Write Cycle Timing Information H_ADDR[9:0] H_DATA[15:0] VALID t1 t3 H_CSN t2 t5 H_WRN t4 H_READY (DTACKN) Figure 7: Motorola write cycle timing diagram. Parameter t1 t2 t3 t4 t5 Description H_ADDR setup to H_CSN ↓ H_WRN ↓ before H_CSN ↓ H_DATA valid from H_READY ↓ H_READY hi-Z from H_CSN ↑ H_DATA hold after H_CSN ↑ Min 0 0 Max 50 5 1 5 Unit § À § À § À § À § À Table 7: Motorola write cycle timing table. 5.5 Intel Read Cycle Timing Information H_ADDR[9:0] H_DATA[15:0] VALID t1 t2 t3 t6 H_CSN H_RDN t5 t4 H_READY Figure 8: Intel read cycle timing diagram. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE Parameter t1 t2 t3 t4 t5 t6 Description H_ADDR setup to H_CSN ↓ H_CSN ↓ before H_RDN ↓ H_DATA valid from H_RDN ↓ H_CSN ↑ from H_RDN ↑ H_READY ↓ from H_RDN ↓ H_DATA hold after H_RDN ↑ Min 0 0 Max 170 0 0 20 5 Unit § À § À § À § À § À § À Table 8: Intel read cycle timing table. 5.6 Intel Write Cycle Timing Information H_ADDR[9:0] H_DATA[15:0] VALID t1 t2 t3 t6 H_CSN H_WRN t5 t4 H_READY Figure 9: Intel write cycle timing diagram. Parameter t1 t2 t3 t4 t5 t6 Description H_ADDR setup to H_CSN ↓ H_CSN ↓ before H_WRN ↓ H_DATA valid from H_WRN ↓ H_CSN ↑ from H_WRN ↑ H_READY ↓ from H_WRN ↓ H_DATA hold after H_WRN ↑ Min 0 0 Max 50 0 0 5 20 Unit § À § À § À § À § À § À Table 9: Intel write cycle timing table. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 5.7 Byte Mode Non-ATM Interface Timing Information. t1 S1(2)_TX_CLK S1(2)_TX_DAV S1(2)_TX_DATA D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 S1(2)_RX_CLK S1(2)_RX_DAV S1(2)_RX_DATA Figure 10: Byte mode non-ATM interface timing diagram. Parameter t1 Description S1(2)_TX_CLK frequency Min 1 Max 25 Unit MHz Table 10: Byte mode non-ATM interface timing table. 5.8 Envelope Mode non-ATM Interface Timing Information S1(2)_TX_CLK S1(2)_TX_DAV S1(2)_TX_DATA D0 D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 t1 S1(2)_RX_CLK S1(2)_RX_DAV S1(2)_RX_DATA D0 Figure 11: Envelope mode non-ATM interface timing diagram. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE Parameter t1 Description S1(2)_RX_CLK frequency Min 1 Max 25 Unit MHz Table 11: Envelope mode non-ATM interface timing table. 5.9 UTOPIA-2 ATM Interface Timing Information t1 U_TX_CLK (25 MHz) U_TX_ADDR[4:0] 00 1F 01 P46 P47 P48 1F 02 1F 03 1F 04 U_TX_CLAV U_TX_ENB U_TX_DATA[7:0] H1 H2 H3 U_TX_SOC (ATM0) (ATM1) Figure 12: UTOPIA-2 ATM interface timing diagram. Parameter t1 Description Signal Hold after U_TX_CLK ↑ Min 5 Max 10 Unit § À Table 12: UTOPIA-2 ATM interface timing table. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 5.10 UTOPIA-2 ATM Interface Timing Information t1 U_RX_CLK (25 MHz) U_RX_ADDR[4:0] 00 1F 01 1F P45 P46 P47 P48 02 1F 03 1F 04 U_RX_CLAV U_RX_ENB U_RX_DATA[7:0] H1 H2 U_RX_SOC (ATM0) (ATM1) Figure 13: UTOPIA-2 ATM interface timing diagram. Parameter t1 Description Signal Hold after U_RX_CLK ↑ Min 5 Max 10 Unit § À Table 13: UTOPIA-2 ATM interface timing table. CONFIDENTIAL Preliminary Information ( Rev 1.2 ) S5N8950 G.dmt ADSL Transceiver for CO and CPE 6 Electrical Characteristics Symbol ILATCH TSTG Parameter Latch-up Current Storage Temperature Rating ± 200 £ 65 ~ 150 Unit mA °C Table 14: Absolute Maximum Ratings Symbol VDD TA Parameter DC Input Voltage Analog Core DC Supply Voltage Operating Temperature (Ambient) Rating 1.8 V I/O 3.3 V I/O 5V-tolerant I/O 1.8 V Core Unit 1.65 ~ 1.95 3.0 ~ 3.6 3.0 ~ 3.6 1.8±5% -40 to 85 V °C Table 15: Recommended Operating Conditions Symbol PD Parameter Power Dissipation Min Typ 716 Max Unit § Ñ Table 16: Power Dissipation Symbol VIH VIL VOH VOL VT VT+ VTIIH IIL IOZ IDD CIN COUT Parameters Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Switching Threshold Schmitt Trigger, Positive-going Threshold Schmitt Trigger, Negative-going Threshold Input High Current (VIN=VDD) Input Low Current (VIN=VSS) Tri-state Output Leakage Current Quiescent Supply Current Input Capacitance Output Capacitance Min 2.0 Typ Max Unit 0.8 2.4 0.4 V 1.4 2.0 0.8 -10(10) -10(-60) -10 (33) (-33) 10(60) 10(-10) 10 100 4 4 µA pF NOTE: ( ) – Input buffer with pull-down Table 17: DC Characteristics CONFIDENTIAL Preliminary Information ( Rev 1.2 )