SAMSUNG S5T8809

PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
INTRODUCTION
16-TSSOP-0044
S5T8809 is a superior low-power-programmable PLL frequency
synthesizer which can be used in high performance / Simple
application for a Wide Area Pager system.
S5T8809 consists of 2 kinds of divider block including a 19-bit Shift
register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit NCounter, 32/33 Prescaler, and a phase detector block including a
Phase detector, Lock detector and a Charge pump.
S5T8809 also has a battery saving mode which can control each
register block by serial control data from the µ-controller (MICOM)
and it also has boost up signal output for fast locking.
( Magnification = 1 : 4 )
FEATURES
•
Maximum operating frequency: 330MHz @ 300mVP-P, VDD1 = 1.0V, VDD2 = 3.0V
•
On-chip reference oscillator supports external crystal which oscillates up to 23MHz
•
Superior supply current:
•
— FFIN = 310MHz, IDD1 = 0.8mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V
Operating voltage: VDD1 = 0.95 to 1.5V and VDD2 = 2.0 to 3.3V
•
Excellent Divider range:
— Ref. Divider:
FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default
FRC (1): 1 / 5 to 1 / 32767
— Rx Divider:
PBC (0): 1 / 1056 ~ 1 / 65535: Default
PBC (1): 1 / 1056 ~ 1 / 262143
•
Boost-up signal output for Fast Locking
•
In the Standby mode, VDD1 block can be controlled by BSB Pin status
— Standby current consumption: 10µA (Max.)
•
Programmable control the output of LD to reduce internal noise
•
Programmable 17 / 19-bit shift register value controlled by PBC
•
Charge pump output circuitry for passive filter
•
Package type: 16−TSSOP (0.65mm)
ORDERING INFORMATION
Device
Package
Operating Temperature
+S5T8809X01-R0B0
16−TSSOP−0044
−25°C to +75°C
+: New Product
1
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
BLOCK DIAGRAM
OSCI 1
OSCO
Amp
2
FRC
VDD1
VDD2
13 or 15 Bit
Divider
( R - counter )
1/8
Prescaler
3
VDD2
13 / 15
16
Lock
Detector
10
LD
16 or 18Bit Latch
2
(Test1. LDC)
Schmitt
Trigger
BSB
14
EN
13
DATA
12
CLK
11
16 / 18
Phase
Detector
Shift Register*
17 or 19 Bit
18
VSS
Schmitt
Trigger
6
Charge
Pump
5
PDO
Fast
Lock
4
FL
Schmitt
Trigger
15
FLC
9
PBC
16 or 18Bit Latch
18
2
Fin
7
VDD1
8
Amp
VDD1
32/33
Prescaler
5 Bit
Swallow
Counter
POR
11 or 13 bit
Main Counter
Schmitt
Trigger
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
PIN CONFIGURATION
OSCI
1
16
TEST
OSCO
2
15
FLC
VDD2
3
14
BSB
FL
4
13
EN
PDO
5
12
DATA
VSS
6
11
CLK
Fin
7
10
LD
VDD1
8
9
PBC
KS8809D
S5T8809
3
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
PIN DESCRIPTION
Pin No
Symbol
Description
1
OSCI
2
OSCO
These input / output pins generate the reference frequency.
In case of OSCI Pin, external reference frequency can be used through the AC coupling.
3
VDD2
4
FL
5
PDO
The output of RX phase detector terminal for passive loop filter.
There are 3-kinds of output signal states according to Rx loop error.
6
VSS
Ground terminal
7
Fin
Input terminal for the frequency from VCO.
Output frequency from VCO was inputted through AC coupling
8
VDD1
Voltage supply terminal for Oscillator and Fin block.
This pin can be supplied up to 0.95 ~ 1.5V from VSS.
9
PBC
This is an input for programmable bit control which has Schmitt Trigger architecture,
Internally biased pull-up.
High = 16 Bits N-Divider (Default: ND0 ~ ND15)
Low = 18 Bits N-Divider (ND0 ~ ND7)
cf) R-divider bits will be changed by the FRC bit of program
10
LD
The output of phase detector can be controlled by R-counter register. When the LDC bit
of R-counter set to Low, the output will be disabled to reduce a noise problem, but if it is
set to High, the output will be enabled to show an lock / unlock status that is the error
width between to Ref. signal and the VCO output signal.
11
CLK
12
DATA
13
EN
These pins are controlled by the µ-controller which has Schmitt Trigger architecture,
Internally biased pull-down. The features of these pins are as follows; Clock input for 17
or 19-bit Shift Register, Serial data input (it include TEST1, FRC and LDC), and Latch
enable input.
14
BSB
In the BS mode (set to Low), the VDD1 block will be powered off, but the internal latch
data is still valid because the VDD2 is supplied continuously. This input has Schmitt
Trigger architecture & internally biased pull-up.
15
FLC
This is the input pin for Fast Locking Control (FLC) which has Schmitt Trigger
architecture, Internally biased pull-down.
Low = The Current of PDO Charge pump output is Normal (Default: x1)
High = The Current of PDO Charge pump output is increase (x 1.5)
16
TEST
4
The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V.
Booster signal output for fast locking.
This is the input pin for TEST which has Schmitt trigger architecture, Internally biased
Pull-down.
Low = All block will be operated as normal state (Default)
High = LD and FL state will be TES mode
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
VDD ~ VDD2
−0.3 ~ +4.0
V
Input Voltage
VI
VSS −0.3 ~ VDD + 0.3
V
Power Dissipation
PD
350
mW
Operating Temperature
TOPR
−25 ~ +75
°C
Storage Temperature
TSTG
−40 ~ +125
°C
Supply Voltage
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VDD1 = 1.0V, VDD2 = 3.0V, unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VDD1
−
0.95
1.0
1.5
V
VDD2
−
2.0
3.0
3.3
Operating current
IDD
FOSCI = 12.8MHz
FFIN = 310MHz @ 0.3VP-P
VDD1 = 1.0V, VDD2 = 3.0V, BSB=High
−
0.8
−
mA
Standby current
ISB1
VDD1 = 0.0V, VDD2 = 3.0V, BSB=Low
−
0.1
10
µA
V
Operating voltage
Input voltage
(DATA, CLK, EN, BS)
Input voltage
(TEST, PBC)
Input current
(Fin, Xin)
Input frequency
VIL
−
−
−
0.3
VIH
−
VDD2-0.3
−
−
VIL
−
−
−
0.2
VIH
−
VSS1-0.2
−
−
IIH
VIH = VDD1, BSB = High
−
−
20
IIL
VIL = 0V, BSB = High
−
−
20
VFIN = 0.3VP-P, VDD1 = 1.0V
40
−
330
VOSCI = 0.3VP-P, VDD1 = 1.0V
7
12.8
23
FFIN
FOSCI
Output current
(PDO, FL)
IOH1
VOH = 0.4V
1.0
−
−
IOL1
VOL = VDD2 - 0.4V
1.0
−
−
Output current
(LD)
IOH2
VOH = 0.4V
0.1
−
−
IOL2
VOL = VDD2 - 0.4V
0.1
−
−
V
µA
MHz
mA
mA
Setup-time
(DATA-CLK, CLK-EN)
ts
−
2
−
−
µS
Hold time
tH
−
2
−
−
µS
5
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
FUNCTIONAL DESCTRIPTION
Table 1. N-Counter Register Program Scheme (19 bit)
Bit
Bit 18 (ND 17) ~ Bit 1 (ND 0)
Bit 0 (LSB)
Name
ND
PMC
Description
N-Counter Data (ND 17 ~ ND 0)
Program Mode Control
Function
18 Bit Program Data
PBC = 1 : 16 bits (ND 15 ~ ND 0) will be valid
PBC = 1 : 18 bits (ND 17 ~ ND 0) will be valid
0: N-Counter Program
1: Ref. R-Counter Program
PMC = 0 → 16/18 bit N_Counter
PMC
N_Counter Divider Data ( ND17 ~ ND0 )
DATA
MSB
1
LSB
2
3
4
5
6
7
8
13
14
15
16
17
18
19
CLK
MSB : 1’st INPUT
positive edge triggered
EN
Figure 1. Rx. N - Counter Register Programming Timing
•
Programmable N-counter consists of 5-bits Swallow Counter, Dual modulars Prescaler and 11-bits Main
Counter (if [PBC = 0], than 13-bits Main Counter)
•
The Divide Ratio is;
N = (P + 1) × S + P (M - S) = PM + S;
P = Dual Modular Prescaler (32)
S = 5-bits Swallow Counter value (0 ~ 31)
M = 11-bits (PBC = High, 32 ~ 2047) or 13-bits (PBC = Low, 32 ~ 8291)
N = Programmable N-Counter value (N > S)
•
The Main Counter can be controlled by PBC pin, when the PBC (pin 9) state set to Low, the Programmable
N-counter range will be extend to 262143
6
PLL FREQUENCY SYNTHESIZER FOR PAGER
•
S5T8809
Ex 1) In case of 16-bits program [PBC = High], Fc = 325.300MHz, Multiplier = 4, Fin = 75.975MHz
[Fin Freq. / Ref. Frequ.] = 75.975MHz / 6.25kHz = 1256
2
10
2
0
0
1
0
1
1
1
1
1
0
0
1
2
5
1
2
1
1
0
0
0
MSB
0
LSB
Main CNT 11 - bits
Swallow CNT 5-bits
PMC bit
NOTE: According to the above equation, 12156 / 32(P) = 379, and left = 28
that means, Swallow CNT value is “11100”, Main CNT value is “379”
•
Ex 2) In case of 18-bits program [PBC = Low], Fin = 330MHz
[Fin Freq. / Ref. Freq.] = [330MHz / 6.25kHz] = 52800
2
17
0
2
0
10
1
2
1
0
0
1
1
1
0
0
1
0
0
2
0
5
2
0
0
0
0
0
0
MSB
LSB
Main CNT 13 - bits
Swallow CNT 5-bits
PMC bit
NOTE: The PMC bit is program mode control bit, if [0], the N-counter will be enabled
Table 2. R-Counter Register Program Scheme (19 bits)
Bit
Bit 18 ~ Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Name
RD
LDC
FRC
TEST 1
PMC
Description
Ref. R-Counter Data
Lock Detector
Control
Frequency of
Reference
Control
TEST mode
control
Program mode
control
Function
15 Bit Programmable
0: Disable
Ref. R-Counter
LD out
FRC = 0 : 13 bits (RD12 — RD0) 1: Enable
FRC = 1 : 15 bits (RD14 — RD0) LD out
0: R_CNT div.
= 8 × RD
1: R_CNT div.
= RD (15bit)
Mainly for
the product
Test
0: ND Program
1: RD Program
•
The Input Reference Frequency (X-tal Oscillator) will be divided by 1/8 Prescaler, and then divided by preprogrammed R-counter value once more.
•
Programmable R-Counter consists of Fixed 1/8 Prescaler, 13 / 15-bits Programmable Counter
When FRC = 0, Fixed 1/8 Prescaler and 13-bits counter (Min. Divide value: 5) are enabled
RD = 8, R = 40 (= 8 × 5) ~ 65528 [Multiple 8]
When FRC = 1, Fixed 1/8 Prescaler is disabled, but using 15-bits counter (Min. Divide value: 5)
7
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
RD = R = 5 ~ 32767 [All value]
CONTROL MODE FOR R-COUNTER REGISTER
LDC
LDC Pin State
0
Low
1
Normal Operation
Description
LDC function is independent of the other Control Bit
FRC
R-Counter Value
Description
0
8 × R_cnt value (OSCI / 8 × R),
Use 13 bits R-Counter
1
R-cnt value (OSC / R),
Use 15 bits R-Counter
FRC function is independent of the other Control Bit
TEST1
TEST
LD state
FL state
Description
0
0
Normal
Normal
• FRC is independent of the other control bit
1
0
Normal
Normal
• Test is internal register control bit
but, Test is external control pin
0
1
Fn (N-CNT)
High state
1
1
Fr (N-CNT)
Normal
• Test is related with Test,
when Test = High → Test Mode
PMC = 1 → 13/15 bit R-Counter, LDC, FRC, TEST1
PMC
R_Counter Divider Data ( RD14 ~ RD0 )
LDC FRCTEST1
DATA
MSB
1
LSB
2
3
4
5
6
7
8
13
14
15
16
17
CLK
MSB : 1’st INPUT
positive edge triggered
EN
Figure 2. Ref. R-Counter Register Programming Timing
8
18
19
PLL FREQUENCY SYNTHESIZER FOR PAGER
•
S5T8809
Ex 1) FRC = 0, In case of 13bits Program, Fosc = 12.8MHz and 1/8 prescaler is used
[(Osc. Freq. / Prescaler) / Ref. Freq.] = [(12.8MHz / 8) / 6.25kHz] = 256
2
12
2
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
MSB
LSB
LDC FRC TEST1 PMC bit
R - counter 13 - bits
•
Ex 2) FRC = 1, In case of 15bits Program, Fosc = 12.8MHz and 1/8 prescaler is used
[Osc. Freq. / Ref. Freq.] = [12.8MHz / 6.25kHz] = 2048
2
14
0
2
0
12
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
MSB
1
LSB
LDC FRC TEST1 PMC bit
R - counter 15 - bits
NOTE: The PMC bit is Program Mode Control Bit, if [1], the R-Counter will be Enabled
D0 ------------- D13
1/8
Prescaler
OSCI
1.6MHz
13/15 bits
Counter
Fr
6.25kHz
12.8MHz
12.8MHz
X-Tal
FRC
Figure 3. The architecture of R-Count Divider
9
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
D0 ------------- D13
1/8
Prescaler
OSCI
1.6MHz
13/15 bits
Counter
6.25kHz
12.8MHz
12.8MHz
X-Tal
FRC
OSCO
Figure 4. Serial DATA Input Timing
10
Fr
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
PHASE DETECTOR / LOCK DETECTOR
OSCI
1
OSCO
2
1/ 8
CNT
13 or 15 Bit
R- Divider
FRC
Fr
10
LD
Lock
Detector
Phase
Detector
5
PDO
4
FL
9
PBC
Fn
FLC
Fin
7
32/33
Counter
16 or 18 Bit
N- Divider
Figure 5. Phase Detector / Lock Detector
Fr
Fn
Z-State
PDO
VDD1
LD
GND
Z-State
FL
* Fast Lock Operation Window
Window width = OSCI x 4
Figure 6. Figure 5-2. Phase Detector / Lock Detector / Fast Lock Output Waveforms
NOTES:
1.
Phase detector always compares the Phase difference of N-counter with R-counter, and generates High or Low
State as much as the phase difference
2.
The LD output is set to Low level same as Phase detector error width
11
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
FAST LOCK
The Fast lock can gives faster Acquisition time when the S5T8809 starts up. If Fast Lock signal was generated one
time, this circuitry do not operate again even though PLL goes into unlock state.
S5T8809 has two did of Fast lock; one is to control the Loop band width of Loop filter, the other is to control the
charge pump current.
Mode 1
CP2
Mode 2
CP1
* During CP2 operation,
I pdo = I cp1 + I cp2
Fast
Lock
Phae
Detector
PDO
VCO
Charge
Pump
VCO
PDO
Phase
Det.
Fast
Lock
FL
FL Ref. clock
Charge
Pump
• CP1: Default charge pump output TR
• CP2: When FLC = High, CP2 goes [On] state, the
Timming & Phase is just same as FL signal
• Mode 1 does not used FL pin, only increase PDO
output current same as the width of 1’st phase error
12
FL Ref. clock
• Exceeding a Loop Band width during Fast Lock
operation
• When the FLC pin set to High level, this function will be
available
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
Fr
R - Counter output
Fn
N - Counter output
Vdd2
Z-state
PDO
FL Ref. CLK
Vdd2
FL
Z-state
Vdd2
CP2 On Time
(FLC = High)
Z-state
Figure 7.
13
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
NOTES
14