VISHAY SI1469DH

SPICE Device Model Si1469DH
Vishay Siliconix
P-Channel 12-V (G-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 74370
S-70353Rev. A, 26-Feb-07
www.vishay.com
1
SPICE Device Model Si1469DH
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
Measured
Data
VGS(th)
VDS = VGS, ID = −250 µA
1.1
ID(on)
VDS ≤ −5 V, VGS = −4.5 V
37
VGS = −10 V, ID = −2 A
0.064
0.065
VGS = −4.5 V, ID = −1.8 A
0.079
0.081
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
Forward Transconductancea
Diode Forward Voltage
a
rDS(on)
V
A
Ω
VGS = −2.5 V, ID = −1.5 A
0.124
0.126
gfs
VDS = −10 V, ID = −2 A
9
6
S
VSD
IS = −2 A
−0.84
−0.83
V
558
470
104
105
b
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
82
80
Total Gate Charge
Qg
5
5.5
Gate-Source Charge
Qgs
0.80
0.80
Gate-Drain Charge
Qgd
1.7
1.7
VDS = −10 V, VGS = 0 V, f = 1 MHz
VDS = −10 V, VGS = −4.5 V, ID = −2.5 A
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
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Document Number: 74370
S-70353Rev. A, 26-Feb-07
SPICE Device Model Si1469DH
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 74370
S-70353Rev. A, 26-Feb-07
www.vishay.com
3