TL7231MD
FULL LAYER-III ISO/IEC 11172-3 AUDIO DECODER
n
n
n
n
n
Single-chip ISO/IEC 11172-3 Layer n
III Audio Decoder
n
Supports All MPEG Bit Rates
n
Including Free Format
Supports 32/44.1/48KHz Sampling
n
Frequencies for MPEG Bit Stream
n
Supports Single Channel, Dual
Channel, Stereo, and Joint Stereo n
6-Band Equalizer Function
Voice Record/Playback Capability
On-chip DAC with 1-bit Sigma Delta
Modulation
Supports Off-chip DAC Interface
On-chip ADC with 12-bit Resolution
Power Management to Reduce
Power Consumption
Any Combination of Intensity
Stereo and MS Stereo is
supported.
n
PLL for Internal Clocks and for
Output PCM Clock Generation
n
Serial Bit Stream Input
n
n
8-bit Host Interface Port
Single 16.9344MHz External Clock
Input
n
Digital Volume Control
n
3.0 V Operation
n
Digital Bass/Treble Control
n
Small Footprint 100-pin Thin Quad
Flat Package
DESCRIPTION
TL7231MD is a single-chip ISO/IEC 11172-3 Layer III audio decoder, capable of decoding
compressed elementary bit streams as specified in ISO/IEC standard. Since it integrated onchip ADC and on-chip DAC, it can provide you more small and cheaper solution for MP3 player
application. It is designed to be well suited for portable audio appliances.
TL7231MD receives the input data bit stream through a serial data interface. The decoded
signal is 16-bit serial PCM format that can be sent directly to DAC. The generated PCM data
can be sent to on-chip DAC or off-chip DAC according to user preference. The off-chip DAC
interface is programmable to adapt the PCM output of TL7231MD to the most common DACs
used on the market.
An 8-bit host interface port is provided to receive control information from and send status
information to host. 8-bit microcontrollers such as those of Intel or Motorola can be connected
easily.
TL7231MD has the capability of compressing voice signals. It can receive voice signals through
on-chip ADC. The compressed voice signals are transmitted to or received from host through
serial data interface. It can also reproduce the voice signals from the compressed voice signals.
September 1999
1/37
TL7231MD
FUNCTIONAL BLOCK DIAGRAM
CONSTANT
ROM
INPUT
BUFFER
OUTPUT
BUFFER
WORKING
SPACE
PROGRAM
ROM
DATA READ0
HD7:0
DATA READ1
M
U
X
DATA WRITE0
HOST
INTERFACE
HALE
HRD#
HWR#
HSEL#
DATA WRITE1
DMA BUS
CLKXRM
SERIAL1
CPUXI
CPUXO
WRITE DATA1
WRITE DATA0
PWRDN
RESET/
CLOCK
UNIT
READ DATA1
RESET
WAKEUP
BUS CONTROL UNIT
READ DATA0
FILTER
DMA
CONTROLLER
DXRM
REQSTRM
DACMSCK
DACBCK
DACLRCK
DACSDATA
DACDEEM
DACMUTE#
CRC
DAC
AOUTL
AOUTR
SERIAL0
DSP Core Unit
TIMER0
ADC
ADCAIN
TIMER1
Figure 1. Functional Block Diagram of TL7231MD
2/37
SAMSUNG Electronics Co.
TL7231MD
AOUTL
DACVBB
VSS
NC
VSS
NC
VSS
NC
NC
NC
VDD
VSS
VDDIO
VSSIO
DACMUTE#
DACDEEM
DACSDATA
DACLRCK
DACBCK
DACMSCK
VSS
VSS
VSS
VSS
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
DACVREF
100
99
PIN DESCRIPTION
DACVSSA
1
75
VSS
DACVDDA
2
74
VSS
DACVHALF
3
73
VSS
AOUTR
4
72
VSS
DACVSSD
5
71
VDD
DACVDDD
6
70
NC
ADCAIN
7
69
NC
ADCVSSA
8
68
NC
ADCVBB
9
67
VDD
ADCVDDA
10
66
VSS
ADCREFN
11
65
VDDIO
ADCREFP
12
64
VSSIO
ADCVSSD
13
63
CLKXRM
ADCVDDD
14
62
DXRM
PLLVDDA
15
61
REQSTRM
PLLVSSA
16
60
VDD
PLLVBB
17
59
HALE
FILTER
18
58
HSEL#
CPUXO
19
57
HRD#
CPUXI
20
56
HWR#
VDD
21
55
HD7
VSS
22
54
HD6
BCLK
23
53
HD5
VDD
24
52
HD4
VSS
25
51
HD3
TL7231MD
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
WAKEUP
PWRDN
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VDDIO
VSSIO
NC
NC
NC
NC
VSS
VSS
VSS
HD0
HD1
HD2
27
VSSIO
RESET
26
VDDIO
TOP VIEW
Figure 2. 100-pin Thin Quad Flat Package (TQFP)
SAMSUNG Electronics CO.
3/37
TL7231MD
Table 1. Pin Locations with Pin Names
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
4/37
NAME
DACVSSA
DACVDDA
DACVHALF
AOUTR
DACVSSD
DACVDDD
ADCAIN
ADCVSSA
ADCVBB
ADCVDDA
ADCREFN
ADCREFP
ADCVSSD
ADCVDDD
PLLVDDA
PLLVSSA
PLLVBB
FILTER
CPUXO
CPUXI
VDD
VSS
BCLK
VDD
VSS
PIN
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NAME
VDDIO
VSSIO
RESET
WAKEUP
PWRDN
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VDDIO
VSSIO
NC
NC
NC
NC
VSS
VSS
VSS
HD0
HD1
HD2
PIN
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
NAME
HD3
HD4
HD5
HD6
HD7
HWR#
HRD#
HSEL#
HALE
VDD
REQSTRM
DXRM
CLKXRM
VSSIO
VDDIO
VSS
VDD
NC
NC
NC
VDD
VSS
VSS
VSS
VSS
PIN
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NAME
VSS
VSS
VSS
VSS
DACMSCK
DACBCK
DACLRCK
DACSDATA
DACDEEM
DACMUTE#
VSSIO
VDDIO
VSS
VDD
NC
NC
NC
VSS
NC
VSS
NC
VSS
DACVBB
AOUTL
DACVREF
SAMSUNG Electronics Co.
TL7231MD
Table 2. Pin Functions with Location
NAME
ADCAIN
ADCREFN
ADCREFP
ADCVBB
ADCVDDA
ADCVDDD
ADCVSSA
ADCVSSD
AOUTL
AOUTR
BCLK
CLKXRM
CPUXI
CPUXO
DACBCK
DACDEEM
DACLRCK
DACMSCK
DACMUTE#
DACSDATA
DACVBB
DACVDDA
DACVDDD
DACVHALF
DACVREF
PIN
7
11
12
9
10
14
8
13
99
4
23
63
20
19
81
84
82
80
85
83
98
2
6
3
100
NAME
DACVSSA
DACVSSD
DXRM
FILTER
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HALE
HRD#
HSEL#
HWR#
NC
NC
NC
NC
NC
NC
NC
NC
NC
SAMSUNG Electronics CO.
PIN
1
5
62
18
48
49
50
51
52
53
54
55
59
57
58
56
41
42
43
44
68
69
70
90
91
NAME
NC
NC
NC
PLLVBB
PLLVDDA
PLLVSSA
PWRDN
REQSTRM
RESET
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VSS
PIN
92
94
96
17
15
16
30
61
28
21
24
37
60
67
71
89
26
39
65
87
22
25
31
32
33
NAME
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSIO
VSSIO
VSSIO
VSSIO
WAKEUP
PIN
34
35
36
38
45
46
47
66
72
73
74
75
76
77
78
79
88
93
95
97
27
40
64
86
29
5/37
TL7231MD
Table 3. Pin Descriptions
Signal Name
Type
CPUXI
CPUXO
I
O
FILTER
O
BCLK
O
RESET
I
WAKEUP
I
PWRDN
I
CLKXRM
I
DXRM
I/O
REQSTRM
O
HSEL#
I
HALE
I
HRD#
I
HWR#
I
HD[7:0]
I/O
ADCAIN
I
ADCREFP
I
ADCREFN
I
6/37
Description
Internal PLL Interface
CPU Clock In. 16.9344MHz crystal clock input.
CPU Clock Out. 16.9344MHz crystal clock output.
Charge Pump Out. External capacitor should be connected
between this pin and analog ground.
Clock Signal
Processor Clock Output.
Reset & Power Down Control
Chip Reset. Reset input to the chip. Internal pull down.
Wake Up. When high, chip is waked up from SLEEP state. This pin
should be remained active at least 1 clock cycle and inactive before
the host issues next SLEEP command. Internal pull down.
Power Down. This pin controls PWRDOWN state. When high, chip
goes to very low power consumption state. After deactivation,
WAKEUP pin should be remained low at least 150µs. Internal pull
down.
(Restriction: This pin should be active ONLY in SLEEP state.
Otherwise, Chip reset should be activated.)
MCU Serial Interface
Serial Clock. MCU serial interface clock.
Serial Data. When MCU transmits data, this data pin is sampled at
negative edge of CLKXRM. When MCU receives data, Data is valid
from negative edge of CLKXRM to next negative edge of CLKXRM.
DXRM should be sampled at positive edge of CLKXRM. After reset,
TL7231MD is set to transmit the most significant bit first.
Request Bit Stream Data. MCU must check this pin to determine to
continue receiving or transmitting. MCU should transmit or receive
data during this signal active.
MCU HIP(Host Interface Port) Interface
HIP Enable. When Low, HIP is selected.
HIP Address Latch Enable. When High, HD[7:0] should have HIP
address, which is sampled at negative edge of this signal.
HIP Read Enable. When low, data is loaded to HD[7:0], which
should be sampled at positive edge of this signal.
HIP Write Enable. Data at HD[7:0] is sampled at positive edge of
this signal.
HIP Address/Data Bus. Multiplexed address lines and data lines.
Internal ADC Interface
ADC Analog Input. Analog input spans between ADCREFP and
ADCREFN.
ADC Internal Reference Top Bias. Connect this pin to voltage
between ADCVDDA and 2.0V.
ADC Internal Reference Bottom Bias. Connect this pin to ground.
SAMSUNG Electronics Co.
TL7231MD
ADCVDDA
PWR
ADCVSSA
GND
ADCVDDD
PWR
ADCVSSD
ADCVBB
GND
GND
DACMSCK
DACBCK
DACLRCK
DACSDATA
O
O
O
O
DACDEEM
O
DACMUTE#
O
AOUTL
AOUTR
DACVHALF
DACVREF
O
O
I/O
I/O
DACVDDA
PWR
DACVSSA
GND
DACVDDD
PWR
DACVSSD
DACVBB
GND
GND
VDD
VSS
PWR
GND
VDDIO
PWR
VSSIO
GND
ADC Supply Voltage for Analog Circuit. Connect this pin to the
+3.0V supply voltage.
ADC Ground for Analog Circuit. Connect this pin to ground.
ADC Supply Voltage for Digital Circuit. Connect this pin to the
+3.0V supply voltage.
ADC Ground for Digital Circuit. Connect this pin to ground.
ADC Analog/Digital Bulk Bias. Connect this pin to ground.
External DAC Interface
DAC Master Clock. 384×Fs clock.
DAC Bit Clock. 32×Fs clock.
DAC Sample Rate Clock. Fs clock.
DAC Serial Data. Serial data.
DAC Deemphasis. When deemphasis is on, this signal is high. It
can be set/clear through HIP commands.
DAC Mute. Analog output mute. When external DAC is set to mute
on, this signal is low. It can be set/clear through HIP commands.
Internal DAC Interface
Analog Output for Left-Channel.
Analog Output for Right-Channel.
DAC Reference Voltage Output for Bypass.
DAC Reference Voltage Output for Bypass.
DAC Supply Voltage for Analog Circuit. Connect this pin to the
+3.0V supply voltage.
DAC Ground for Analog Circuit. Connect this pin to ground.
DAC Supply Voltage for Digital Circuit. Connect this pin to the
+3.0V supply voltage.
DAC Ground for Digital Circuit. Connect this pin to ground.
DAC Pad Bulk Bias. Connect this pin to ground.
Power/Ground Pins
Supply Voltage. Connect this pin to the +3.0V supply voltage.
Circuit Ground. Connect this pin to ground.
Supply Voltage for I/O Buffers. Connect this pin to the +3.0V
supply voltage.
Circuit Ground for I/O Buffers. Connect this pin to ground.
SAMSUNG Electronics CO.
7/37
TL7231MD
FUNCTIONAL DESCRIPTION
RESET/CLOCK UNIT
TL7231MD is driven by a single clock at the frequency of 16.9344MHz. The clock is derived
from an external source or from an industry standard crystal oscillator, generating input
frequency of 16.9344MHz. The clock generation unit has a PLL, and all the internal clock
signals including internal DAC/ADC clocks are generated with the input clock.
When TL7231MD is in power-on-reset, RESET signal should be active at least 150µs till the
internal PLL is stabilized. To reset TL7231MD during normal operation, RESET signal should be
active at least 16 cycles.
TL7231MD
CPUXI
30p
16.9344MHz
1M
30p
CPUXO
FILTER
820p
Figure 3. Clock Circuit
DSP CORE LOGIC
The core logic of TL7231MD is a 32-bit floating-point DSP processor. The independent multiplier
and accumulator of TL7231MD can achieve high performance. Internal registers are 40-bit
registers that store values with a 32-bit mantissa and an 8-bit exponent. These registers can
serve as both the source and destination for any arithmetic operation. Since all the data
input/output transactions are managed by DMA, there is no computational overhead due to data
transactions.
SERIAL INTERFACE
The serial interface of TL7231MD is used to receive MPEG bit stream data or transmit/receive
voice data. It is configured to transfer 8 bits of data per word. It can be configured to be LSBfirst or MSB first transfer mode. LSB-first means that the data bits are transmitted and received
least-significant bit (LSB) first. MSB-first means that the data bits are transmitted and received
most-significant bit (MSB) first. The clock for the serial interface should be generated externally.
The related signals are CLKXRM, DXRM, and REQSTRM. REQSTRM is used for
synchronization between microcontroller and TL7231MD, and data is transferred during
REQSTRM active.
8/37
SAMSUNG Electronics Co.
TL7231MD
When microcontroller tries to send data to TL7231MD, it should check whether REQSTRM is
active or not. If the signal is active, microcontroller sets its serial interface to transmit mode and
send serial clock and serial data. After transmitting each byte, microcontroller should check
REQSTRM to decide whether next byte is to be transmitted or not.
When microcontroller tries to receive data from TL7231MD, it should check whether REQSTRM
is active or not. If the signal is active, microcontroller sets its serial interface to receive mode
and send serial clock and receive serial data from TL7231MD. After receiving each byte,
microcontroller should check REQSTRM to decide whether TL7231MD will transmit next byte or
not.
HOST INTERFACE PORT (HIP)
Host interface port is used to send commands to and receive status information from
TL7231MD. HIP of TL7231MD is a parallel I/O port that makes a connection to a host processor
easily. Through the HIP, TL7231MD can be used as a memory-mapped peripheral to a host
processor. The HIP can be thought of as an area of dual-port memory that allows
communication between the computational core of the TL7231MD and host. The HIP is
completely asynchronous. The host processor can write data into the HIP while the TL7231MD
is operating at full speed. HIP transfers are managed using interrupt scheme.
HIP contains 21 registers. Four of them are data-in registers (HDI0/HDI1/HDI2/HDI3) and one of
them is a status register (HSR4). The remaining 16 registers are data-out registers
(HDO0/ …/HDO15). Data written into HDIs by host are read by TL7231MD. Through these
registers host can give necessary commands to TL7231MD. A command is written into a HDI0,
and the required parameters of the command are written into the HDI1/HDI2/HDI3. The status
register (HSR4) keeps the information whether data written into the data-in registers are read by
TL7231MD. The status register is managed automatically by TL7231MD and can be read by
host. TL7231MD starts HIP command processing when HDI0 register is written. So if any
command requires parameters, user should write parameters first, and then write command.
Serial ID number can be used to check whether given command has been accepted or not.
TL7231MD can receive the serial ID value through HDO0 when TL7231MD has accepted the
given command. Thus when commands are given to TL7231MD with different serial ID numbers,
it can be examined which command is being processed. Serial ID number itself hasn’t any
special meaning. If this feature is not needed, it is not required to send ID values with
commands. Then the value of HDO0 is undetermined. There is an exception for the ID number
convention. If you use HIP command 0Dh(Revision Code), TL7231MD returns the TL7231MD
revision number, not the ID number.
HDOs are written by TL7231MD and can be read by host. All HIP registers should be memorymapped into the memory space of the host processor. The address space of those registers is
shown in Table 4. The usable commands are listed in Table 6. The contents reported by HDOs
are shown from Figure 4 to Figure 16.
Table 4. Address of Host Interface Port Registers
SAMSUNG Electronics CO.
9/37
TL7231MD
ADDRESS
0h
1h
2h ~ 3h
4h
10h
11h
12h
13h
14h
15h
16h ~ 1Fh
REGISTERS
HDI0
HDI1
HDI2/HDI3
HSR4
HDO0
HDO1
HDO2
HDO3
HDO4
HDO5
HDO6 ~ HDO15
DESCRIPTION
Command
Serial ID Number
Parameters if needed
Status Register (Fig. 4)
Command Serial ID Number (Fig. 5)
Decoder State (Fig. 6)
IO Status (Fig.7)
IO Status (Fig. 8)
Volume (Fig. 9)
Serial Interface Mode (Fig. 10)
The information provided by these registers depends on
the mode setting of TL7231MD. (Refer to Table 5)
The information provided by HDO6 to HDO15 depends on the mode setting of TL7231MD.
Refer to Table 5. The mode can be set by using HIP command 19h(Report Format). For this
command, refer to Table 6.
Table 5. The contents of HDO6 ~ HDO15 according to mode setting
ADDRESS
REGISTERS
DESCRIPTION
16h
HDO6
17h
HDO7
18h
HDO8
19h
HDO9
1Ah
HDO10
Mode0: 00h
Mode1: Tone Control Status. When tone control is
enabled, 1 is reported. Otherwise, 0 is reported.
Mode2: MP3 Frame Count (Fig. 11)
Mode3: Voice Data Code Count (Fig. 11)
Mode4: Equalizer Control Status. When equalizer control
is enabled, 1 is reported. Otherwise, 0 is
reported.
Mode0: 00h
Mode1: Tone Control - Prescaling Information
Mode2: MP3 Frame Count (Fig. 11)
Mode3: Voice Data Code Count (Fig. 11)
Mode4: EQ Control – Prescaling Information
Mode0: 00h
Mode1: Tone Control – Bass Cutoff Frequency
Mode2: MP3 Frame Count (Fig. 11)
Mode3: Voice Data Code Count (Fig. 11)
Mode4: EQ Control – Band1 Gain
Mode0: 00h
Mode1: Tone Control – Bass Gain
Mode2: MP3 Frame Count (Fig. 11)
Mode3: Voice Data Code Count (Fig. 11)
Mode4: EQ Control –Band2 Gain
Mode0: 00h
10/37
SAMSUNG Electronics Co.
TL7231MD
1Bh
HDO11
1Ch
HDO12
1Dh
HDO13
1Eh
HDO14
1Fh
HDO15
SAMSUNG Electronics CO.
Mode1: Tone Control – Treble Cutoff Frequency
Mode2: The most recently synchronized frame header of
MP3 bit stream. (Fig. 12)
Mode3: 00h
Mode4: EQ Control – Band3 Gain
Mode0: 00h
Mode1: Tone Control – Treble Gain
Mode2: The most recently synchronized frame header of
MP3 bit stream. (Fig. 13)
Mode3: 00h
Mode4: EQ Control – Band4 Gain
Mode0: 00h
Mode1: 00h
Mode2: The most recently synchronized frame header of
MP3 bit stream. (Fig. 14)
Mode3: 00h
Mode4: EQ Control – Band5 Gain
Mode0: 00h
Mode1: 00h
Mode2: Bass Boost Information (Fig. 15)
Mode3: 00h
Mode4: EQ Control – Band6 Gain
Mode0: 00h
Mode1: 00h
Mode2: DAC Output Valid (Fig. 16)
Mode3: 00h
Mode4: 00h
Mode0: 00h
Mode1: 00h
Mode2: CRC Error Count
Mode3: 00h
Mode4: 00h
11/37
TL7231MD
Table 6. Host Interface Port Commands
COMM
AND
PARAME
TER
00h
01h
04h
05h
06h
07h
08h
09h
0Dh
0Fh
None
None
None
None
None
None
None
None
None
None
Stop
MP3 Decoding
Voice Encoding
Voice Decoding
Voice Encoding
Voice Decoding
Voice Encoding
Voice Decoding
Revision Code
Sleep
10h
None
Mute ON
11h
12h
None
None
Mute OFF
Internal ADC
14h
None
Internal DAC
15h
None
External DAC
16h
1byte
External DAC
Format
17h
None
MSB First
18h
19h
None
1byte
LSB First
Report Format
MEANING
DESCRIPTION
Stop execution and go into WAIT state.
Execute MP3 decoding.
Execute voice encoding (16Kbps).
Execute voice decoding (16Kbps).
Execute voice encoding (24Kbps).
Execute voice decoding (24Kbps).
Execute voice encoding (32Kbps).
Execute voice decoding (32Kbps).
Report the TL7231MD revision number in HDO0.
Go into SLEEP state. This command should be used in
WAIT state. If this command is used during algorithm
execution, TL7231MD becomes unstable.
When using internal DAC, The output voltage level of
AOUTL/AOUTR is GND. When using external DAC,
DACMUTE# becomes active. After reset, TL7231MD is
set to be mute on.
Mute is disabled.
Use Internal ADC. External ADC interfaces are disabled.
After reset, it is the default value.
Use internal DAC. After reset, it is set to use internal
DAC.
Use external DAC. Internal DAC is disabled. The
waveform of I/O pin related to external DAC is controlled
according to External DAC Format or External DAC
Format 2.
Set the waveform of I/O pin related to external DAC. The
parameter value of External DAC Format command
should be as follows: {0, 0, 0, 0, 0, I2S, PL, PB}. For the
2
meaning of I S, PL, and PB, refer to Figure 8.
Serial Interface MSB-first mode. This is the default mode
after reset.
Serial Interface LSB-first mode
The reported contents of HDO6 to HDO15 are changed
according to parameter of this command.
Parameter
0
1
2
3
4
12/37
Reporting Contents
all 00h
Tone Control Information
MP3 Decoding Information
Voice Encoding/Decoding
Information
Equalizer Control Information
SAMSUNG Electronics Co.
TL7231MD
20h
1byte
Bass Boost
Control
(MP3 Only)
21h
1byte
Volume Control
22h
1byte
Prescale Control
23h
1byte
24h
1byte
25h
1byte
Tone Control –
Bass Gain
(MP3 Only)
Tone Control –
Treble Gain
(MP3 Only)
Tone Control –
Bass Cutoff
(MP3 Only)
26h
1byte
Tone Control –
Treble Cutoff
(MP3 Only)
27h
none
28h
none
30h
none
Tone Control –
Enable
(MP3 Only)
Tone Control –
Disable
(MP3 Only)
MP3 CRC Bypass
(MP3 Only)
SAMSUNG Electronics CO.
Control Bass boost. The upper nibble of the parameter
controls the cutoff frequency of bass boost, and the lower
nibble controls the level of bass boost. The value of
upper nibble should be in the range of 0 to 6. The cutoff
frequency is
25 × upper nibble + 50 (Hz).
If the values of the lower nibble is in the range of 0 to 12,
the low frequency band below the cutoff frequency is
boosted by 0dB ~ 18dB (1.5dB step). The other values
mean no boost. For example, if the parameter value is
42h, then the cutoff frequency will be 25×4+50=150Hz,
and the frequency band below 150Hz will be boosted by
3dB compared to the upper frequency band. In case of
using bass boost, volume is reduced by 1.5 × n dB where
n means the parameter value. The reset value is
FFh(disabled).
Control volume. The parameter should have the value of
range from 0 to 255. If the value is n, the volume is
attenuated by n/2 dB compared to maximum volume. The
reset value is 0.
Control the prescaling. The parameter is a signed value
and can be -128 to 127. The prescaling is done by 0.5 ×
n dB according to parameter value n. That is, 0h ~ 7Fh
means 0dB ~ 63.5dB scaling, 80h ~ FFh means –64dB ~
-0.5dB scaling. The reset value is 0dB.
Control the Bass Gain. The parameter is a signed value
and can be -128 to 127. The gain can be 0.5 × n dB
according to parameter value n. The reset value is 0.
Control the Treble Gain. The parameter is a signed value
and can be -128 to 127. The gain can be 0.5 × n dB
according to parameter value n. The reset value is 0.
Control the Bass Cutoff Frequency. The parameter can
have the value of 0 to 255. The cutoff frequency can be
20 + 5 × n Hz according to parameter value n. The reset
value is 0.
Control the Treble Cutoff Frequency. The parameter can
have the value of 0 to 255. The cutoff frequency can be
5000 + 20 × n Hz according to parameter value n. The
reset value is 0.
Enable the Tone Control Function. Tone Control Function
is disabled when reset.
Disable the Tone Control Function. Tone Control Function
is disabled when reset.
During MP3 decoding, even if the input bit stream
contains the CRC field, TL7231MD doesn’t check the
CRC error. After reset, TL7231MD is set to check CRC
error.
13/37
TL7231MD
31h
none
MP3 CRC Check
40h
1byte
EQ Control –
Band1 Gain
(MP3 Only)
41h
1byte
EQ Control –
Band2 Gain
(MP3 Only)
42h
1byte
EQ Control –
Band3 Gain
(MP3 Only)
43h
1byte
EQ Control –
Band4 Gain
(MP3 Only)
44h
1byte
EQ Control –
Band5 Gain
(MP3 Only)
45h
1byte
EQ Control –
Band6 Gain
(MP3 Only)
46h
none
47h
none
8xh
None
EQ Control –
Enable
(MP3 Only)
EQ Control –
Disable
(MP3 Only)
External DAC
Format2
14/37
During MP3 decoding, if the input bit stream contains the
CRC field, check the CRC error. If an error occurs,
TL7231MD outputs 0 during the period of corresponding
MP3 frame. The reset value is MP3 CRC check.
Control the gain of Band1(<30Hz) of 6-band equalizer.
The parameter is a signed value and can be -128 to 127.
The gain can be 0.5 × n dB according to parameter value
n. The reset value is 0dB.
Control the gain of Band2(30Hz~125Hz) of 6-band
equalizer. The parameter is a signed value and can be 128 to 127. The gain can be 0.5 × n dB according to
parameter value n. The reset value is 0dB.
Control the gain of Band3(125Hz~500Hz) of 6-band
equalizer. The parameter is a signed value and can be 128 to 127. The gain can be 0.5 × n dB according to
parameter value n. The reset value is 0dB.
Control the gain of Band4(500Hz~2KHz) of 6-band
equalizer. The parameter is a signed value and can be 128 to 127. The gain can be 0.5 × n dB according to
parameter value n. The reset value is 0dB.
Control the gain of Band5(2KHz~8KHz) of 6-band
equalizer. The parameter is a signed value and can be 128 to 127. The gain can be 0.5 × n dB according to
parameter value n. The reset value is 0dB.
Control the gain of Band6(>8KHz) of 6-band equalizer.
The parameter is a signed value and can be -128 to 127.
The gain can be 0.5 × n dB according to parameter value
n. The reset value is 0dB.
Enable the Equalizer Function. The equalizer function is
disabled after reset.
Disable the Equalizer Function. The equalizer function is
disabled after reset.
Same as External DAC Format command. Parameter
values are located at lower nibble of the command. The
command should be the form of {1, 0, 0, 0, 0, I2S, PL,
PB}.
SAMSUNG Electronics Co.
TL7231MD
Bass boost control command(20h) is another form of tone control command(23h ~28h). It is
implemented by using the same filter as tone control command. Thus, if bass boost control
command is received with valid parameter value, gains and cutoffs are changed as follows;
l
l
l
l
Bass gain and cutoff frequency of tone control are changed according to the parameter
value.
Treble gain is changed to 0.
Prescaling is set to –12dB to remove clipping noise.
Tone control is enabled.
If bass boost command is received with invalid parameter value, the gains and cutoff
frequencies are not changed, and tone control is disabled. If a command related to tone control
is received, only the related gain or cutoff frequency is changed, and the command has no
effect on the tone control enable/disable and prescaling, and the information of bass boost
which is reported through HDO13 is not changed. For the tone control enable command(27h), it
just enables the tone control function, and has no effect on the gains and cutoff frequencies.
Tone control disable command(28h) disable tone control function, and change the bass boost
status which is reported through HDO13 to FFh(disable).
Prescaling has effect when tone control or equalizer is enabled or bass boost command is
received.
Equalizer consists of 6 bands, and band1 and band6 are shelving type, band2 to band5 are
peaking type. Since each band has relatively small Q value, correction matrix is automatically
used to complement this small Q value whenever attenuation value is set by using EQ gain
control commands(40h ~ 45h). It is not recommended that gain difference of neighbor bands
exceeds 10dB.
SAMSUNG Electronics CO.
15/37
TL7231MD
7
6
5
4
Reserved
3
2
1
0
S3
S2
S1
S0
Bit
Bit
Number Mnemonic
Function
3
S3
When set, it means that host wrote parameter to HDI3
register, but it isn’ t read by TL7231MD.
2
S2
When set, it means that host wrote parameter to HDI2
register, but it isn’ t read by TL7231MD.
1
S1
When set, it means that host wrote command ID to HDI1
register, but it isn’ t read by TL7231MD.
0
S0
When set, it means that host wrote command to HDI0
register, but it isn’ t read by TL7231MD.
Figure 4. HDI Status Reported through HSR4
7
6
5
4
3
2
1
0
ID
Bit
Bit
Number Mnemonic
7:0
ID
Function
Serial ID Number
Figure 5. Command ID reported through HDO0
16/37
SAMSUNG Electronics Co.
TL7231MD
7
6
5
4
3
2
1
0
STATE
Bit
Bit
Number Mnemonic
7:0
STATE
Function
TL7231MD Status Report
00h: WAIT State
01h: MP3 Decoding
04h: Voice Encoding (16Kbps)
05h: Voice Decoding (16Kbps)
06h: Voice Encoding (24Kbps)
07h: Voice Decoding (24Kbps)
08h: Voice Encoding (32Kbps)
09h: Voice Decoding (32Kbps)
Figure 6. TL7231MD Status reported through HDO1
SAMSUNG Electronics CO.
17/37
TL7231MD
7
6
5
4
Reserved
3
2
DE
MU#
Bit
Bit
Number Mnemonic
3
DE
1
0
SF
Function
Deemphasis Enable:
When set, deemphasis is enabled. Reset value is 0.
2
MU#
Mute Enable:
When cleared, mute is on. Reset value is 0.
1:0
FS
Sampling Frequency:
During MP3/voice decoding, it shows the sampling
frequency of bit stream. DACLRCK is set as follows:
00: 44.1KHz
01: 48KHz
10: 32KHz
11: not used
During voice encoding, it shows the sampling frequency
of bit stream. ADCADEN# is set as follows:
00: not used
01: not used
10: not used
11: 8KHz
Reset value is 00.
Figure 7. I/O Status reported through HDO2
18/37
SAMSUNG Electronics Co.
TL7231MD
7
6
5
Reserved
4
3
2
1
0
I2S
PL
PB
EDAC
EADC
Bit
Bit
Number Mnemonic
4
Function
I2S Format Enable:
I2S
When set, I2S format (1 bit delay), When cleared normal
PCM format. Reset value is 0.
3
PL
Polarity of DACLRCK:
When cleared, left channel data is sent through
DACSDATA during LRCK=0. When set, right channel
data is sent through DACSDATA during LRCK=0. Reset
value is 0. (Refer Figure17.)
4
PB
Polarity of DACBCK:
When cleared, DACSDATA has valid data between falling
edges of DACBCK. When set, DACSDATA has valid data
between rising edges of DACBCK. (Refer Figure17.)
Reset value is 0.
1
EDAC
External DAC Enable:
When set, external DAC is used. Reset value is 0.
0
EADC
External ADC Enable:
When set, external ADC is used. Reset value is 0.
Figure 8. I/O Status reported through HDO3
7
6
5
4
3
2
1
0
Volume
Bit
Bit
Number Mnemonic
7:0
Volume
Function
The value can be 0 to 200.
Figure 9. Volume reported through HDO4
SAMSUNG Electronics CO.
19/37
TL7231MD
7
6
5
4
3
2
1
0
Mode
Bit
Bit
Number Mnemonic
0
Mode
Function
Serial Interface Mode.
When set, LSB-first mode. When cleared, MSB-first
mode. The reset value is 0.
Figure 10. Serial Interface Mode reported through HDO5
7
6
5
4
3
2
1
0
HDO9
HDO8
HDO7
HDO6
Bit
Number
HDO9 7:0
HDO8 7:0
HDO7 7:0
HDO6 7:0
Bit
Mnemonic
Function
These registers show 32-bit unsigned integer value.
HDO9 is the most-significant byte. When mode is 2, it
represents the successfully decoded frame counter
during MP3 decoding. When mode is 3, it represents the
encoded/decoded code count during voice
encoding/decoding.
Figure 11. Count Value reported through HDO6 ~ HDO9
20/37
SAMSUNG Electronics Co.
TL7231MD
7
6
5
4
Reserved
3
ID
Bit
Bit
Number Mnemonic
3
2:1
ID
LAYER
2
1
LAYER
0
PT
Function
0: Reserved
1: ISO/IEC standard 11172-3 audio (MP3)
00: Reserved
01: Layer3
10: Layer2
11: Layer1
TL7231MD decodes only layer3 bit stream.
0
PT
Protection Bit:
0: CRC Protection
1: No CRC Protection
Figure 12. Frame Header reported through HDO10 when mode is 2.
SAMSUNG Electronics CO.
21/37
TL7231MD
7
6
5
4
3
BRI
SF
Bit
Bit
Number Mnemonic
7:4
BRI
2
1
0
PD
PR
Function
Bit Rate Index:
0000: Free
0001: 32Kbps
0010: 40Kbps
0011: 48Kbps
0100: 56Kbps
0101: 64Kbps
0110: 80Kbps
0111: 96Kbps
1000: 112Kbps
1001: 128Kbps
1010: 160Kbps
1011: 192Kbps
1100: 224Kbps
1101: 256Kbps
1110: 320Kbps
1111: Forbidden
3:2
SF
Sampling Frequency:
00: 44.1KHz
01: 48KHz
10: 32KHz
11: Reserved
1
PD
Padding Bit
0: No Padding Bit
1: One Padding Bit
0
PR
Private Bit
Bit for private use.
Figure 13. Frame Header reported through HDO11 when mode is 2.
22/37
SAMSUNG Electronics Co.
TL7231MD
7
6
MODE
5
4
ME
3
2
CR
OC
Bit
Bit
Number Mnemonic
7:6
MODE
1
0
EM
Function
Audio Channel Mode:
00: Stereo
01: Joint Stereo (Intensity Stereo and/or MS Stereo)
10: Dual Channel
11: Single Channel
5:4
ME
Joint Stereo Coding Method:
00: Neither Intensity Stereo nor MS Stereo
01: Only Intensity Stereo
10: Only MS Stereo
11: Both Intensity Stereo and MS Stereo
3
CR
Copyright:
0: No Copyright
1: Copyright Protected
2
OC
Original/Copy:
0: Copy
1: Original
1:0
EM
Type of Deemphasis:
00: None
01: 50/15 microseconds
10: Reserved
11: CCITT J.17
DACDEEM of TL7231MD becomes active if deemphasis
is needed without relation to deemphasis type.
Figure 14. Frame Header reported through HDO12 when mode is 2.
SAMSUNG Electronics CO.
23/37
TL7231MD
7
6
5
4
3
2
CF
CF
0
BB
Bit
Bit
Number Mnemonic
7:4
1
Function
Cutoff Frequency:
The value can be in the range of 0 to 6.
3:0
BB
Base Boost Value
Figure 15. Bass Boost Information reported through HDO13 when mode is 2.
7
6
5
4
3
2
1
0
Valid
Bit
Bit
Number Mnemonic
0
Valid
Function
DAC Output Valid:
When set, output of internal DAC is valid. Reset value is
0.
Figure 16. DAC Output Status reported through HDO14
24/37
SAMSUNG Electronics Co.
TL7231MD
DAC
DAC of TL7231MD employs the 1-bit 4th-order sigma-delta architecture with 16-bit resolution,
over-sampling of 64X. Analog post-filter with low clock sensitivity and linear phase can filter out
the shaping-noise and output analog voltage with high resolution. The characteristic of Internal
DAC is shown Table 7.
Table 7. Characteristics of Internal DAC
PARAMETER
Resolution
SNR
THD
SNDR
Reference Voltage Output
(DACVREF)
Frequency Response
Analog Output
Voltage Range
MIN
Load Impedance
Digital Filter
Pass Band Ripple
Stop and Attenuation
Pass Band
10K
TYP
16
79.7
84.9
78.5
0.5×
DACVDDA
± 0.1
0.5×
DACVDDA
MAX
UNITS
bits
dB
dB
dB
V
± 0.5
dB
Vpp
Ω
± 0.0072
62.7
0.45
dB
dB
Fs
(DACVDDD/DACVDDA=3.0V, Temp=25°C, Fs=44.1KHz, Signal Freq.=20~20KHz, Cload of AOUTL/AOUTR = 10pF)
With TL7231MD, user can configure whether the internal DAC is used or not. The configuration
of DAC can be achieved through HIP commands shown in Table 5. When using internal DAC,
the following circuit in Figure 17 is recommended.
SAMSUNG Electronics CO.
25/37
TL7231MD
3.0V
10u
0.1u
DACVDDA
DACVSSA
DACVBB
1u
AOUTR
Low Pass
Filter
(optional)
Rout
Low Pass
Filter
(optional)
Lout
100K
1u
AOUTL
TL7231MD
100K
DACVREF
10u
0.1 u
10u
0.1 u
DACVHALF
DACVDDD
3.0V
DACVSSD
0.1u
10u
Figure 17. Reference Circuit when using internal DAC
26/37
SAMSUNG Electronics Co.
TL7231MD
External DAC Interfaces
TL7231MD supports eight external interface formats. Three of them, for example, are shown in
Figure 18. The interface can be configured through HIP commands. The frequency of
DACBCLK is 32 times of that of DACLRCK. When voice decoding, only 32KHz of DACLRCK
is used.
Left Channel
Right Channel
DACLRCK
DACBCK
DACSDATA
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
LSB+1
LSB
LSB+2
LSB+1
Right-Justified Mode
(EDAC: 1, PB: 0, PL: 0, I2S: 0)
Left Channel
Right Channel
DACLRCK
DACBCK
DACSDATA
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
Right-Justified Mode
(EDAC: 1, PB: 1, PL: 1, I2S: 0)
Left Channel
Right Channel
DACLRCK
DACBCK
DACSDATA
MSB
MSB-1
LSB+2
LSB+1
LSB
MSB
MSB-1
LSB
I2S-Justified Mode
(EDAC: 1, PB: 0, PL: 0, I2S: 1)
Figure 18. Examples of External DAC Interfaces
SAMSUNG Electronics CO.
27/37
TL7231MD
ADC
The internal ADC of TL7231MD is 12-bit resolution ADC. It is recycling type ADC with sampleand-hold function. The analog input ADCAIN should be single-ended type with the range from
ADCREFP to ADCREFN. This ADCAIN voltage follows reference voltage range fundamentally.
So, if user wants to alter the input range, the voltage value of ADCREFP should be changed.
But ADCREFP should be greater than 2.0V. The characteristic of internal ADC is shown Table 8.
Table 8. Characteristics of Internal ADC
PARAMETER
MIN
TYP
74.3
64.9
64.4
THD
SNR
SNDR
MAX
UNITS
dB
dB
dB
(ADCVDDD/ADCVDDA=3.0V, ADCAIN=8KHz)
3.0V
10u
0.1u
ADCVDDA
ADCVSSA
ADCVBB
ADCREFP
ADCAIN
ADCREFP/2
ADCREFN
Vref
TL7231MD
ADCREFP
10u
0.1u
ADCREFN
ADCVDDD
3.0V
ADCVSSD
0.1u
10u
Figure 19. Reference Circuit when using internal ADC
With TL7231MD, the following circuit in Figure 19 is recommended to use internal ADC.
28/37
SAMSUNG Electronics Co.
TL7231MD
Voice Record/Playback Function
TL7231MD records voice data from ADC in 8kHz sampling rate. There are three compression
modes according to bit rates of compressed data: high quality (32Kbps), medium quality
(24Kbps) and low quality (16Kbps). In high quality mode, relatively large bits are allocated for
compressed data to achieve high quality of the sound. In low quality mode, smaller bits are
allocated to record much more samples in the same size of storage media. Medium quality
mode gives tradeoff between high and low quality modes. Compressed codes are byte-aligned
and transmitted to host MCU through the serial port.
In playback the codes are uncompressed to PCM samples, with the compression mode in
recording, and then oversampled to 32 kHz and output to DAC. Compressed codes are
transmitted from host MCU through the serial interface.
Table 9 is the summary of the relation between compression modes and code size.
Table 9. Summary of Three Voice Compression Modes
RECORDING TIME
COMPRESSION MODES CODE LENGTH
FOR 32MB STORAGE MEDIA
(BIT)
High Quality
(32Kbps)
4
140 min.
Medium Quality (24Kbps)
3
186 min.
Low Quality
(16Kbps)
2
280 min.
SAMSUNG Electronics CO.
29/37
TL7231MD
Lower Power Operation
TL7231MD has low-power feature that makes the processor get into very low-power dormant
states through hardware or software control. The power saving scheme is explained with the
state diagram of TL7231MD shown in Figure 20.
RUN
In this state, TL7231MD decodes MP3 or compressed voice bit stream, or encodes voice signal.
Also in this state it can process other HIP commands such as 20h and 21h. HIP command 01h,
04h through 09h, and 0Fh should not be used in this state. TL7231MD consumes normal power
at this state, It processes all internal functions and drives external pads. It can transit to WAIT
state with HIP command 00h. When there is no job left or it waits available data, power
consumption is reduced as that of WAIT state.
WAIT
When RESET signal becomes active, TL7231MD goes into WAIT state. There it can transit to
RUN, or SLEEP state. When TL7231MD is in this state, it is ready to receive any HIP
commands from host. It can go into RUN state when it receives HIP commands such as 01h,
04h though 09h. Also it can process other HIP commands such as volume control (21h) etc. in
this state. TL7231MD goes into this state through HIP command 00h from RUN state. When
TL7231MD is in this state, only peripheral interface block consumes power. That is, internally
generated peripheral clock is active but clock for the DSP core logic is not. When it receives HIP
command 0Fh, it goes into SLEEP state in which more power is saved.
SLEEP
In SLEEP state, only internal analog blocks such as PLL, ADC and DAC of TL7231MD
consume power. In this state, internal ADC and DAC are disabled. But PLL consumes normal
operation power. In this state, TL7231MD can transit to PWRDOWN state when external
PWRDN pin becomes active. Active WAKEUP signal changes its state from SLEEP to WAIT.
PWRDOWN
When TL7231MD is in SLEEP state and PWRDN signal becomes active, it transits to
PWRDOWN. To make TL7231MD stay in this state, the external PWRDN signal keep its active
state. When the PWRDN signal becomes inactive, TL7231MD exits from this PWRDOWN state,
and then goes into SLEEP state. When it changes its state from PWRDOWN to SLEEP, this
state should not be changed during minimum 150µs until internal PLL is stabilized. TL7231MD
consumes the minimum power at this state because all internal logic blocks and analog blocks
are power-downed.
30/37
SAMSUNG Electronics Co.
TL7231MD
HIP COMMAND
HIP COMMAND
(00h)
RUN
HIP COMMAND
(0Fh)
WAIT
PWRDN PIN
PWRDOWN
SLEEP
WAKEUP PIN
PWRDN PIN
RESET
Figure 20. Decoder States and Power Management
SAMSUNG Electronics CO.
31/37
TL7231MD
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (See Notes)†
Symbol
VDD
VIN
IIN
TSTG
Parameter
DC Supply Voltage
DC Input Voltage
DC Input Current
Storage Temperature
Rating
-0.3 to 3.8
-0.3 to 5.5
±10
-40 to 125
Unit
V
V
mA
°C
† Stresses beyond those listed under “ absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “ DC ELECTRICAL CHARACTERISTICS” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1:
NOTE 2:
All voltage values are with respect to VSS.
This value was obtained under specially produced worst-case test conditions for the TL7231MD, which are
not sustained during normal device operation.
DC ELECTRICAL CHARACTERISTICS (Note3)†
Symbol
VDD
VSS
VIH
VIL
VOH
VOL
IIH
IIL
IRN
IWT
ISL
IPD
CIN
COUT
TA
VCPUXI
Parameter
Supply voltage
Supply voltage
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level input leakage current
without internal pull-up
Low level input leakage current
without internal pull-up
Supply current in RUN state
Supply current in WAIT state
Supply current in SLEEP
Supply current in PWRDOWN
state
Input capacitance
Output capacitance
Air temperature
High level input voltage for CPUXI
MIN
2.7
0.4
UNIT
V
V
V
V
V
V
-10
+10
µA
-10
+10
µA
1.8
-0.3
2
TYP
3.0
0
MAX
3.3
VDD +0.3
0.6
61
26
12
mA
mA
mA
250
µA
-40
2.5
4
4
85
VDD +0.3
pF
pF
°C
V
† For TL7231MD, all typical values are at VDD = 3.0 V, TA (air temperature) = 25°C.
NOTE 3: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can
be driven by CMOS clock.
NOTICE: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice.
32/37
SAMSUNG Electronics Co.
TL7231MD
AC ELECTRICAL CHARACTERISTICS
AC Test Condition
Parameter
Value
Temperature
85°C
Supply Voltage
3.0V
Input Rise and Fall Times
2ns
Output Load
10pF
Serial port
The following table defines the timing parameters for the serial port pins. The numbers shown in
Figure 21 correspond to each number in the first column of the table.
NO.
Symbol
Description
MIN
MAX
Unit
1
TCC
Cycle time of CLKXRM
144.7
ns
2
TD
Delay time, CLKXRM to DXRM valid
42.2
3
TSU
Setup time, DXRM before CLKXRM low
1.9
ns
4
TH
Hold time, DXRM from CLKXRM low
1.2
ns
5
TREQ
Request check time, falling edge of CLKXRM
to falling edge of REQSTRM
78.4
295.2
331.3
ns
ns
1
CLKXRM
2
DXRM
(Transmit)
DXRM
(Receive)
Bit0
Bit0
3
Bit1
Bit1
Bit2
Bit2
Bit3
Bit3
Bit4
Bit4
Bit5
Bit5
Bit6
Bit6
Bit7
Bit7
4
5
REQSTRM
Figure 21. Timing for Serial Port in case of LSB-First Mode
SAMSUNG Electronics CO.
33/37
TL7231MD
Host interface Port
The following table defines the timing parameters for the Host Interface Port I/O pins. The
numbers shown in Figure 22 correspond to each number in the first column of the table.
NO.
Symbol
Description
MIN
MAX
Unit
6
THAW
HALE pulse width
2.0
ns
7
THDSU
Setup time, HD address setup before HALE low
2.0
ns
8
THDH
Hold time, HD address hold after HALE low
0.8
ns
9
THAS
Start of write or read after HALE low
0.0
ns
10
THDSU
Setup time, HD data setup before end of write
0.7
ns
11
THDH
Hold time, HD data hold after end of write
2.2
ns
12
THRW
Read or write pulse width
36.2
ns
13
THDE
HD data enabled after start of read
7.8
ns
14
THDD
HD data valid after start of read
7.9
ns
15
THRDH
HD data hold after end of read
3.7
7.8
ns
16
THRDD
HD data disabled after end of read
4.2
7.9
ns
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TL7231MD
HALE
6
12
HSEL#
9
HWR#
7
HD[7:0]
8
ADDRESS
DATA
10
11
HOST Write Cycle
HALE
5
12
HSEL#
9
HRD#
7
HD[7:0]
8
15
13
ADDRESS
DATA
14
16
HOST Read Cycle
Figure 22. Timing for Host Interface Port pins
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TL7231MD
PACKAGE DIMENSION
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TL7231MD
The reproduction of this datasheet is NOT allowed without approval of SEC.
All information and data contained in this datasheet are subject to change without notice. This
publication supersedes and replaces all information previously supplied. SEC has no
responsibility to the consequence of using the patents described in this document.
©1999 SAMSUNG Electronics Co., – All Rights Reserved
SAMSUNG Electronics CO.
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