Ordering number: EN 5482A Monolithic Linear IC LA9240M Analog Signal Processor (ASP) for CD players Package Dimensions Overview The LA9240M is an analog signal processing and servo control bipolar IC designed for use in compact disc players; a compact disc player can be configured by combining this IC with a CD-DSP such as the LC78622E and LC78620E, with a small number of additional components required. unit : mm 3159-QFP64E [LA9240M] Functions I/V amplifier, RF amplifier (with AGC), SLC, APC, FE, TE (with VCA and auto-balance function), focus servo amplifier (with offset cancellation function), tracking servo amplifier (with offset cancellation function), spindle servo amplifier (with gain switching function), sled servo amplifier (with off function), focus detection (DRF, FZD), track detection (HFL, TES), defect detection, and shock detection. Features SANYO : QIP64E . The following automatic adjustment functions are built in. . Focus offset auto cancel: FE (pin 20) . Tracking offset auto cancel: TE (pin 7) . EF balance auto adjustment . RF level AGC function . Tracking servo gain RF level following function . Focus search smoothing setting pin: FSC (pin 46) . EF balance adjustment variable range setting pin: TBC (pin . 47) Focus search mode switching pin: FSS (pin 55) Specifications Maximum Ratings at Ta = 25°C, Pins 22, 45 = GND Parameter Maximum supply voltage Allowable power dissipation Symbol VCC max Pd max Conditions Pin 56, 64 Ratings Unit 7 350 V mW Operating temperature Topr –25 to +75 °C Storage temperature Tstg –40 to +150 °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 83097HA(II)/83096HA(II) No.5482 - 1/20 LA9240M Operating Conditions at Pins 22, 45 = GND Parameter Symbol Recommended supply voltage Conditions Ratings VCC Operating supply voltage VCC op Unit 5 V 3.6 to 5.5 V * Operating Supply Voltage at Limit of Operating Temperature at Pins 22, 45 = GND Parameter Symbol Operating temperature Conditions Topr2 Operating supply voltage VCC op2 Set resistance R between DSP and CLK interface to 5.1 kΩ Ratings Unit –5 to +75 °C 3.4 to 5.5 V Operating Characteristics at Ta = 25°C, Pins 22, 45 = GND, VCC (pins 56, 64) = 5 V Parameter Current drain Reference voltage [Interface] CE-Vth CL-Vth DAT-Vth Maximum CL frequency [RF amplifier] RFSM no signal voltage Minimum gain [Focus amplifier] FDO gain FDO offset Off time offset Offset adjustment step F search voltage H1 F search voltage L1 F search voltage H2 F search voltage L2 [Tracking amplifier] TE gain MAX TE gain MIN TE−3 dB TO gain TGL offset TGH offset THLD offset Off 1 offset Off 2 offset Offset adjustment step Balance range H Balance range L TOFF-VTH TGL-VTH [PH] No signal voltage [BH] No signal voltage [DRF] Detection voltage Output voltage H Output voltage L Symbol ICCO VREF Conditions VCC1 (pin 64) + VCC2 (pin 56) VR CEvth CLvth DATvth CLmax CE CL DAT typ 32 2.5 max 42 2.7 0.8 0.8 0.8 FIN1, FIN2 : 1 MΩ-input, PH1 = 4 V freq = 200 kHz, RFSM Unit mA V V V V kHz 500 RFSMo RFSMGmin min 22 2.3 1.35 1.60 1.85 V –14.0 –12.5 –11.0 dB FDG FDost FDofost FEstep FSmax1 FSmin1 FSmax2 FSmin2 FIN2 : 1 MΩ-input, FDO Difference from reference voltage, servo on Difference from reference voltage, servo off FE FDO, FSS = GND FDO, FSS = GND FDO, FSS = VCC FDO, FSS = VCC 3.5 –170 –40 5.0 0 0 3 0.8 –0.8 0.8 0 6.5 +170 +40 dB mV mV mV V V V V TEGmax TEGmin TEfc TOG TGLost TGHost THLDost OFF1ost OFF2ost TEstep BAL-H BAL-L TOFFvth TGLvth f = 10 kHz, E: 1 MΩ-input, PH1 = 4 V f = 10 kHz, E: 1 MΩ-input, PH1 = 1 V E: 1 MΩ-input TH → TO gain, THLD mode Servo on, TGL = H, TO TGL = L, difference from TGL offset, TO THLD mode, difference from TGL offset, TO TOFF = H TOFF2 off (IF) TE ∆ Gain E/F input, TB = 5 V, TBC = open ∆ Gain E/F input, TB = 0 V, TBC = open 6.0 –0.5 9.0 +4.0 1.0 1.0 7.5 +1.8 60 6.0 0 0 0 0 0 30 3.5 –3.5 2.5 2.5 dB dB kHz dB mV mV mV mV mV mV dB dB V V 4.0 –250 –50 –50 –50 –50 8.0 +250 +50 +50 +50 +50 3.0 3.0 PHo Difference from RFSM –0.85 –0.65 –0.45 V BHo Difference from RFSM 0.45 0.65 0.85 V –0.60 4.5 –0.35 4.9 0 –0.20 V V V DRFvth DRF-H DRF-L Difference from VR at RFSM +0.5 Continued on next page. No.5482 - 2/20 LA9240M Continued from preceding page. Parameter [FZD] Detection voltage 1 Detection voltage 2 [HFL] Detection voltage Output voltage H Output voltage L [TES] Detection voltage LH Detection voltage HL Output voltage H Output voltage L [JP] Symbol FZD1 FZD2 Unit –0.4 4.9 0 –0.25 V +0.5 V –0.10 0.10 4.9 0 –0.05 0.15 +0.5 V V V V 0.35 0.5 0.65 V –0.65 –0.5 –0.35 V –40 –40 –30 0 0 0 +40 +40 +30 mV mV mV 0.75 1.0 1.25 V –1.25 –1.0 –0.75 V 0.35 0.5 0.65 V Difference from TO at SLEQ SLEQ = VR, Difference from VR Off mode SLOF –30 –100 –40 1.0 0 0 0 1.4 +30 +100 +40 2.0 mV mV mV V SLC 2.25 2.5 2.75 V SCIo SCIvthH SCIvthL SCI, difference from VR SCI, difference from VR SCI, difference from VR –40 60 –140 0 100 –100 +40 140 –60 mV mV mV DEFvth Difference between LF2 voltage when RFSM = 3.5 V and DEF is detected and LF2 voltage when RFSM = 3.5 V 0.20 0.35 0.50 V 4.5 4.9 0 +0.5 V V 180 4.3 210 4.6 mV V Difference from VR at RFSM TES-LH TES-HL TES-H TES-L TESI, difference from VR TESI, difference from VR JP-L SPD12ost SPD8ost SPDof Output voltage H12 SPD-H12 Output voltage L12 SPD-L12 Output voltage H8 SPD-H8 Output voltage H Output voltage L [APC] Reference voltage Off voltage max –0.55 4.5 HFLvth HFL-H HFL-L Output voltage L Detection voltage typ +0.2 0 JP-H [Sled amplifier] SLEQ offset Offset SLD Offset off Off VTH [SLC] No signal voltage [Shock] No signal voltage Detection voltage H Detection voltage L [DEF] FE, difference from VR FE, difference from VR min 0 Output voltage H [Spindle amplifier] Offset 12 Offset 8 Offset off Conditions SLEQost SLDost SLDof SLOFvth SLCo Difference from JP+ = 0 V, JP– = 0 V at JP+ = 0 V, JP– = 5 V, TO Difference from JP+ = 0 V, JP– = 0 V at JP+ = 5 V, JP– = 0 V, TO Difference from VR at SPD, 12 cm mode Difference from VR at SPD, 8 cm mode Difference from VR at SPD, OFF mode Difference from offset-12, 12 cm mode CV+ = 5 V, CV– = 0 V Difference from offset-12 , 12 cm mode CV+ = 0 V, CV– = 5 V Difference from offset-8, 8 cm mode CV+ = 5 V, CV– = 0 V DEF-H DEF-L LDS LDDof LDS voltage at which LDD = 3 V LDD –0.15 0.05 4.5 150 3.9 V V No.5482 - 3/20 LA9240M Pin Functions Pin No. 1 FIN2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 FIN1 E F TB TE− TE TESI SCI TH TA TD− TD JP TO FD FD− FA FA− FE FE− AGND SP SPI SPG SP− SPD SLEQ SLD SL− SL+ JP− JP+ TGL TOFF TES HFL 38 39 40 41 42 43 44 45 46 47 48 49 50 51 SLOF CV− CV+ RFSM RFS− SLC SLI DGND FSC TBC NC DEF CLK CL Symbol Contents Pickup photodiode connection pin. Added to FIN1 pin to generate the RF signal, subtracted from FIN1 pin to generate the FE signal. Pickup photodiode connection pin. Pickup photodiode connection pin. Subtracted from F pin to generate the TE signal. Pickup photodiode connection pin. TE signal DC component input pin. Pin which connects the TE signal gain setting resistor between this pin and TE pin. TE signal output pin. TES (Track Error Sense) comparator input pin. The TE signal is input through a bandpass filter. Shock detection input pin. Tracking gain time constant setting pin. TA amplifier output pin. Pin for configuring the tracking phase compensation constant between the TD and VR pins. Tracking phase compensation setting pin. Tracking jump signal (kick pulse) amplitude setting pin. Tracking control signal output pin. Focusing control signal output pin. Pin for configuring the focusing phase compensation constant between the FD and FA pins. Pin for configuring the focusing phase compensation constant between the FD− and FA− pins. Pin for configuring the focusing phase compensation constant between the FA and FE pins. FE signal output pin. Pin which connects the FE signal gain setting resistor between this pin and FE pin. Analog signal GND. CV+ and CV− pins input signal single-end output. Spindle amplifier input. 12-cm spindle mode gain setting resistor connection pin. Spindle phase compensation constant connection pin, along with the SPD pin. Spindle control signal output pin. Sled phase compensation constant connection pin. Sled control signal output pin. Input pin for sled movement signal from microprocessor. Input pin for sled movement signal from microprocessor. Input pin for tracking jump signal from DSP. Input pin for tracking jump signal from DSP. Input pin for tracking gain control signal from DSP. Gain is low when TGL is high. Input pin for tracking off control signal from DSP. Tracking servo is off when TOFF is high. Output pin for TES signal to DSP. The High Frequency Level is used to determine whether the main beam is positioned over a bit or over the mirrored surface. Sled servo off control input pin Input pin for CLV error signal from DSP. Input pin for CLV error signal from DSP. RF output pin. RF gain setting and EFM signal 3T compensation constant setting pin, along with the RFSM pin. Slice Level Control is an output pin that controls the data slice level used by the DSP for the RF waveform. Input pin used by DSP for controlling the data slice level. Digital system GND pin. Focus search smoothing capacitor output pin. Tracking balance control; EF balance adjustment variable range setting pin No connection Disc defect detection output pin. Reference clock input pin. 4.23 MHz signal from the DSP is input. Microprocessor command clock input pin. Continued on next page. No.5482 - 4/20 LA9240M Continued from preceding page. Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol DAT CE DRF FSS VCC2 REFI VR LF2 PH1 BH1 LDD LDS VCC1 Contents Microprocessor command data input pin. Microprocessor command chip enable input pin. RF level detection output (Detect RF). Focus search select; focus search mode (± search/+search vs. the reference voltage) switching pin Servo system and digital system VCC pin. By-pass capacitor connection pin for reference voltage. Reference voltage output pin. Disc defect detection time constant setting pin. RF signal peak hold capacitor connection pin. RF signal bottom hold capacitor connection pin. APC circuit output pin. APC circuit input pin. RF system VCC pin. No.5482 - 5/20 LA9240M Equivalent Circuit Block Diagram No.5482 - 6/20 LA9240M Test Circuit LA9240M No.5482 - 7/20 LA9240M Description of Operation 1. APC (auto laser power control) This circuit controls the pickup laser power. The laser is turned on and off by commands from the microprocessor. 2. RF amplifier (eye pattern output) The pickup photodiode output current (A + C) is input to FIN2 (pin 1), and (B + D) is input to FIN1 (pin 2). The current that is input is converted to the voltage, passes through the AGC circuit, and is then output from the RFSM amplifier output RFSM (pin 41). The internal AGC circuit has a variable range of ±3 dB, and the time constant can be changed through the external capacitor connected to PH1 (pin 60). In addition, this circuit also controls the bottom level of the EFM signal (RFSM output), and the response can be changed through the external capacitor connected to BH1 (pin 61). The center gain setting for the AGC variable range is set by the resistance between RFSM (pin 41) and RFS− (pin 42); if necessary, this resistance is also used for 3T compensation for the EFM signal. 3. SLC (slice level control) The SLC sets the duty ratio for the EFM signal that is input to the DSP to 50%. The DC level is determined by integrating the EFMO signal output from the DSP to determine the duty factor. 4. Focus servo The focus error signal is derived by detecting the difference between (A + C) and (B + D), which is (B + D) − (A + C), and is then output from FE (pin 20). The focus error signal gain is set by the resistance between FE (pin 20) and FE− (pin 21). Offset cancellation is performed by the FE amplifier. ‘‘Offset cancellation’’ cancels the offset for the IC’s internal IV amplifier, etc. Adjustment is initiated by the FOCUS-OFFSET ADJUST START command, and terminates after about 30 ms. The FOCUS-OFFSET ADJUST OFF command is used to return to the state before offset cancellation. The FA amplifier is the pickup phase compensation amplifier, and the equalizer curve is set by the external capacitor and resistance. Furthermore, this amplifier has a mute function which is applied when VCC is turned on, when the F-SERVO OFF command is sent, and during F-SEARCH. In order to turn the focus servo on, send either the LASER ON command or the F-SERVO ON command. The FD amplifier has a phase compensation circuit, and a focus search signal composition function and is completed in about 560 ms. Focus search is initiated by the F-SEARCH command, and a ramp waveform is generated by the internal clock. This waveform is used for focus detection (focus zero cross) with the focus error signal and then turn the focus servo on. The ramp waveform amplitude is set by the resistance between FD (pin 16) and FD− (pin 17). FSC (pin 46) is for smoothing the focus search ramp waveforms, and a capacitor is connected between FSC and REF. FSS (pin 55) is the focus search mode switching pin. If FSS is shorted with VCC, the ‘‘+ search’’ is set; if FSS is left open or is shorted with GND, the ‘‘± search’’ is set. 5. Tracking servo The pickup photodiode output current is input to E (pin 3) and F (pin 4). The current that is input is converted to the voltage, passes through the balance adjustment VCA circuit and then the VCA circuit that follows the gain in the RFAGC circuit, and is then output from TE (pin 7). The tracking error gain is set by the resistance between TE− (pin6) and TE (pin7). Offset cancellation is performed by the TE amplifier. Offset cancellation terminates after about 30 ms. The TRACK-OFFSET ADJUST OFF command is used to return to the state before the offset. The TH amplifier alters the servo response characteristics according to the THLD signal, etc., generated internally after detection of the TGL signal from the DSP or the JP signal. When a defect is detected, the THLD mode goes into effect internally. To avoid this, short DEF (pin 49) to L = GND. By inserting an external bandpass filter to remove the shock component from the tracking error signal at SCI (pin 9), the gain is automatically boosted when a defect is detected. The TA output (pin 11) has a built-in resistance to allow configuration of a low-pass filter. The TD amplifier performs servo loop phase compensation; the characteristics are set by external CR. Furthermore, this amplifier has a mute function, which is applied when VCC is turned on or the TRACK-SERVO OFF command is issued. The muting function is released by the TRACK-SERVO ON command. The TOFF amplifier that is positioned immediately after TD (pin 13) functions to turn off the servo in response to the TOFF signal from the DSP. The TO amplifier has a JP pulse composition function. The JP pulse is set by JP (pin 14). (THLD detection is performed internally.) 6. Sled servo The response characteristics are set by SLEQ (pin 28). The amplifier positioned after SLEQ (pin 28) has a mute function that is applied either when SLOF (pin 38) goes high or the SLED OFF command is issued. The sled is moved by inputting current to SL− (pin 30) and SL+ (pin 31); specifically, the pins are connected to the microprocessor output ports via resistors, and the movement gain is set by the resistance value of that resistor. It is important to note that if there is a deviation in the resistance values for SL− (pin 30) and SL+ (pin 31), an offset will arise in the SLD output. 7. Spindle servo This configures the servo circuit, which maintains the linear velocity of the disc at a constant speed, along with the DSP. This circuit accepts signals from the DSP through CV− (pin 39) and CV+ (pin 40) and sets the equalizer characteristics through SP (pin 23), SP− (pin 26), and SPD (pin 27), which are output to SPD (pin 27). The 12-cm mode amplifier gain is set by the resistor connected between SPG (pin 25) and the reference voltage. In 8-cm mode, this amplifier serves as an internal buffer, and SPG (pin 25) is ignored. Note that the gain setting is made for 8-cm mode first, and then 12-cm mode. If SPG (pin 25) is left open, the gain is forcibly set for 8-cm mode, regardless of whether 8-cm or 12-cm mode is in effect. No.5482 - 8/20 LA9240M 8. TES and HFL (traverse signals) When moving the pickup from the outer track to the inner track, the EF output from the pickup must be connected so that the phase relationship of TES and HFL is as shown in the diagram below. For the TESI input, the TES comparator has negative polarity and hysteresis of approximately ±100 mV. An external bandpass filter is needed in order to extract only the required signal from the TE signal. 9. DRF (luminous energy determination) DRF goes high when the peak of the EFM signal (RFSM output) held by the PH1 (pin 60) capacitor exceeds approximately 2.1 V. The PH1 (pin 60) capacitor affects the DRF detection time constant and the RFAGC response bidirectional setting. The DRF output is driven by a constant current (250 µA). Pickup position Focus 10. Focus determination Focus is assumed to be obtained when the focus error signal S curve reaching REF + 0.2 V is detected, and the S curve subsequently returns to REF. Focus No.5482 - 9/20 LA9240M 11. DEFECT The mirrored surface level is maintained by the capacitor for LF2 (pin 59); when a drop in the EFM signal (RFSM output) reaches 0.35 V or more, a high signal is output to DEF (pin 49). If DEF (pin 49) goes high, the tracking servo enters THLD mode. In order to prevent the tracking servo from entering THLD mode when a defect is detected, prevent DEFECT from being output by either shorting DEF (pin 49) to GND, or shorting LF2 (pin 59) to GND. The DEFECT output is driven by constant current (approximately 100 µA). EFM signal (RFSM output) LF2 (pin 59) DEF (pin 49) 12. Microprocessor interface Because the Reset (Nothing) command initializes the LA9240M, it must be used carefully. The LA9240M command acceptance (mode switching) timing is defined by the internal clock (4.23 MHz divided to 130 kHz) after the falling edge of CE (RWC); therefore, when commands are sent consecutively, CE must go low for at least 10 µsec. The 4.23 MHz clock is required for that reason. 2BYTE-COMMAND DETECT and 2BYTE-COMMAND RESET are used only for the purpose of masking two-byte data. All instructions can be input by setting CE high and sending commands synchronized with the CL clock from the microprocessor to DAT (pin 52) in LSB first format. Note that the command is executed at the falling edge of CE. Timing * The DSP pin names are shown in parentheses. 13. Reset circuit The power-on reset is released when VCC exceeds approximately 2.8 V. 14. Pattern design notes To prevent signal jump-in from CV+ (pin 40) to RFSM (pin 41), a shielding line is necessary in between. 15. VCC /REF/GND/NC VCC1 (pin 64) VCC2 (pin 56) AGND (pin 22) DGND (pin 45) NC (pin 48) VR (Pin 58) : : : : : : RF system SERVO system, DIGITAL system RF system, SERVO system DIGITAL system No connection Reference voltage No.5482 - 10/20 LA9240M Microprocessor Command List COMMAND MSB Reset mode Power-on mode LSB DSP 00000000 RESET RESET(NOTHING) 00001000 FOCUS START FOCUS START #1 11110000 11111000 11111111 2BYTE-COMMAND DETECT 2BYTE-COMMAND DETECT 2BYTE-COMMAND RESET 2BYTE-COMMAND DETECT 2BYTE-COMMAND DETECT 2BYTE-COMMAND RESET 10010000 FOCUS-OFFSET ADJUST START 10010001 FOCUS-OFFSET ADJUST OFF 10010010 TRACK-OFFSET ADJUST START 10010011 TRACK-OFFSET ADJUST OFF 10010100 10010101 LASER ON LASER OFF : F-SERVO ON 10010110 LASER OFF : F-SERVO OFF 10010111 SPINDLE 8CM — V — V — — — — — V — 10011000 SPINDLE 12 CM 10011001 SPINDLE OFF 10011010 SLED ON 10011011 SLED OFF V — V — — — 1 0 0 1 1 1 0 0 E/F BALANCE START 10011101 TRACK-SERVO OFF 10011110 TRACK-SERVO ON Non-adjusted — V — — Notes Concerning Microprocessor Program Creation 1. Commands After sending the FOCUS START command and the E/F BALANCE START command, send 11111110 (FEH) in order to clear the internal registers of the IC. Reason: Although the above commands are executed at point 1 in the timing chart below, the same commands will be executed again at point 2 if there is subsequent input to CE as shown below. Timing 2 µs or more 2 µs or more 10 µs or more 1 µs or more 1 µs or more ‘‘FOCUS START’’ command ‘‘E/F BALANCE START’’ command When sending a TRACK-OFFSET ADJUST START command or a FOCUS-OFFSET ADJUST START command after either VCC ON (POWER ON RESET), RESET command, or a corresponding OFFSET ADJUST OFF command, waiting time is necessary as listed below. (Only when a 4.2 MHz clock is input.) TRACK-OFFSET ADJUST START: 4 ms or more FOCUS-OFFSET ADJUST START: 4 ms or more 2. E/F balance adjustment E/F balance adjustments should be made in a bit region of the disc, not a mirrored region. Since there is no track-kick for LA9240M, measures must be taken during EF balance adjustment to obtain a stable TE signal. (By a sled movement signal from a microprocessor, for example.) No.5482 - 11/20 LA9240M Pin Internal Equivalent Circuit Pin No. Pin Name 1 2 FIN2 FIN1 3 4 E F 5 6 17 21 26 28 44 TB TE– FD− FE− SP− SLEQ SLI 16 27 43 FD SPD SLC 8 36 TESI TES Internal Equivalent Circuit Continued on next page. No.5482 - 12/20 LA9240M Continued from preceding page. Pin No. Pin Name 9 34 SCI TGL 7 10 TE TH 11 12 TA TD− 13 TD Internal Equivalent Circuit Continued on next page. No.5482 - 13/20 LA9240M Continued from preceding page. Pin No. Pin Name 14 JP 15 TO 18 19 20 FA FA− FE Internal Equivalent Circuit Continued on next page. No.5482 - 14/20 LA9240M Continued from preceding page. Pin No. Pin Name 24 25 SPI SPG 29 30 31 SLD SL− SL+ 32 33 JP− JP+ 35 TOFF Internal Equivalent Circuit Continued on next page. No.5482 - 15/20 LA9240M Continued from preceding page. Pin No. Pin Name 37 46 49 54 HFL FSC DEF DRF 38 SLOF 39 40 23 CV− CV+ SP 42 RFS− 47 TBC Internal Equivalent Circuit Continued on next page. No.5482 - 16/20 LA9240M Continued from preceding page. Pin No. Pin Name 50 CLK 51 52 53 CL DAT CE 55 FSS 57 58 REFI VR 59 LF2 Internal Equivalent Circuit Continued on next page. No.5482 - 17/20 LA9240M Continued from preceding page. Pin No. Pin Name 41 60 61 RFSM PH1 BH1 62 LDD 63 LDS Internal Equivalent Circuit No.5482 - 18/20 LA9240M Sample Application Circuit No.5482 - 19/20 LA9240M No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. Anyone purchasing any products described or contained herein for an above-mentioned use shall: 1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: 2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1997. Specifications and information herein are subject to change without notice. No.5482 - 20/20