Ordering number : EN5823 CMOS IC LC35256D-10, LC35256DM, DT-70/10 Dual Control Pins: OE and CE 256K (32768-word × 8-bit) SRAM Overview Package Dimensions The LC35256D, LC35256DM, and LC35256DT are 32768-word × 8-bit asynchronous silicon gate CMOS static RAMs. These devices use a 6-transistor full CMOS memory cell, and feature low-voltage operation, low current drain, and an ultralow standby current. They provide two control signal inputs: an OE input for highspeed access and a chip select (CE) input for device selection and low power operating mode. This makes these devices optimal for systems that require low power or battery backup, and they allow memory to be expanded easily. Their ultralow standby current allows capacitorbased backup to be used as well. Since they support 3-V operation, they are appropriate for use in portable systems that operate from batteries. unit: mm Features 3187-SOP28D • Supply voltage range: 2.7 to 5.5 V — 5-V operation: 5.0 V±10% — 3-V operation: 2.7 to 3.6 V • Access times — 5-V operation LC35256DM, DT-70: 70 ns (max) LC35256D, DM, DT-10: 100 ns (max) — 3-V operation LC35256DM, DT-70: 200 ns (max) LC35256D, DM, DT-10: 500 ns (max) • Standby current — 5-V operation: 1.0 µA (Ta ≤ 60°C), 5.0 µA (Ta ≤ 85°C) — 3-V operation: 0.8 µA (Ta ≤ 60°C), 4.0 µA (Ta ≤ 85°C) • Operating temperature range: –40 to +85°C • Data retention supply voltage: 2.0 to 5.5 V • All I/O levels — 5-V operation: TTL compatible — 3-V operation: VCC – 0.2 V/0.2 V • Shared I/O pins and 3-state outputs • No clock signal required. • Packages — 28-pin DIP (600 mil) plastic package: LC35256D — 28-pin SOP (450 mil) plastic package: LC35256DM — 28-pin TSOP (8 × 13.4 mm) plastic package: LC35256DT 3012A-DIP28 [LC35256D] SANYO: DIP28 unit: mm [LC35256DM] SANYO: SOP28D unit: mm 3221-TSOP28(type-I) [LC35256DT] SANYO: TSOP28(type-I) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 51398RM (OT) No. 5823-1/8 LC35256D-10, LC35256DM, DT-70/10 Pin Assignment Row decoder Memory cell array Input data control circuit Input data buffer Address buffer Block Diagram Column I/O circuit Column decoder Output data buffer Address buffer Pin Functions A0 to A14 Address inputs WE Read/write control input OE Output enable input CE Chip enable input I/O1 to I/O8 Data I/O VCC, GND Power supply, ground No. 5823-2/8 LC35256D-10, LC35256DM, DT-70/10 Function Table CE OE WE Read cycle Mode L L H Data output I/O Supply current Write cycle L X L Data input ICCA Output disable L H H High-impedance ICCA Unselected H X X High-impedance ICCS ICCA X : H or L Specifications Absolute Maximum Ratings Parameter Symbol Maximum supply voltage Conditions Ratings VCC max Unit 7.0 V V Input pin voltage VIN –0.3* to VCC + 0.3 I/O pin voltage VI/O –0.3 to VCC + 0.3 V Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Note *: –3.0 V for pulse widths of up to 30 ns. I/O Capacitances at Ta = 25°C, f = 1 MHz Parameter Symbol Ratings Conditions min typ Unit max I/O pin capacitance CI/O VI/O = 0 V 6 10 pF Input pin capacitance CIN VIN = 0 V 6 10 pF Note: These parameters are not measured in all units, but rather are only measured in sampled units. [5-V Operation] DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Supply voltage Input voltages Symbol Ratings Conditions min typ Unit max VCC 4.5 5.5 V VIH 2.2 VCC + 0.3 V VIL –0.3* +0.8 V 5.0 Note *: –3.0 V for pulse widths of up to 30 ns. DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Symbol Ratings Conditions min typ* Unit max Input leakage current ILI VIN = 0 to VCC –1.0 +1.0 µA Output leakage current ILO VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC –1.0 +1.0 µA High-level output voltage VOH IOH = –1.0 mA Low-level output voltage VOL IOL = 2.0 mA 0.4 V VCE = VIL, II/O = 0 mA, VIN = VIH or VIL 5.0 mA mA ICCA2 Operating current drain Standby mode current drain 2.4 min TTL inputs VCC – 0.2 V/ 0.2 V inputs TTL inputs ICCA3 ICCS1 ICCS2 VCE = VIL, VIN = VIH or VIL, II/O = 0 mA, Duty 100% VCE ≥ VCC – 0.2 V, VIN = 0 to VCC VCE = VIH, VIN = 0 to VCC LC35256DM, DT-70 V 35 40 cycle LC35256D, DM, DT-10 25 30 mA 1 µs cycle 3.5 6.0 mA Ta ≤ 25°C 0.01 µA Ta ≤ 60°C 1.0 µA Ta ≤ 85°C 5.0 µA 1.0 mA Note *: Reference value at Ta = 25°C, VCC = 5 V. No. 5823-3/8 LC35256D-10, LC35256DM, DT-70/10 AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V AC test conditions Input pulse voltage level VIH = 2.4 V, VIL = 0.6 V Input rise and fall times 5 ns Input and output timing level Output load 1.5 V LC35256DM, DT-70 One TTL gate + 30 pF (Including jig capacitances.) LC35256D, DM, DT-10 One TTL gate + 100 pF (Including jig capacitances.) Read Cycle LC35256D, DM, DT Parameter Symbol -70* min -10 max min Unit max Read cycle time tRC Address access time tAA 70 100 ns CE access time tCA 70 100 ns OE access time tOA 35 50 Output hold time tOH 10 10 ns CE output enable time tCOE 10 10 ns OE output enable time tOOE 5 5 CE output disable time tCOD 30 30 ns OE output disable time tOOD 25 25 ns 70 100 ns ns ns Note *: Specification values for the LC35256DM and LC35256DT. Write Cycle LC35256D, DM, DT Parameter Symbol -70* min -10 max min Unit max Write cycle time tWC 70 100 Address setup time tAS 0 0 ns Write pulse width tWP 55 60 ns CE setup time tCW 60 70 ns Write recovery time tWR 0 0 ns CE write recovery time tWR1 0 0 ns tDS 35 40 ns Data hold time tDH 0 0 ns CE data hold time tDH1 0 0 ns WE output enable time tWOE 5 5 WE output disable time tWOD Data setup time ns ns 30 30 ns Note *: Specification values for the LC35256DM and LC35256DT. [3-V Operation] DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 2.7 to 3.6 V Parameter Supply voltage Input voltages Symbol Conditions Ratings min typ Unit max VCC 2.7 3.6 V VIH VCC – 0.2 VCC + 0.3 V VIL –0.3* +0.2 V 3.0 Note *: –2.0 V for pulse widths of up to 30 ns. No. 5823-4/8 LC35256D-10, LC35256DM, DT-70/10 DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 2.7 to 3.6 V Parameter Symbol Ratings Conditions min typ* Unit max Input leakage current ILI VIN = 0 to VCC –1.0 +1.0 µA Output leakage current ILO VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC –1.0 +1.0 µA High-level output voltage VOH IOH = –0.5 mA Low-level output voltage VOL IOL = 1.0 mA Operating VCC – 0.2 V/ current drain 0.2 V inputs Standby mode VCC – 0.2 V/ current drain 0.2 V inputs VCC – 0.2 min ICCA4 ICCS1 VCE = VIL, VIN = VIH or VIL, II/O = 0 mA, Duty 100% V LC35256DM, DT-70 7 cycle LC35256D, DM, DT-10 1 µs cycle Ta ≤ 25°C VCE ≥ VCC – 0.2 V, VIN = 0 to VCC 0.2 V 10 mA 3 5 mA 1.5 2.5 mA 0.01 µA Ta ≤ 60°C 0.8 µA Ta ≤ 85°C 4.0 µA Note *: Reference value at Ta = 25°C, VCC = 3 V. AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 2.7 to 3.6 V AC test conditions Input pulse voltage level VIH = VCC – 0.2 V, VIL = 0.2 V Input rise and fall times 10 ns Input and output timing level Output load 1.5 V LC35256DM, DT-70 30 pF (Including jig capacitances.) LC35256D, DM, DT-10 100 pF (Including jig capacitances.) Read Cycle LC35256D, DM, DT Parameter Symbol -70* min -10 max min Unit max Read cycle time tRC Address access time tAA 200 500 ns CE access time tCA 200 500 ns OE access time tOA 100 250 Output hold time tOH 20 20 ns CE output enable time tCOE 20 20 ns OE output enable time tOOE 10 10 CE output disable time tCOD 60 120 ns OE output disable time tOOD 50 100 ns 200 500 ns ns ns Note *: Specification values for the LC35256DM and LC35256DT. No. 5823-5/8 LC35256D-10, LC35256DM, DT-70/10 Write Cycle LC35256D, DM, DT Parameter Symbol -70* min -10 max min Unit max Write cycle time tWC 200 500 ns Address setup time tAS 0 0 ns Write pulse width tWP 140 200 ns CE setup time tCW 150 250 ns Write recovery time tWR 0 0 ns CE write recovery time ns tWR1 0 0 Data setup time tDS 130 180 ns Data hold time tDH 0 0 ns CE data hold time tDH1 0 0 ns WE output enable time tWOE 10 10 ns WE output disable time tWOD 60 120 ns Note *: Specification values for the LC35256DM and LC35256DT. Timing Charts Read Cycle *1 *5 No. 5823-6/8 LC35256D-10, LC35256DM, DT-70/10 Write Cycle 1 (WE write) *6 *5 Write Cycle 2 (CE write) *6 *5 Notes: 1. Applications must set WE high during the read cycle. 2. External circuits in the application must not apply reverse phase signals to the DOUT pins when those pins are in the output state. 3. The time tWP is the period when CE and WE are both low. It is defined as the time from the fall of WE to the rise of CE or the rise of WE, whichever occurs first. 4. The time tCW is the period when CE and WE are both low. It is defined as the time from the fall of CE to the rise of CE or the rise of WE, whichever occurs first. 5. The data outputs (DOUT) go to the high-impedance state if any one of the following conditions hold: OE is high, CE is high, or WE is low. 6. OE must be held either high or low during the write cycle. 7. The DOUT pins have the same phase as the write cycle write data. No. 5823-7/8 LC35256D-10, LC35256DM, DT-70/10 Notes on Circuit Design Take the following operations into account when designing circuits that use these products to assure that none of the items in the maximum ratings are exceeded. • Supply voltage variations and fluctuations • Manufacturing variations in the electrical characteristics of the electrical components, including semiconductor devices, resistors, and capacitors. • Ambient temperature • Variations and fluctuations in the input and clock signals • Possible application of abnormal pulses Parameters listed in the allowable operating ranges must never exceed their stipulated ranges. If input pins to a CMOS IC are left open, through currents may occur in internal circuits to which intermediate potentials are input and result in incorrect circuit operation. Always verify that any unused pins are set up in appropriate states. Data Retention Characteristics at Ta = –40 to +85°C Parameter Symbol Data retention supply voltage Data retention current drain VDR ICCDR Chip enable setup time tCDR Chip enable hold time tR Ratings Conditions typ*1 min VCE ≥ VCC – 0.2 V 2.0 Ta ≤ 25°C VCC = 3.0 V, VCE ≥ VCC – 0.2 V max 5.5 0.01 Unit V µA Ta ≤ 60°C 0.7 µA Ta ≤ 85°C 3.5 µA 0 ns tRC*2 ns Notes: 1. Reference value at Ta = 25°C, VCC = 3 V. 2. tRC: Read cycle time Data Retention Waveforms Data retention mode Note *: VCCL 5-V operation: 4.5 V 3-V operation: 2.7 V ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5823-8/8