Ordering number : EN*5609A CMOS IC LC374100SM, ST 4 MEG (524288 words× 8 bits) Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC374100SM and LC374100ST are 524,288-word × 8-bit organization (4,194,304-bit) mask programmable read only memories. They feature a wide operating voltage range (2.6 to 5.5 V), a 100-ns access time (tCA) at VCC = 4.5 to 5.5 V, and a 200-ns access time at VCC = 2.6 to 3.3 V. unit: mm 3205-SOP32 [LC374100SM] Features • 524288 words × 8 bits organization • Power supply voltage range: 2.6 to 5.5 V • Fast access time(tAA): 120 ns (max.) VCC = 4.5 to 5.5 V (tCA): 100 ns (max.) VCC = 4.5 to 5.5 V 200 ns (max.) VCC = 2.6 to 5.5 V • Operating current: 55 mA (max.) • Standby current: 30 µA (max.) • Full static operation (internal clocked type) • 3 state outputs • JEDEC standard pin configuration • Package type LC374100SM: SOP32 (525 mil) LC374100ST: TSOP32 (8 mm × 20 mm) SANYO: SOP32 unit: mm 3224-TSOP32 [LC374100ST] SANYO: TSOP32 (type-I) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 53098HA (OT) No. 5609-1/4 LC374100SM, ST Pin Assignments Pin Functions A0 to A16 Address input D0 to D7 Data output CE Chip enable input OE Output enable input VCC Power supply VSS Ground Block Diagram Truth Table CE OE H X High-impedance Standby mode Output L H High-impedance Operating mode L L DOUT Current drain Operating mode X: H or L level should be offered. No. 5609-2/4 LC374100SM, ST Specifications Absolute Maximum Ratings Parameter Symbol Conditions Maximum supply voltage VCC *1 Supply input voltage VIN *1, 2 Supply output voltage VOUT Allowable power dissipation Pd max Ratings *1 Unit –0.3 to +7.0 V –0.3*2 to VCC + 0.3 V –0.3 to VCC + 0.3 V 1.0 W *1 Ta = 25°C; Reference values for the SANYO DIP package Operating temperature Topr *1 0 to +70 °C Storage temperature Tstg *1 –55 to +125 °C Note: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to Recommended Operating Conditions. 2. VIN (min) = –3.0 V (pulse width ≤ 30 ns) Input/Output Capacitance* at Ta = 25°C, f = 1.0 MHz Parameter Input capacitance Symbol CIN Output capacitance COUT Ratings Conditions min typ 8 pF 10 pF VIN = 0 V; Reference values for the SANYO DIP package VOUT = 0 V; Reference values for the SANYO DIP package Unit max Note: * This parameter is periodically sampled and not 100% tested. 3 V Operation DC Recommended Operating Ranges at Ta = –10 to +70°C, VCC = 2.6 to 5.5 V Parameter Symbol Conditions Ratings min typ Unit max Supply voltage VCC 2.6 5.5 V Input high level voltage VIH 2.2 VCC + 0.3 V Input low level voltage VIL –0.3 +0.6 V 5.0 DC Electrical Characteristics at Ta = –10 to +70°C, VCC = 2.6 to 5.5 V Parameter Operating supply current Standby supply current Symbol Conditions Ratings min typ Unit max ICCA1 CE = 0.2 V, VI = VCC – 0.2 V/0.2 V 30 mA ICCA2 CE = VIL, IO = 0 mA, VI = VIH/VIL, f = 10 MHz 55 mA ICCS1 CE = VCC – 0.2 V ICCS2 CE = VIH 30 (1.0) µA 1.0 (300) mA(µA) Input leakage current ILI VIN = 0 to VCC ±1.0 µA Output leakage current ILO CE or OE = VIH, VOUT = 0 to VCC ±1.0 µA Output high level voltage VOH IOH = –0.5 mA Output low level voltage VOL IOL = 0.5 mA 0.2 V 0.8 VCC V Note: * Guaranteed at Ta = 25°C AC Characteristics at Ta = –10 to +70°C, VCC = 2.6 to 5.5 V Parameter Cycle time Symbol Conditions tCYC Ratings min typ Unit max 200 (120*2) ns Address access time tAA 200 (120*2) ns CE access time tCA 200 (100*2) ns OE access time tOA 80 (40*2) Output hold time tOH Output disable time*1 tOD*1 20 ns ns 100 ns Note: 1. tOD is measured from the earlier edge of the CE or OE’s going high impedance. This parameter is periodically sampled and not 100% tested. 2. Guaranteed at VCC = 4.5 to 5.5 V No. 5609-3/4 LC374100SM, ST AC Test Conditions Input pulse levels 0.4 to 2.8 V Input rise/fall time 5 ns Input timing level 1.5 V Output timing level 1.5 V Output load See Figure 1 Figure 1 Output Load Timing Chart System Design Notes These ICs adopt the ATD technique, in which operation starts when a change in either the CE or address inputs is detected. This means that the output data immediately after power is applied is invalid. When using these ICs as program memory for Z80 and similar microprocessors, applications must take into account the fact that valid data will not be output after power is first applied unless the value of either the CE or at least one of the address lines is changed after the power supply has stabilized. Another point due to the use of the ATD technique is that these ICs are sensitive to input noise. Do not apply voltages outside the allowable DC input levels for extended periods and do not apply input voltages with large noise components. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5609-4/4