* Ordering number:ENN 4144 CMOS IC LC573104A, 573102A 4-bit Single Chip Microcontroller Preliminary Overview Package Dimensions LC573104A and LC573102A are CMOS 4-bit microcontrollers featuring low-voltage operation and low power dissipation. Both LC573104A and LC573102A incorporate a 4-bit parallel processing ALU, 4K bytes/2K bytes ROM, a 64×4-bit RAM, a 16-bit timer, and an infrared remote control transmission carrier output circuit. unit:mm 3112A-MFP24S [LC573104A, 573102A] 5.4 7.6 13 24 1 Features 0.35 • ROM : 4096×8 bits (LC573104A) 2048×8 bits (LC573102A) • RAM : 64×4 bits • Cycle time Cycle time 17.6µs 12 0.15 0.1 1.5 12.5 0.63 • Remote controller. • Control of small measuring instruments. 1.7max Applications System clock generator Ceramic oscillation circuit 1.0 (0.75) SANYO : MFP24S Oscillation frequency Supply voltage 455kHz 2.3 to 6.0V Pin Assignment • Current Drain a. At normal operation Current drain System clock generator Oscillation frequency Supply voltage 150µA typ CR oscillation 455kHz 3.0V 400µA typ CR oscillation 455kHz 5.0V b. HALT mode Current drain System clock generator Oscillation frequency Supply voltage 80µA typ CR oscillation 455kHz 3.0V 300µA typ CR oscillation 455kHz 5.0V Condition Oscillation frequency Supply voltage When CR oscillation is at STOP mode 455kHz 5.0V c. HOLD mode Leakage current 0.1µA typ Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O1501TN (KT)/13195JN/5252JN No.4144–1/16 LC573104A, 573102A • Port · Input port (S port, M port) : · Input/Ouput port : P0 port, P1 port P2 port 2-port (8 pins) [Key scan input port] 3-port (10 pins) 2-port (8 pins) [Key scan output port] 1-port (2 pins) [Key scan expansion port] [LED direct drivable port] • Infrared remote control carrier generation circuit. · Software-controllable remote control carrier output ON/OFF. · Software-controllable carrier frequency and duty ratio. <38kHz-1/3 duty, 38kHz-1/2 duty, 57kHz-1/2 duty> (When fixed carrier signal is output, it is specified by mask option) · 1kHz to 200kHz infrared remote control transmission carrier frequency. (When carrier output is selected by timer at mask option, and when 455kHz CR oscillator is used) · Infrared carrier output-dedicated terminal built-in (CA terminal). · 108ms HALT-mode cancel signal output. • Timer · 16-bit software-controllable Timer Timer input clock : Ceramic (CR) oscillation frequency (455kHz). · 108ms HALT release request signal generation timer (Free running timer). · Watchdog timer (changed over between USED/UNUSED by mask option) • Sub-routine stack level · 2 levels • Oscillation circuit · Ceramic (CR) oscillation circuit : 455kHz (for System clock generation), Feedback resistor built-in. • Standby function · HALT mode HALT mode used to reduce current drain. HALT mode suspends program execution. Following shows how to release the HALT mode. (A) System reset (B) HALT mode release request signal. · HOLD mode HOLD mode stops ceramic resonator (CR). The HOLD mold can be released in two ways. (A) System reset (B) Apply H level input to S port pin or M port pin. (However, it is necessary to set S port or M port HOLD mode release permission flag beforehand.) • From of shipment · MFP-24S (1.0mm pitch) and chip. NOTE : When dipping in solder to mount the MFP package on board, contact SANYO for instructions. No.4144–2/16 LC573104A, 573102A The Application Development System for the LC573100 Series. (1) Manual (A) Users Manual : LC573100 Series Users Manual. (B) Development Tool Manual : LC573100 Series Development Tool Manual. (2) Development Tools • Tools for application development of the LC573100 Series. (A) Personal computer (MS-DOS based). (B) Cross assembler (LC573100.EXE). (C) Mask option generator (SU573100.EXE). • Tools to evaluate application development of the LC573100 Series. (A) EVA chip (LC5797). NOTE 1) As RAM capacity differs between EVA chip (LC5797) and the LC573100 Series, always check before programming and debugging. LC573100 : 64×4 bits LC5797 : 256×4 bits NOTE 2) Always keep the DPH value in mind when programming. Only DPH ‘0’ to ‘3’ may be used as the RAM address. If DPH other than ‘0’ to ‘3’ is used as RAM address when programming, SANYO will not be liable for any trouble caused. (B) EVA chip board (TB5730). NOTE) The application evaluation board is the evaluation board made by the user. (C) Evaluation board [EVA420 (Monitor ROM : ER-573000)] (D) Display and mask option data control board [DCB-1A (REV3.6)] Development Support System Outline Do not cross or twist these cables. No.4144–3/16 LC573104A, 573102A (A) Block Diagram (LC573104A) No.4144–4/16 LC573104A, 573102A Die Specifications Chip size : Chip thickness : Pad size : 3.51mm×3.19mm 480µm 120µm×120µm Pad Layout Pad coordinates MFP24S pin assignment Pad Pin X No. Name (µm) 17 1465 1 VDD 18 1155 2 CA 19 – 305 3 P20 20 – 1485 4 P21 21 – 1485 5 P00 22 – 1485 6 P01 23 – 1485 7 P02 24 – 1485 8 P03 1 – 1485 9 P10 2 – 1485 10 P11 3 – 1485 11 P12 4 – 1485 12 P13 5 – 410 13 S1 Y (µm) 1365 1365 1365 1365 1110 870 565 325 20 – 220 – 480 – 1395 – 1395 MFP24S pin assignment Pad Pin X No. Name (µm) 6 360 14 S2 7 560 15 S3 8 760 16 S4 – 960 17 TEST – 1140 18 TEST 9 1560 19 M1 10 1560 20 M2 11 1560 21 M3 12 1560 22 M4 13 1465 23 RES 14 1465 24 VSS 15 1465 25 CF1 16 1465 26 CF2 Y (µm) – 1395 – 1395 – 1395 – 1395 – 1395 – 1395 – 905 – 685 – 445 330 570 755 1155 • The chip center is the origin of the above pad coordinates. The X, Y values represent the coordinate of the pad center. • When dipping the MFP24S package in solder to mount on boards, contact SANYO for instructions, etc. • Chip substrate should be connected to VSS or left open. No.4144–5/16 LC573104A, 573102A Pin Function MFP24S Pin Pin No. name 17 VDD 14 VSS Input/ Function description Output – Supply voltage. See Fig 1. 15 CF1 Input 16 CF2 5 S1 6 S2 7 S3 8 S4 9 M1 10 M2 11 M3 – Option Reset status Ground. See Fig 1. User for system clock oscillation. • 455kHz ceramic resonator is connected between CF1 and Output CF2 for oscillation. • Stops oscillation when receiving CR oscillation stop command. Input Input port S. • LSI system is reset by charging VDD to S1 to S4 simultaneously (Mask option). (1) 'L' level HOLD Tr YES/NO (2) Reset by S1 to S4. • Pull-down resistor ON. • Reset signal ENABLE. • Data is loaded in accumulator. Input Input port M. 'L' level HOLD Tr YES/NO • Pull-down resistor ON. Data loaded in accumulator. 12 M4 21 P00 Input/ 22 P01 Output • Data loaded in accumulator. 23 P02 24 P03 1 P10 Input/ 2 P11 Output • Data loaded in accumulator. 3 P12 4 P13 19 P20 Input/ 20 P21 Output • Data loaded in accumulator. Input/output port. • Output pin to output data from accumulator. (P-ch Open Drain Output) Input/output port. • Output pin to output data from accumulator. (P-ch Open Drain Output) Input/output port. • Output pin to output data from accumulator. (P-ch Open Drain Output) • LED direct drivable pin. 18 CA Output Remote control carrier output. Fixed carrier output/ • At reset 'L' level. Carrier output by timer • At fixed carrier output 38kHz-1/3 duty. 13 RES Input Reset input. Internal pull-up resistor. No.4144–6/16 LC573104A, 573102A Supply connections Fig. 1 Supply connections No.4144–7/16 LC573104A, 573102A Mask Option (1) Input port option Option Circuit Remarks 'L' level Hold Next port switches over in Tr selection sequence. • S1 to S4, M1 to M4 Input signal level Hold Tr selection • 'L' level Hold Tr used. • 'L' level Hold Tr not used. (2) Reset signal option by S port Option Circuit Remarks Resetting IC by Selects signal for resetting IC S port system by simultaneously charging 'H' level to S1 to S4. • Allow • Prohibit (3) Carrier standard clock generation circuit option for remote control Option 38/57kHz Circuit Remarks Software-controllable carrier frequency and duty. • Following carrier frequency and duty may be selected by setting control register 4. (1) 38kHz-1/3 Duty (2) 38kHz-1/2 Duty (3) 57kHz-1/2 Duty Timer 8 bit Timer 8-bit overflow signal overflow generates carrier signal for infrared remote control. No.4144–8/16 LC573104A, 573102A (4) Watchdog timer circuit option Option Circuit Remarks Watchdog Watchdog timer used/unused timer selection selection Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Conditions Ratings –0.3 to +7.0 V VDD1 –0.3 to VDD –0.3 to VDD V –0.3 to VDD+0.3 V –0.3 to VDD+0.3 V VDD2 Input voltage VOUT S1 to S4, M1 to M4, RES, P00 to P03, P10 to P13, P20, P21, CF1 (P00 to P03, P10 to P13, P20, P21 are input mode) CA, P00 to P03, P10 to P13, P20, P21, CF2 (P00 to P03, P10 to P13, P20, P21 are output mode) IOUT1 CA (per 1 pin) IOUT2 P00 to P03, P10 to P13 (per 1 pin) IOUT3 P20, P21 (Per 1 pin) IOUT4 Output pins other than listed above (per 1 pin) VIN Output voltage Output current (Per 1 pin) Total output current of all pins except CA Unit VDD Operating temperature IALL Topr Storage temperature Tstg 25 V mA 500 µA 10 mA 500 µA 25 mA –30 to +70 ˚C –40 to +125 ˚C All pins totaled (except for CA pin) Recommended Operating Ranges at Ta =–30 to +70˚C, VSS=0V Parameter Supply voltage Symbol Input low-level voltage VDD VIH1 VIL1 Input high-level voltage VIH2 Input low-level voltage VIL2 Operation frequency fOPG Input high-level voltage Conditions S1 to S4, M1 to M4, P00 to P03, P10 to P13, P20, P21 (P0, P1, P2 ports are input mode) RES At CR oscillation, Fig. 2 Ratings min typ max Unit 2.3 6.0 V 0.7VDD VDD V V 0 0.3VDD 0.75VDD VDD V 0 0.25VDD V 380 455 500 kHz Fig. 2 CR Oscillation Circuit No.4144–9/16 LC573104A, 573102A Electrical Characteristics at Ta =–30 to +70˚C, VSS=0V Parameter Symbol RIN1A Input impedance Output high-level voltage Output off-leak current Output high-level voltage Output off-leak current Output current (H) RIN1B RIN2 VOH1 IOFF IOFF VOH2 IOFF IOFF IOH1 Output current (L) IOL1 HALT-mode supply current IDD1 Operating current IDD2 Supply leak current 1 ILEAK1 Supply leak current 2 ILEAK2 Oscillator start-up voltage Oscillator sustaining voltage Oscillator start-up time VST VSUS tST Ratings Conditions min VDD=2.9V, VIL=0.4V, S1 to S4, M1 to M4, 'L' level Hold Tr, Fig. 3 VDD=2.9V, VIL=0.4V, S1 to S4, M1 to M4, 'L' level pull-down Tr, Fig. 3 typ 150 300 1000 kΩ 30 50 100 kΩ 300 kΩ 1.0 µA VDD=2.9V, RES 10 VDD=2.9V, IOH=–450µA, P00 to P03, P10 to P13 VIN=VSS VDD=2.9V, P00 to P03, P10 to P13 VIN=VDD VDD=2.9V, IOH=–10mA, P20, P21 V VDD–0.45 –1.0 µA VDD–0.5 V VIN=VSS VDD=2.9V, P20, P21 1.0 VIN=VDD –1.0 VDD=3.0V, VOH=VDD–1.5V, CA VDD=3.0V, VOH=0.9V, CA µA µA 6 12 2 mA 5 VDD=3.0V, 455kHz CR oscillation, Ccd=Ccg=150pF, Ta≤50°C, Fig.5 VDD=3.0V, 455=kHz CR oscillation, Ccd=Ccg=150pF, Ta≤50°C, Fig.5 VDD=3.0V Unit max mA 80 300 µA 150 500 µA Ta=25°C 0.2 1 µA Ta=50°C 1 5 µA 2.3 V Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4 2.0 V VDD=2.3V, Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4 30 ms Recommended Oscillators. Oscillator Manufacturer 455kHz ceramic Kyocera oscillator Murata Fuji Ceramics Part number Ccg Ccd 150pF KBR-455BK/Y 150pF CSB455E 150pF 150pF POE-455 150pF 150pF Electrical Characteristics at Ta =–30 to +70˚C, VSS=0V Parameter Symbol RIN1A Input impedance Output high-level voltage Output off-leak current Output high-level voltage Output off-leak current RIN1B RIN2 VOH1 IOFF IOFF VOH2 IOFF IOFF VDD=5.0V, RES VDD=5.0V, P20, P21 VDD=5.0V, VOH=VDD–2.5V, CA Output current (L) IOL1 VDD=5.0V, VOL=0.9V, CA Operating current IDD2 Supply leak current 1 ILEAK1 Supply leak current 2 ILEAK2 Oscillator start-up voltage Oscillator sustaining voltage Oscillator start-up time VST VSUS tST typ 70 200 600 kΩ 30 50 100 kΩ 300 kΩ 1.0 µA –1.0 µA VDD–0.5 V 1.0 –1.0 µA µA 10 20 mA 2 5 mA VDD=5.0V, 455kHz CR oscillation, Ccd=Ccg=150pF, Ta≤50°C, Fig.5 VDD=5.0V, 455kHz CR oscillation, Ccd=Ccg=150pF, Ta≤50°C, Fig.5 VDD=5.0V V VDD–0.75 VIN=VSS VIN=VDD Unit max 10 VDD=5.0V, IOH=–750µA, P00 to P03, P10 to P13 VIN=VSS VDD=5.0V, P00 to P03, P10 to P13 VIN=VDD VDD=5.0V, IOH=–10mA, P20, P21 IOH1 IDD1 min VDD=5.0V, VIL=0.4V, S1 to S4, M1 to M4, 'L' level Hold Tr, Fig. 3 VDD=5.0V, S1 to S4, M1 to M4, 'L' level pull-down Tr, Fig. 3 Output current (H) HALT-mode supply current Ratings Conditions 300 400 µA 400 500 µA Ta=25°C 0.2 1 µA Ta=50°C 1 5 µA 2.3 V Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4 VDD=2.3V, Ccd=Ccg=150pF, 455kHz CR oscillation, Fig. 4 2.0 V 30 ms No.4144–10/16 LC573104A, 573102A Fig. 3 : S1 to S4, M1 to M4 input structure Fig. 4 : Oscillator start-up voltage, Oscillator sustaining voltage, and Oscillator start-up time measuring circuit. Note : CR is 455kHz, S-PORT : M-PORT : Input lead Tr is ON. RES terminal has resistor built-in and is OPEN. I/O-PORT is set at Output Mode and data is ‘H’. Fig. 5 : Supply current measuring circuit LC573100 Series Instruction Set The instruction set uses the following abbreviations and symbols. AC ACn CF DP DPL DPH EDP EDPL EDPH SP TREG SCFn CTLn HEFn ROM CFCF ( ) [ ] ∨ ∨ < ← : Accumulator : Accumulator bit n : Carry flag : Data pointer : Data pointer low nibble : Data pointer high nibble : Data pointer save register : Data pointer save register low nibble : Data pointer save register high nibble : Strobe pointer : Temporary register : Start conditioning flag n : Control register n : Hold enable flag n : ROM data : Ceramic resonator oscillator control flag : Contents : Contents : Logical OR : Logical exclusive-OR : Logical AND : Transfer direction, result M M (DP) [M (DP)] PC PCn PAGE STSn (STSm) [P ( )] X Xn PDF SFR (SFR) CSTF SPC CCF ( ) [ ] φn WDT : Memory : Memory addressed by DP : Contents of memory addressed by DP : Program counter : Program counter bit n : Page latch : Status register n : Status register n content : Contents of port ( ) : Immediate data : Immediate data bit n : Input port pull-down flag : Special function register : Contents of special function register : Chrono start flag : Strobe pointer control bit : Carrier output control flag : Complement of contents : Complement of contents : Output from stage n of 15-stage divider : Watchdog timer • The special function registers are abbreviated as follows. TCON : Timer control register TLOW : Timer/counter register low byte THIGH : Timer/counter register high byte CTL4 : Control register 4 P0 : Port P0 P1 : Port P1 P2 : Port P2 No.4144–11/16 LC573104A, 573102A Bytes Status Cycles Instruction LC573100 Series Instructions TAAT 0000 0001 AC, TRGE ← ROM 1 2 Contents of ROM on current page, addressed by PC whose low-orderd 8 bits MTR 0001 0010 M (DP) ← TREG 1 1 Stores the conternts of TREG memory location pointed to by DP. ASR0 0001 1000 ACn ← ACn+1, AC3 ← 0 1 1 Shifts the contents of the AC right and enter 0 into the MSB. ASR1 0001 1001 ACn ← ACn+1, AC3 ← 1 1 1 Shifts the contents of the AC right and enter 1 into the MSB. ASL0 0001 1010 ACn ← ACn–1, AC0 ← 0 1 1 Shifts the contents of the AC left and enter 0 into the LSB. ASL1 0001 1011 ACn ← ACn–1, AC0 ← 1 1 1 Shifts the contents of the AC left and enter 1 into the LSB. INC 1001 1000 AC, M (DP) ← M (DP)+1 1 1 Memory M (DP) contents incremented +1, and loaded to AC and M (DP). DEC 1001 1001 AC, M (DP) ← M (DP)–1 1 1 Memory M (DP) contents decremented –1, and loaded to AC and M (DP). ADC 1000 0000 AC ← (AC)+[M (DP)]+CF 1 1 Mnemonic Instruction code Function Function description flag affected Accumulator are replaced with contents of AC and M (DP), are loaded to AC and TREG AC, memory M (DP) and CF contents are binary-added and the result loaded CF to AC. ADC* 1000 1000 AC, M (DP) ← (AC)+[M (DP)]+CF 1 1 AC, memory M (DP) and CF contents are binary-added and the result loaded CF Arithmetic to AC, M (DP). 1001 –––– SBC 1000 0001 SBC* 1000 1001 SBCI X 1001 –––– ADD 1000 0010 ADD* 1000 ADDI X 2 2 AC, immediate data and CF contents are binary-added, and the result loaded to AC. CF AC ← (AC)+[M (DP)]+CF 1 1 AC, memory M (DP) and CF contents are binary-subtracted, and the result loaded to AC. CF AC, M (DP) ← (AC)+[M (DP)]+CF 1 1 AC, memory M (DP) and CF contents are binary-subtracted, and the result loaded to AC and M (DP). CF 2 2 AC, immediate data and CF contents are binary-subtracted and the result loaded to AC. CF AC ← (AC)+[M (DP)] 1 1 AC and memory M (DP) contents are binary-added and the result loaded to AC. CF 1010 AC, M (DP) ← (AC)+[M (DP)] 1 1 AC and memory M (DP) contents are binary-added and the result loaded to AC and M (DP). CF AC ← (AC)+X 2 2 AC and immediate data contents are binary-added and the result loaded to CF 0001 AC ← (AC)+X+CF X3X2X1X0 1001 0010 –––– X3X2X1X0 SUB 1000 0011 AC ← (AC)+[M (DP)]+1 1 1 AC and memory M (DP) contents are binary-subtracted and the result loaded to AC. CF SUB* 1000 1011 AC, M (DP) ← (AC)+[M (DP)]+1 1 1 AC and memory M (DP) contents are binary-subtracted and the result loaded to AC and M (DP). CF AC ← (AC)+X+1 2 2 SUBI X AC. 1001 0011 –––– X3X2X1X0 ADN 1000 0100 AC ← (AC)+[M (DP)] 1 1 AC and memory M (DP) contents are binary-added and the result loaded to AC. ADN* 1000 1100 AC, M (DP) ← (AC)+[M (DP)] 1 1 AC and memory M (DP) contents are binary-added and the result loaded to AC and M (DP). AC ← (AC)+X 2 2 AC and immediate data contents are binary-added and the result loaded in AC. ADNI X Logical 0000 AC ← (AC)+X+CF X3X2X1X0 ADCI X AC and immediate data contents are binary-subtracted and the result loaded in CF AC. 1001 0100 –––– X3X2X1X0 AND 1000 0101 AC ← (AC) [M (DP)] 1 1 AC and memory M (DP) contents are ANDed and the result loaded to AC. AND* 1000 1101 AC, M (DP) ← (AC) [M (DP)] 1 1 AC and memory M (DP) contents are ANDed and the result loaded to AC and M (DP). ANDI X 1001 –––– 2 2 AC and immediate data contents are ANDed and the result loaded to AC. EOR 1000 0110 AC ← (AC) ∨ [M (DP)] 1 1 AC and memory M (DP) are exclusive ORed and the result loaded to AC. EOR* 1000 1110 AC, M (DP) ← (AC) ∨ [M (DP)] 1 1 AC and memory M (DP) are exclusive ORed, and the result loaded to AC and M (DP). EORI X 1001 –––– 2 2 AC and immediate data are exclusive ORed and the result loaded to AC. OR 1000 0111 AC ← (AC) ∨ [M (DP)] 1 1 AC and memory M (DP) are ORed and the result loaded to AC. OR* 1000 1111 AC, M (DP) ← (AC) ∨ [M (DP)] 1 1 AC and memory M (DP) are ORed and the result loaded to AC and M (DP). ORI X 1001 –––– 2 2 AC and immediate data are ORed and the result loaded to AC. 0101 AC ← (AC) X X3X2X1X0 0110 AC ← (AC) ∨ X X3X2X1X0 0111 AC ← (AC) ∨ X X3X2X1X0 Continued on next page. No.4144–12/16 LC573104A, 573102A Bytes Status Cycles Data transfer Flag SP Data Pointer Instruction Continued from preceding page. SDPL 0001 1100 DPL ← (AC) 1 1 AC contents loaded to DPL. SDPH 0001 1101 DPH ← (AC) 1 1 AC contents loaded to DPH. LDPL 1111 1101 AC ← (DPL) 1 1 DPL contents loaded to AC. LDPH 1111 1110 AC ← (DPH) 1 1 DPH contents loaded to AC. MDPL X 1011 X3X2X1X0 DPL ← X 1 1 Immediate data X loaded to DPL. MDPH X 1100 X3X2X1X0 DPH ← X 1 1 Immediate data X loaded to DPH. EDPL 0001 1110 (DPL) ↔ (EDPL) 1 1 DPL and EDPL contents exchanged. EDPH 0001 1111 (DPH) ↔ (EDPH) 1 1 DPH and EDPH contents exchanged. IDPL 1001 1010 DPL ← (DPL)+1 1 1 DPL contents incremented +1. IDPH 1001 1100 DPH ← (DPH)+1 1 1 DPH contents incremented +1. DDPL 1001 1011 DPL ← (DPL)–1 1 1 DPL contents decremented –1. DDPH 1001 1101 DPH ← (DPH)–1 1 1 DPH contents decremented –1. SSP 1010 1110 SP ← (AC) 1 1 AC contents loaded to SP. LSP 1010 1010 AC ← (SP) 1 1 SP contents loaded to AC. MSP X 1110 1 1 Immediate data X loaded to SP. ISP 1001 1110 SP ← (SP)+1 1 1 SP contents incremented +1. DSP 1001 1111 SP ← (SP)–1 1 1 SP contents decremented –1. LHLT 1010 1011 AC ← (STS2), STS2 ← 0 1 1 STS2 contents loaded to AC and STS2 is reset. SCF1 to SCF4 L500 1010 1100 AC ← (STS1), SCF0 ← 0 1 1 STS1 contents loaded to AC and SCF0 is reset. SCF0 CSP 0000 0100 CSTF ← 0 1 1 CSTF reset. CSTF CST 0000 0101 CSTF ← 1 1 1 CSTF set. CSTF RC5 0000 0110 HEF0 ← 0 1 1 HEF0 reset to inhibit Halt mode release by overflow from the divider circuit. HEF0 SC5 0000 0111 HEF0 ← 1 1 1 HEF0 set enabling overflow from the divider circuit to release the Halt mode. HEF0 RCF 1111 0000 CF ← 0 1 1 CF reset. CF SCF 1111 0001 CF ← 1 1 1 CF set. CF LDA 1010 1001 AC ← [M (DP)] 1 1 Memory M (DP) contents transferred to AC. STA 1010 1101 M (DP) ← (AC) 1 1 AC contents stored in memory M (DP). LDI X 0011 X3X2X1X0 AC ← X 1 1 Immediate data X loaded to AC. MVI X 0010 X3X2X1X0 M (DP) ← X 1 1 Immediate data X loaded to memory M (DP). Mnemonic Instruction code Function X3X2X1X0 SP ← X Function description flag affected Continued on next page. No.4144–13/16 LC573104A, 573102A HALT 0000 SCI X 1101 0000 Function CPU operation halts X3X2X1X0 CTL2 ← X 1 1 • Halts CPU operation. HALT mode is released under the following conditions. • HALT mode is cancelled by the interaction of SIC X and SC5 commands. 1 1 X0 to X3 Operation. Function description HEF1 to HEF4 X0 HFE1 is set to enable release of HALT mode by overflow signal from divider circuit following CF oscillation circuit. X1 HFE2 is set enabling signal rise at input port S to release HALT mode. X2 HFE3 is set enabling signal rise at input port M to release HALT mode. X3 HFE4 is set enabling 1/10 second pulse to release HALT. NOP 1111 1111 No operation 1 1 No operation. IPS 1010 1111 AC ← [P (S)] 1 1 Input data at input port S loaded to AC. IPM 1010 1000 AC ← [P (M)] 1 1 Input data at input port M loaded to AC. SPDR X 1111 0 1 X 1X0 PDF ← X 1 1 Pull-down resister MOS-Tr at corresponding input port turned ON/OFF. Bit content Input/Output Status flag affected Bytes Instruction code Cycles Mnemonic CPU control Instruction Continued from preceding page. OUT TWRT IN 1111 0000 0001 1100 0010 0111 (1) Cannot be used when SPC =0&SP=0H to CH, EH, FH. 1 1 Operation X0=0 S-Terminal Pull down Tr OFF. X0=1 S-Terminal Pull down Tr ON. X1=0 M-Terminal Pull down Tr OFF. X1=1 M-Terminal Pull down Tr ON. Cannnot be used. (Causes error when OUT is executed at SPC=0&SP=0H to CH, EH, FH.) (2) When SP=0&SP=D CTL3 ← (AC) AC contents transferred to CTL3. (3) When SPC=1 SFR ← (AC) AC contents transferred to special function register SFR. (1) Cannot be used when SPC =0&SP=0H to CH, EH, FH. 1 1 PDF CFCF CCF Cannnot be used. (Causes error when TWRT is executed at SPC=0&SP=0H to CH, EH, FH.) (2) When SPC=0&SP=D CTL3 ← ROM High-order 4 bits data of ROM, on current page, addressed by PC whose loworder 8 bits are replaced by AC and M (DP) contents, is transferred to CTL3. (3) When SPC=1 SFR ← ROM High-order 4 bits or 8 bits data of ROM, on the current page, addressed by PC whose low-order 8 bits are replaced by AC and M (DP) contents is transferred to special function register SFR (1) Cannot be used at SPC =0&SP=0H to CH, EH, FH. 1 1 CFCF CCF Cannnot be used. (Causes error when IN is executed at SPC=0&SP=0H to CH, EH, FH.) (2) When SPC=0&SP=D AC ← (STS3) STS3 contents transferred to AC. (3) When SPC=1 AC ← (SFR) Special function register SFR contents transferred to AC. Continued on next page. No.4144–14/16 LC573104A, 573102A Bytes (PC10 to PC0) ← X10 to X0 2 2 Loads data specified by X10 to X0 to PC and jumps unconditionally. If AC0=1 then 2 2 When AC bit 0 is '1', data specified by X10 to X0 is loaded to PC and jumps. 1 X10X9X8 If AC1=1 then 2 2 When AC bit 1 is '1', data specified by X10 to X0 is loaded to PC and jumps. BAB2 X X7X6X5X4 X3X2X1X0 0110 1 X10X9X8 If AC2=1 then 2 2 When AC bit 2 is '1', data specified by X10 to X0 is loaded to PC and jumps. BAB3 X X7X6X5X4 X3X2X1X0 0111 1 X10X9X8 If AC3=1 then 2 2 When AC bit 3 is '1', data specified by X10 to X0 is loaded to PC and jumps. BAZ X X7X6X5X4 X3X2X1X0 0100 0 X10X9X8 If AC=0 then 2 2 When AC is '0', data specified by X10 to X0 is loaded to PC and jumps. BANZ X X7X6X5X4 X3X2X1X0 0101 0 X10X9X8 2 2 When AC is not '0', data specified by X10 to X0 is loaded to PC and jumps. BCNH X X7X6X5X4 X3X2X1X0 0110 0 X10X9X8 2 2 When CF is '0', data specified by X10 to X0 is loaded to PC and jumps. BCH X X7X6X5X4 X3X2X1X0 0111 0 X10X9X8 If CF=1 then 2 2 PAGE X7X6X5X4 X3X2X1X0 0001 0001 (PC10 to PC0) ← X10 to X0 PAGE ← [M (DP)] When CF is '1', data specified by X10 to X0 is loaded to PC and jumps. 1 1 Memory M (DP) contents loaded to PAGE latch. PC10 to PC08 ← (PAGE) PC07 to PC04 ← (AC) 1 1 Unconditionally jumps to page specified by PAGE and address whose loworder 8 bits are specified by contents of AC and memory M (DP). Mnemonic JMP X BAB0 X BAB1 X Branching/subroutine Status Cycles Instruction Continued from preceding page. Instruction code 0000 1 X10X9X8 X7X6X5X4 X3X2X1X0 0100 1 X10X9X8 X7X6X5X4 X3X2X1X0 0101 Function (PC10 to PC0) ← X10 to X0 affected At '0', PC is incremented +2. (PC10 to PC0) ← X10 to X0 At '0', PC is incremented +2. (PC10 to PC0) ← X10 to X0 At '0', PC is incremented +2. (PC10 to PC0) ← X10 to X0 When AC is not '0', PC is incremented +2. (PC10 to PC0) ← X10 to X0 If CF≠1 then flag At '0', PC is incremented +2. (PC10 to PC0) ← X10 to X0 If AC≠0 then Function description When AC is '0', PC is incremented +2. (PC10 to PC0) ← X10 to X0 When CF is '1', PC is incremented +2. When CF is '0', PC is incremented +2. JMP* 0001 0000 ROM0 1100 0010 1000 0000 PC11 ← 0 2 2 Select ROM bank 0. ROM1 1100 0010 1000 0001 PC11 ← 1 2 2 Select ROM bank 1. STACK ← (PC)+2 (PC10 to PC0) ← X10 to X0 PC ← (STACK) 2 2 Current PC+2 contents are saved in STACK, data specified by X10 to X0 is loaded to PC and sub-routine is called. 1 1 Returns PC contents saved in STACK to PC and returns from sub-routine. 1001 0000 SPC ← 0 2 2 Resets strobe pointer control bit (SPC) to '0'. SPC SPC ← 1 2 2 Sets strobe pointer control bit (SPC) to '1'. SPC SCF0 SCF4 PC03 to PC00 ← [M (DP)] JSR X RST Miscellaneous SPC0 SPC1 1010 0 X10X9X8 X7X6X5X4 X3X2X1X0 0001 0011 1100 0010 1100 1001 0010 0001 CSEC 1111 1011 φ11 to φ15 ← 0 1 1 Resets high-order 4 bits of divider circuit. RWDT 1111 1001 (WDT) ← 0 1 1 Resets Watchdog Timer counter. No.4144–15/16 LC573104A, 573102A LC573100 Series Instructions Map Lower 0 1 2 3 4 5 6 7 8 0 HALT TAAT TWRT – CSP CST RC5 SC5 1 JMP* PAGE MTR RTS – – – IN 9 A B C D E F SDPL SDPH EDPL EDPH Uppwer 2 JMP X ASR0 ASR1 ASL0 ASL1 MVI X 3 LDI X 4 BAZ X BAB0 X 5 BCNH X BAB1 X 6 BCNH X BAB2 X 7 BCH X BAB3 X 8 ADC SBC ADD SUB ADN AND EOR OR ADC* SBC* ADD* SUB* ADN* AND* EOR* OR* 9 ADCI SBCI ADDI SUBI ADNI ANDI EORI ORI INC DEC IDPL DDPL IDPH DDPH ISP DSP IPM LDA LSP LHLT L500 STA SSP IPS LDPL LDPH NOP JSR X A B MDPL X C MDPH X – ROMX SPCX D E F – SIC X MSP X RCF SCF NOP NOP SPDR X – RWDT – XXX : 1 Byte-1 Cycle instruction ROMX : ROM0 instruction (C820H), ROM1 instruction (C821H) XXX : 2 Byte-2 Cycle instruction SPCX : CSEC OUT SPC0 instruction (C920H), SPC1 instruction (C921H) XXX : 1 Byte-2 Cycle instruction Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2001. Specifications and information herein are subject to change without notice. PS No.4144–16/16