SANYO LC72133V

Ordering number : EN5427A
CMOS LSI
LC72133M, 72133V
PLL Frequency Synthesizer for
Electronic Tuning
Overview
Package Dimensions
The LC72133M and LC72133V are a phase-locked loop
frequency synthesizer LSI circuits for use in radio tuners.
It supports low-voltage (2.7 to 3.6 V) operation and can
implement high-performance AM/FM tuners easily.
unit: mm
3036B-MFP20
[LC72133M]
Functions
• High speed programmable dividers
— FMIN: 10 to 120 MHz ..........pulse swallower
(built-in divide-by-two prescaler), VDD ≥ 2.7 V
10 to 130 MHz ..........pulse swallower
(built-in divide-by-two prescaler), VDD ≥ 3.0 V
— AMIN: 2 to 40 MHz ..............pulse swallower
0.5 to 10 MHz ...........direct division
• IF counter
— IFIN: 0.4 to 12 MHz ...........AM/FM IF counter
• Reference frequencies
— Twelve selectable frequencies
(4.5 or 7.2 MHz crystal)
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50 and 100 kHz
• Phase comparator
— Dead zone control
— Unlock detection circuit
— Deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— Input or output ports: 2
— Support clock time base output
• Serial data I/O
— Support CCB format communication with the
system controller.
• Operating ranges
— Supply voltage........................2.7 to 3.6 V
— Operating temperature............–20 to +70°C
• Package
MFP20
SSOP20
SANYO: MFP20
unit: mm
3179A-SSOP20
[LC72133V]
SANYO: SSOP20
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT)/63196HA (OT) No. 5427-1/22
LC72133M, 72133V
Pin Assignment
Block Diagram
No. 5427-2/22
LC72133M, 72133V
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Supply voltage
Maximum input voltage
Maximum output voltage
Maximum output current
Allowable power dissipation
Pins
Ratings
Unit
VDD max
VDD
–0.3 to +5.5
VIN1 max
CE, CL, DI, AIN
–0.3 to +5.5
V
VIN2 max
XIN, FMIN, AMIN, IFIN
–0.3 to VDD + 0.3
V
VIN3 max
IO1, IO2
–0.3 to +15
V
VO1 max
DO
–0.3 to +5.5
V
VO2 max
XOUT, PD
–0.3 to VDD + 0.3
V
V
VO3 max
BO1 to BO4, IO1, IO2, AOUT
IO1 max
BO1
0 to 3.0
mA
IO2 max
AOUT, DO
0 to 6.0
mA
IO3 max
BO2 to BO4, IO1, IO2
0 to 6.0
mA
Ta ≤ 70°C: LC72133M
180
mW
160
mW
Pd max
–0.3 to +15
Ta ≤ 70°C: LC72133V
V
Operating temperature
Topr
–20 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Symbol
VDD
VIH1
VIH2
Supported crystals
min
typ
max
Unit
2.7
3.6
V
CE, CL, DI
0.7 VDD
5.5
V
IO1, IO2
V
0.7 VDD
13
CE, CL, DI, IO1, IO2
0
0.3 VDD
V
VO1
DO
0
5.5
V
V O2
BO1 to BO4, IO1, IO2,
AOUT
0
13
V
fIN1
Input amplitude
Conditions
VIL
Output voltage
Input frequency
Pins
VDD
XIN
VIN1
1
8
MHz
fIN2-1
FMIN
VIN2-1
10
90
MHz
fIN2-2
FMIN
VIN2-2
10
120
MHz
fIN2-3
FMIN
VIN2-1, VDD ≥ 3.0 V
10
130
MHz
fIN3
AMIN
VIN3, SNS = 1
2
40
MHz
fIN4
AMIN
VIN4, SNS = 0
0.5
10
MHz
fIN5
IFIN
VIN5
0.4
12
MHz
VIN1
XIN
fIN1
400
900
mVrms
VIN2-1
FMIN
fIN2-1, fIN2-3
VIN2-2
FMIN
fIN2-2
VIN3
AMIN
VIN4
AMIN
VIN5-1
VIN5-2
Xtal
70
900
mVrms
100
900
mVrms
fIN3, SNS = 1
70
900
mVrms
fIN4, SNS = 0
70
900
mVrms
IFIN
fIN5, IFS = 1
70
900
mVrms
IFIN
fIN6, IFS = 0
100
900
mVrms
XIN, XOUT
*
4.0
8.0
MHz
Note: * Recommended crystal oscillator CI values:
CI ≤ 120Ω (For a 4.5 MHz crystal)
CI ≤ 70Ω (For a 7.2 MHz crystal)
<Sample Oscillator Circuit>
Crystal oscillator: HC-49/U (manufactured by Kinseki, Ltd.), CL = 12 pF
C1 = C2 = 15 pF
The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items. Therefore we
recommend consulting with the manufacturer of the crystal for evaluation and reliability.
No. 5427-3/22
LC72133M, 72133V
Electrical Characteristics for the Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V
Parameter
Symbol
Pins
Conditions
min
typ
max
Unit
Rf1
XIN
1.0
MΩ
Rf2
FMIN
500
kΩ
Rf3
AMIN
500
kΩ
Rf4
IFIN
250
kΩ
Rpd1
FMIN
200
kΩ
Rpd2
AMIN
200
kΩ
Hysteresis
VHIS
CE, CL, DI, IO1, IO2
Output high level voltage
VOH1
PD
IO = –1 mA
VOL1
PD
IO = 1 mA
1.0
V
IO = 0.5 mA
0.6
V
IO = 1 mA
1.2
V
IO = 1 mA
0.25
V
IO = 3 mA
0.75
V
IO = 1 mA
0.25
V
IO = 5 mA
1.25
V
Built-in feedback resistance
Built-in pull-down resistor
VOL2
Output low level voltage
Input high level current
Input low level current
Output off leakage current
VOL3
BO1
DO
0.1 VDD
V
VDD – 1.0
V
VOL4
BO2 to BO4, IO1, IO2
VOL5
AOUT
IO = 1 mA, AIN = 1.3 V
0.5
V
IIH1
CE, CL, DI
VI = 5.5 V
5.0
µA
IIH2
IO1, IO2
VI = 13 V
5.0
µA
IIH3
XIN
VI = VDD
1.3
8
µA
IIH4
FMIN, AMIN
VI = VDD
2.7
15
µA
IIH5
IFIN
VI = VDD
5.4
30
µA
IIH6
AIN
VI = 5.5 V
200
nA
IIL1
CE, CL, DI
VI = 0 V
5.0
µA
IIL2
IO1, IO2
VI = 0 V
5.0
µA
IIL3
XIN
VI = 0 V
1.3
8
µA
IIL4
FMIN, AMIN
VI = 0 V
2.7
15
µA
IIL5
IFIN
VI = 0 V
5.4
30
µA
IIL6
AIN
VI = 0 V
200
nA
IOFF1
BO1 to BO4, AOUT,
IO1, IO2
VO = 13 V
5.0
µA
5.0
µA
IOFF2
DO
VO = 5.5 V
High level three-state
off leakage current
IOFFH
PD
VO = VDD
0.01
200
nA
Low level three-state
off leakage current
IOFFL
PD
VO = 0 V
0.01
200
nA
Input capacitance
CIN
6
VDD
Xtal = 7.2 MHz,
fIN2 = 130 MHz,
VIN2 = 70 mVrms
IDD2
VDD
PLL block stopped
(PLL INHIBIT),
Xtal oscillator operating
(Xtal = 7.2 MHz)
IDD3
VDD
PLL block stopped
Xtal oscillator stopped
IDD1
Current drain
FMIN
2
pF
5
0.3
mA
mA
30
µA
No. 5427-4/22
LC72133M, 72133V
Pin Functions
Symbol
XIN
XOUT
FMIN
Pin No.
1
20
14
Type
Xtal OSC
Local oscillator
signal input
Functions
Circuit configuration
• Crystal resonator connection
(4.5/7.2 MHz)
• FMIN is selected when the serial data input DVS bit is
set to 1.
• The input frequency range is from 10 to 130 MHz.
• The input signal passes through the internal divide-bytwo prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
Operating
FMIN input frequency
conditions
10 to 90 MHz 10 to 120 MHz 10 to 130 MHz
Operating power- 2.7 to 3.6 V
2.7 to 3.6 V
3.0 to 3.6 V
supply voltage
Operating input
70 to 900
100 to 900
70 to 900
levels
mVrms
mVrms
mVrms
• AMIN is selected when the serial data input DVS bit is
set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
AMIN
13
Local oscillator
signal input
CE
2
Chip enable
CL
4
Clock
• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
DI
3
Data input
• Inputs serial data transferred from the controller to the
LC72133.
DO
5
Data output
• Outputs serial data transferred from the LC72133 to the
controller.
The content of the output data is determined by the
serial data DOC0 to DOC2.
VDD
15
Power supply
• The LC72133 power supply pin (VDD = 2.7 to 3.6 V)
• The power on reset circuit operates when power is first
applied.
Set this pin high when inputting (DI) or outputting (DO)
serial data.
Continued on next page.
No. 5427-5/22
LC72133M, 72133V
Continued from preceding page.
Symbol
VSS
BO1
BO2
BO3
BO4
IO1
IO2
Pin No.
19
6
7
8
9
10
12
Type
Ground
Output port
Functions
• The LC72133 ground
I/O port
• I/O dual-use pins
• The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port
• When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
Input state: low = 0 data value
high = 1 data value
• When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low
• These pins function as input pins following a power on
reset.
PD
16
Charge pump
output
AIN
AOUT
17
18
LPF amplifier
transistor
• The n-channel MOS transistor used for the PLL active
low-pass filter.
IF counter
• Accepts an input in the frequency range 0.4 to 12 MHz.
• The input signal is directly transmitted to the IF counter.
• The result is output starting the MSB of the IF counter
using the DO pin.
• Four measurement periods are supported: 4, 8, 32, and
64 ms.
11
—
• Dedicated output pins
• The output states are determined by BO1 to BO4 bits in
the serial data.
Data: 0 = open, 1 = low
• A time base signal (8 Hz) can be output from the BO1
pin. (When the serial data TBC bit is set to 1.)
• Care is required when using the BO1 pin, since it has a
higher on impedance than the other output ports (pins
BO2 to BO4).
• The data = 0 (open) state is selected after the power-on
reset.
• PLL charge pump output
When the frequency generated by dividing the local
oscillator frequency by N is higher than the reference
frequency, a high level is output from the PD pin.
Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high impedance state
when the frequencies match.
IFIN
Circuit configuration
No. 5427-6/22
LC72133M, 72133V
Serial Data I/O Methods
The LC72133 inputs and outputs data using the Sanyo CCB (computer control bus) audio LSI serial bus format. This
LSI adopts an 8-bit address format CCB.
I/O mode
Address
B0
B1
B2
B3
A0
A1
A2
A3
Function
1
IN1 (82)
0
0
0
1
0
1
0
0
• Control data input mode (serial data input)
• 24 data bits are input.
• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.
2
IN2 (92)
1
0
0
1
0
1
0
0
• Control data input mode (serial data input)
• 24 data bits are input.
• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.
0
Data output mode (serial data output)
• The number of bits output is equal to the number of clock
cycles.
• See the “DO Output Data (Serial Data Output) Structure”
item for details on the meaning of the output data.
3
OUT (A2)
0
1
0
1
0
1
0
No. 5427-7/22
LC72133M, 72133V
1. DI Control Data (Serial Data Input) Structure
• IN1 Mode
• IN2 Mode
No. 5427-8/22
LC72133M, 72133V
2. DI Control Data Functions
No.
Control block/data
Functions
Related data
Programmable divider data • Data that sets the programmable divider.
P0 to P15
(1)
A binary value in which P15 is the MSB. The LSB changes depending on
DVS and SNS. (*: don’t care)
DVS
SNS
LSB
Divisor setting (N)
1
*
P0
272 to 65535
Actual divisor
0
1
P0
272 to 65535
The value of the setting
0
0
P4
4 to 4095
The value of the setting
Twice the value of the setting
Note: P0 to P3 are ignored when P4 is the LSB.
DVS, SNS
• Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches
the input frequency range. (*: don’t care)
DVS
SNS
Input pin
Input frequency range
1
*
FMIN
10 to 130 MHz
0
1
AMIN
2 to 40 MHz
0
0
AMIN
0.5 to 10 MHz
Note: See the “Programmable Divider” item for more information.
Reference divider data
R0 to R3
(2)
• Reference frequency (fref) selection data.
R3
R2
R1
R0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reference frequency (kHz)
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
10
9
5
1
1
1
1
1
0
0
0
1
3
15
1
1
1
0
PLL INHIBIT + Xtal OSC STOP
100
50
25
25
12.5
6.25
3.125
3.125
1
1
1
1
PLL INHIBIT
Note: PLL INHIBIT
The programmable divider block and the IF counter block are stopped, the FMIN,
AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump
goes to the high impedance state.
XS
• Crystal resonator selection
XS = 0: 4.5 MHz
XS = 1: 7.2 MHz
The 7.2 MHz frequency is selected after the power-on reset.
IF counter control data
CTE
• IF counter measurement start data
CTE = 1: Counter start
CTE = 0: Counter reset
GT0, GT1
• Determines the IF counter measurement period.
(3)
Measurement time (ms)
IFS
GT1
GT0
0
0
4
Wait time (ms)
3 to 4
0
1
8
3 to 4
1
0
32
7 to 8
1
1
64
7 to 8
Note: See the “IF Counter” item for more information.
(4)
(5)
I/O port specification data
IOC1, IOC2
• Specifies the I/O direction for the bidirectional pins IO1 and IO2.
Data: 0 = input mode, 1 = output mode
Output port data
BO1 to BO4, IO1, IO2
• Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports
Data: 0 = open, 1 = low
• The data = 0 (open) state is selected after the power-on reset.
IOC1
IOC2
Continued on next page.
No. 5427-9/22
LC72133M, 72133V
Continued from preceding page.
No.
Control block/data
DO pin control data
DOC0, DOC1, DOC2
Functions
Related data
• Data that determines the DO pin output
DOC2
DOC1
DOC0
0
0
0
0
0
0
1
1
0
1
0
1
Open
Low when the unlock state is detected
end-UC*1
Open
DO pin state
1
1
1
1
0
0
1
1
0
1
0
1
Open
The IO1 pin state*2
The IO2 pin state*2
Open
The open state is selected after the power-on reset.
Note: 1. end-UC: Check for IF counter measurement completion
UL0, UL1,
CTE,
IOC1, IOC2
(6)
➀ When end-UC is set and the IF counter is started (i.e., when CTE is changed
from zero to one), the DO pin automatically goes to the open state.
➁ When the IF counter measurement completes, the DO pin goes low to indicate
the measurement completion state.
➂ Depending on serial data I/O (CE: high) the DO pin goes to the open state.
2. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high)
will output the contents of the internal DO serial data in synchronization with the
CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2).
Unlock detection data
UL0, UL1
(7)
• Selects the phase error (øE) detection width for checking PLL lock.
A phase error in excess of the specified detection width is seen as an unlocked state.
UL1
UL0
0
0
Stopped
øE detection width
Open
Detector output
0
1
0
øE is output directly
1
0
±0.55 µs
øE is extended by 1 to 2 ms
1
1
±1.11
øE is extended by 1 to 2 ms
DOC0,
DOC1,
DOC2
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data
becomes zero.
Phase comparator
control data
DZ0, DZ1
(8)
• Controls the phase comparator dead zone.
DZ1
DZ0
0
0
Dead zone mode
DZA
0
1
DZB
1
0
DZC
1
1
DZD
Dead zone widths: DZA < DZB < DZC < DZD
(9)
Clock time base
TBC
Charge pump control data
DLC
Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output
from the BO1 pin. (BO1 data is invalid in this mode.)
DLC
(10)
BO1
• Forcibly controls the charge pump output.
Charge pump output
0
Normal operation
1
Forced low
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to
low and setting Vtune to VCC. (This is the deadlock clearing circuit.)
Continued on next page.
No. 5427-10/22
LC72133M, 72133V
Continued from preceding page.
No.
Control block/data
(11)
IF counter control data
IFS
• Note that if this value is set to zero the system enters input sensitivity degradation mode,
and the sensitivity is reduced to 10 to 30 mV rms.
* See the “IF Counter Operation” item for details.
LSI test data
TEST 0 to TEST 2
• LSI test data
TEST0
TEST1
These values must all be set to 0.
TEST2
DNC
Don’t care. This data must be set to 0.
(12)
Functions
Related data
These test data are set to 0 automatically after the power-on reset.
(13)
3. DO Output Data (Serial Data Output)
• OUT Mode
4. DO Output Data
No.
Control block/data
I/O port data
I2, I1
(1)
Functions
• Latched from the pin states of the IO1 and IO2 I/O ports.
• These values follow the pin states regardless of the input or output setting.
• Data is latched at the point where the circuit enters data output mode (OUT mode).
I1 ← IO1 pin state
I2 ← IO2 pin state
Related data
IOC1,
IOC2
High: 1
Low: 0
(2)
PLL unlock data
UL
• Latched from the state of the unlock detection circuit.
UL ← 0: Unlocked
UL ← 1: Locked or detection stopped mode
UL0,
UL1
(3)
IF counter binary data
C19 to C0
• Latched from the value of the IF counter (20-bit binary counter).
C19 ← MSB of the binary counter
C0 ← LSB of the binary counter
CTE,
GT0,
GT1
No. 5427-11/22
LC72133M, 72133V
5. Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs, tLC < 0.75 µs
6. Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs, tDC, tDH < 0.35 µs
Note: Since the DO pin is an n-channel open-drain circuit, the time for the data to change (tDC and tDH) will differ depending on the value of the pull-up
resistor and printed circuit, board capacitance.
No. 5427-12/22
LC72133M, 72133V
7. Serial Data Timing
Parameter
Symbol
Pins
Conditions
min
typ
max
Unit
Data setup time
tSU
DI, CL
0.75
µs
Data hold time
tHD
DI, CL
0.75
µs
Clock low-level time
tCL
CL
0.75
µs
Clock high-level time
tCH
CL
0.75
µs
CE wait time
tEL
CE, CL
0.75
µs
CE setup time
tES
CE, CL
0.75
µs
CE hold time
tEH
CE, CL
0.75
Data latch change time
tLC
tDC
DO, CL
tDH
DO, CE
Data output time
Differs depending on the
value of the pull-up resistor
and the printed circuit board
capacitances.
µs
0.75
µs
0.35
µs
No. 5427-13/22
LC72133M, 72133V
Programmable Divider Structure
DVS
SNS
Input pin
Set divisor
Actual divisor: N
A
1
*
FMIN
272 to 65535
Twice the set value
Input frequency range (MHz)
B
0
1
AMIN
272 to 65535
The set value
2 to 40
C
0
0
AMIN
4 to 4095
The set value
0.5 to 10
10 to 130
Note: * Don’t care.
1. Programmable Divider Calculation Examples
• FM, 50 kHz steps (DVS = 1, SNS = *, FMIN selected)
FM RF = 80.0 MHz (IF = –10.7 MHz)
FM VCO = 69.3 MHz
PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0)
69.3 MHz (FM VCO) ÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 1386 → 056A (HEX)
• SW, 5 kHz steps (DVS = 0, SNS = 1, AMIN high speed side selected)
SW RF = 21.75 MHz (IF = +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2 MHz (SW VCO) ÷ 5 kHz (fref) = 4440 → 1158 (HEX)
• MW, 10 kHz steps (DVS = 0, SNS = 0, AMIN low-speed side selected)
MW RF = 1000 kHz (IF = +450 kHz)
MW VCO = 1450 kHz
PLL fref = 10 kHz (R0 to R2 = 0, R3 = 1)
1450 kHz (MW VCO) ÷ 10 kHz (fref) = 145 → 091 (HEX)
No. 5427-14/22
LC72133M, 72133V
IF Counter Structure
The LC72133 IF counter is a 20-bit binary counter. The result, i.e., the counter’s MSB, can be read serially from the DO
pin.
Measurement time
GT1
GT0
0
0
4
3 to 4
0
1
8
3 to 4
Measurement period (GT) (ms)
Wait time (twu) (ms)
1
0
32
7 to 8
1
1
64
7 to 8
The IF frequency (Fc) is measured by determining how many pulses were input to an IF counter in a specified
measurement period, GT.
Fc =
C
GT
(C = Fc × GT)
C: Count value (number of pulses)
1. IF Counter Frequency Calculation Examples
• When the measurement period (GT) is 32 ms, the count (C) is 53980 hexadecimal (342400 decimal):
IF frequency (Fc) = 342400 ÷ 32 ms = 10.7 MHz
• When the measurement period (GT) is 8 ms, the count (C) is E10 hexadecimal (3600 decimal):
IF frequency (Fc) = 3600 ÷ 8 ms = 450 kHz
No. 5427-15/22
LC72133M, 72133V
2. IF Counter Operation
Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.
The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the
LC72133 when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period
between the point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF counter at
the end of the measurement period must be read out during the period that CTE is 1. This is because the IF counter is
reset when CTE is set to 0.
Note: When operating the IF counter, the control microprocessor must first check the state of the IF-IC SD (station
detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an
IF count operation. Autosearch techniques that use only the IF counter are not recommended, since it is
possible for IF buffer leakage output to cause incorrect stops at points where there is no station.
IFIN minimum input sensitivity standard
f (MHz)
0.4 ≤ f < 0.5
0.5 ≤ f < 8
8 ≤ f ≤ 12
1: Normal mode
70 mVrms
(0.5 to 5 mVrms)
70 mVrms
70 mVrms
(2 to 10 mVrms)
0: Degradation mode
100 mVrms
(10 to 15 mVrms)
100 mVrms
100 mVrms
(30 to 50 mVrms)
IFS
Note: Values in parentheses are actual performance values presented as reference data.
No. 5427-16/22
LC72133M, 72133V
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle,
unlock determination requires a time longer than the period of the reference frequency. However, immediately after
changing the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the
reference frequency.
Figure 1 Unlocked State Detection Timing
For example, if fref is 1 kHz, i.e., the period is 1 ms, after changing the divisor N, the system must wait at least 2 ms
before checking for the unlocked state.
Figure 2 Circuit Structure
No. 5427-17/22
LC72133M, 72133V
2. Unlock Detection Software
Figure 3
3. Unlocked State Data Output Using Serial Data Output
In the LC72133, once an unlocked state occurs, the unlocked state serial data (UL) will not be reset until a data input
(or output) operation is performed. At the data output ① point in Figure 3, although the VCO frequency has
stabilized (locked), since no data output has been performed since the divisor N was changed the unlocked state data
remains in the unlocked state. As a result, even though the frequency has stabilized (locked), the system remains
(from the standpoint of the data) in the unlocked state.
Therefore, the unlocked state data acquired at data output ①, which occurs immediately after the divisor N was
changed, should be treated as a dummy data output and ignored. The second data output (data output ➁) and
following outputs are valid data.
Locked State Determination Flowchart
4. Directly Outputting Unlocked State Data from the DO Pin (Set by the DO pin control data)
Since the locking state (high = locked, low = unlocked) is output directly from the DO pin, the dummy data
processing described in section 3 above is not required. After changing the divisor N, the locking state can be
checked after waiting at least two reference frequency periods.
No. 5427-18/22
LC72133M, 72133V
Clock Time Base Usage Notes
The pull-up resistor used on the clock time base output pin (BO1) should be at least 100 kΩ. Also, to prevent chattering
we recommend using a Schmitt input at the controller (microprocessor) that receives this signal.
This is to prevent degrading the VCO C/N characteristics when a loop filter is formed using the built-in low-pass filter
transistor. Since the clock time base output pin and the low-pass filter have a common ground internal to the IC, it is
necessary to minimize the time base output pin current fluctuations and to suppress their influence on the low-pass filter.
Other Items
1. Notes on the Phase Comparator Dead Zone
DZ1
DZ0
Dead zone mode
Charge pump
Dead zone
0
0
DZA
ON/ON
– –0 s
0
1
DZB
ON/ON
–0 s
1
0
DZC
OFF/OFF
+0 s
1
1
DZD
OFF/OFF
+ +0 s
Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the
ON/ON state, the loop can easily become unstable. This point requires special care when designing application
circuits.
The following problems may occur in the ON/ON state.
• Side band generation due to reference frequency leakage
• Side band generation due to both the correction pulse envelope and low frequency leakage
Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that acquiring a
high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in
which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA
or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in
which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD,
which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which
either AM stereo is not used or an adequate AM stereo pilot margin can be achieved.
No. 5427-19/22
LC72133M, 72133V
Dead Zone
The phase comparator compares fp to a reference frequency (fr) as shown in Figure 4. Although the characteristics of
this circuit (see Figure 5) are such that the output voltage is proportional to the phase difference ø (line A), a region
(the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal
circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide
a high S/N ratio.
However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the
VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit
outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF
signal.
Figure 4
Figure 5
2. Notes on the FMIN, AMIN, and IFIN Pins
Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100 pF is
desirable. In particular, if a capacitance of 1000 pF or over is used for the IF pin, the time to reach the bias level will
increase and incorrect counting may occur due to the relationship with the wait time.
3. Notes on IF Counting → SD must be used in conjunction with the IF counting time
When using IF counting, always implement IF counting by having the microprocessor determine the presence of the
IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which
auto-searches are performed with only IF counting are not recommended, since they can stop at points where there is
no signal due to leakage output from the IF counter buffer.
4. DO Pin Usage Techniques
In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for
unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the
controller.
5. Power Supply Pins
A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS pins for noise exclusion.
This capacitor must be placed as close as possible to the VDD and VSS pins.
No. 5427-20/22
LC72133M, 72133V
Pin States After the Power ON Reset
Application System Example
No.5427-21/22
LC72133M, 72133V
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
① Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
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damages, cost and expenses associated with such use:
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SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No.5427-22/22