Ordering number : EN5378 CMOS LSI LC72322R, 72323R Single-Chip Microcontroller with PLL and LCD Driver Overview The LC72322R and LC72323R are single-chip microcontrollers for use in electronic tuning applications. These ICs include on chip both LCD drivers and a PLL circuit that can operate at up to 150 MHz. The LC72322R and LC72323R feature that these ICs are reversed pinassignment versions of LC72322 and LC72323 respectively and have the equal functions and specifications to theirs respectively. • • Functions • Stack: Eight levels • Fast programmable divider • General-purpose counters: HCTR for frequency measurement and LCTR for frequency or period measurement • LCD driver for displays with up to 56 segments (1/2 duty, 1/2 bias) • Program memory (ROM): 4095 (8 KB) 16-bit digits: LC72322R 3071 (6 KB) 16-bit digits: LC72323R • Data memory (RAM): 256 4-bit digits • All instructions are single-word instructions • Cycle time: 2.67 µs, 13.33 µs, or 40.00 µs (option) • Unlock FF: 0.55 µs detection, 1.1 µs detection • Timer FF: 1 ms, 5ms, 25ms, 125ms • Input ports*: One dedicated key input port and one high-breakdown voltage port • Output ports*: Two dedicated key output ports, one high-breakdown voltage open-drain port • • • • • • • • • • • Two CMOS output ports (of which one can be switched to be used as LCD driver outputs) Seven CMOS output ports (mask option switchable to use as LCD ports) I/O ports*: One switchable between input and output in four-bit units and one switchable between input and output in bit units Note: * Each port consists of four bits. Program runaway can be detected and a special address set (Programmable watchdog timer). Voltage detection type reset circuit One 6-bit A/D converter Two 8-bit D/A converters (PWM): LC72322R only One external interrupt Hold mode for RAM backup Sense FF for hot/cold startup determination PLL: 4.5 to 5.5 V CPU: 3.5 to 5.5 V RAM: 1.3 to 5.5 V LC72P321R as OTP used Package: QIP80DR Package Dimensions unit: mm 3223-QFP80DR [LC72322R, LC72323R] This LSI can easily use CCB that is SANYO’s original bus format. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO: QIP80DR SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5378-1/13 LC72322R, 72323R Pin Assignment No. 5378-2/13 LC72322R, 72323R Block Diagram No. 5378-3/13 LC72322R, 72323R Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings VDD max Input voltage Output voltage Output current Allowable power dissipation VIN1 HOLD, INT, RES, ADI, SNS, and the G port VIN2 Inputs other than VIN1 Unit –0.3 to +6.5 V –0.3 to +13 V –0.3 to VDD + 0.3 V VOUT1 H port VOUT2 Outputs other than VOUT1 IOUT1 All D and H port pins 0 to 5 mA IOUT2 All E and F port pins 0 to 3 mA IOUT3 All B and C port pins 0 to 1 mA IOUT4 S1 to S28 and all I port pins 0 to 1 mA 300 mW Pd max –0.3 to +15 V –0.3 to VDD + 0.3 V Ta = –40 to +85°C Operating temperature Topr –40 to +85 °C Storage temperature Tstg –45 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 3.5 to 5.5 V Ratings Parameter Supply voltage Input high level voltage Input low level voltage Input frequency Input amplitude Input voltage range Symbol Conditions min typ Unit max VDD1 CPU and PLL operating 4.5 5.5 V VDD2 CPU operating 3.5 5.5 V VDD3 Memory retention voltage 1.3 5.5 V VIH1 G port 0.7 VDD 8.0 V VIH2 RES, INT, HOLD 0.8 VDD 8.0 V VIH3 SNS 2.5 8.0 V VIH4 A port 0.6 VDD VDD V VIH5 PE0, PE2 and F ports 0.7 VDD VDD V VIH6 LCTR (period measurement), VDD1, PE1 and PE3 0.8 VDD VDD V VIL1 G port 0 0.3 VDD V VIL2 RES, INT, PE1, PE3 0 0.2 VDD V VIL3 SNS 0 1.3 V VIL4 A port 0 0.2 VDD V VIL5 PE0, PE2 and F ports 0 0.3 VDD V VIL6 LCTR (period measurement), VDD1 0 0.2 VDD V VIL7 HOLD 0 0.4 VDD fIN1 XIN 4.0 4.5 V 5.0 MHz fIN2 FMIN, VIN2, VDD1 10 130 MHz fIN3 FMIN, VIN3, VDD1 10 150 MHz fIN4 AMIN (L), VIN4, VDD1 0.5 10 MHz fIN5 AMIN (H), VIN5, VDD1 2.0 40 MHz fIN6 HCTR, VIN6, VDD1 0.4 12 MHz fIN7 LCTR (frequency), VIN7, VDD1 100 500 kHz fIN8 LCTR (period), VIH6, VIL6, VDD1 1 20 × 103 VIN1 XIN 0.50 1.5 Vrms Vrms Hz VIN2 FMIN 0.10 1.5 VIN3 FMIN 0.15 1.5 Vrms VIN4, 5 AMIN 0.10 1.5 Vrms VIN6, 7 LCTR, HCTR 0.10 1.5 Vrms 0 VDD V VIN8 ADI No. 5378-4/13 LC72322R, 72323R Electrical Characteristics for the Allowable Operating Ranges Ratings Parameter Hysteresis Symbol VH Rejected pulse width PREJ Power-down detection voltage VDET Input high level current Input low level current Conditions LCTR (period), RES, INT, PE1, PE3 min typ Unit max 0.1 VDD V SNS 2.7 3.0 50 µs 3.3 V IIH1 INT, HOLD, RES, ADI, SNS, and G port: VI = 5.5 V 3.0 µA IIH2 A, E, and F ports: E and F ports with outputs off, A port with no RPD, VI = VDD 3.0 µA IIH3 XIN: VI = VDD = 5.0 V 2.0 5.0 15 µA IIH4 FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V 4.0 10 30 µA IIH5 A port: With an RPD, VI = VDD = 5.0 V IIL1 INT, HOLD, RES, ADI, SNS, and the G port: VI = VSS 3.0 µA IIL2 A, E, and F ports: E and F ports with outputs off, A port with no RPD, VI = VSS 3.0 µA 50 µA IIL3 XIN: VIN = VSS 2.0 5.0 15 µA IIL4 FMIN, AMIN, HCTR, LCTR: VI = VSS 4.0 10 30 µA Input floating voltage VIF A port: With an RPD Pull-down resistance RPD A port: With an RPD, VDD = 5.0 V Output high level off leakage current Output low level off leakage current Output high level voltage Output low level voltage Output middle level voltage 75 100 V 200 kΩ IOFFH1 EO1, EO2: VO = VDD 10 nA IOFFH2 B, C, D, E, F, and I ports: VO = VDD 3.0 µA IOFFH3 H port: VO = VDD 5.0 µA IOFFL1 EO1, EO2: VO = VSS 0.01 10 nA 3.0 µA VDD – 1.0 VDD – 0.5 0.01 IOFFL2 B, C, D, E, F, and I ports: VO = VSS VOH1 B and C ports: IO = 1 mA VDD – 2.0 VOH2 E and F ports: IO = 1 mA VDD – 1.0 V VOH3 EO1, EO2: IO = 500 µA VDD – 1.0 V VOH4 XOUT: IO = 200 µA VDD – 1.0 V VOH5 S1 to S28 and the I port: IO = –0.1 mA VDD – 1.0 V VOH6 D port: IO = 5 mA VDD – 1.0 VOH7 COM1, COM2: IO = 25 µA VDD – 0.75 VDD – 0.5 VDD – 0.3 V VOL1 B and C ports: IO = 50 µA 0.5 1.0 2.0 V VOL2 E and F ports: IO = 1 mA 1.0 V VOL3 EO1, EO2: IO = 500 µA 1.0 V VOL4 XOUT: IO = 200 µA 1.0 V V V VOL5 S1 to S28 and the I port: IO = 0.1 mA 1.0 V VOL6 D port: IO = 5 mA 1.0 V VOL7 COM1, COM2: IO = 25 µA 0.75 V VOL8 H port: IO = 5 mA, VDD1 VM1 COM1, COM2: VDD = 5.0 V, IO = 25 µA IDD1 VDD1, fIN2 = 130 MHz 15 IDD2 VDD2, PLL stopped, CT = 2.67 µs (HOLD mode, Figure 1) 1.5 mA IDD3 VDD2, PLL stopped, CT = 13.33 µs (HOLD mode, Figure 1) 1.0 mA IDD4 VDD2, PLL stopped, CT = 40.00 µs (HOLD mode, Figure 1) 0.7 mA A/D conversion error Current drain 0.05 VDD ADI: VDD1 IDD5 0.3 0.5 (150 Ω) 0.75 2.0 2.5 –1/2 (400 Ω) 2.0 V 3.0 V +1/2 LSB 20 mA VDD = 5.5 V, oscillator stopped, Ta = 25°C (BACK UP mode, Figure 2) 5 µA VDD = 2.5 V, oscillator stopped, Ta = 25°C (BACK UP mode, Figure 2) 1 µA No. 5378-5/13 LC72322R, 72323R Test Circuits Note: PB to PF, PH, and PI are all open. However, PE and PF are specified as output. Figure 1 IDD2 to IDD4 in HOLD Mode Note: PA to PI, S1 to S4, COM1, and COM2 are all open. Figure 2 IDD5 in BACK UP Mode No. 5378-6/13 LC72322R, 72323R Pin Functions Pin Pin No. Functions PA0 30 These pins can be used, for example, for key data acquisition. PA1 31 PA2 32 PA3 33 Built-in pull-down resistors can be specified as an option. This option is in 4-pin units, and cannot be specified for individual pins. I/O I/O circuit type Low-threshold type dedicated input ports Input Input through these pins is disabled in BACKUP mode. PB0 35 PB1 36 Dedicated output ports PB2 37 PB3 38 PC0 39 Since the output transistor impedances are unbalanced CMOS, these pins can be effectively used for functions such as key scan timing. These pins go to the output highimpedance state in BACKUP mode. PC1 40 PC2 41 PC3 42 PD0 43 Dedicated output ports PD1 44 PD2 45 These are normal CMOS outputs. These pins go to the output high-impedance state in BACKUP mode. PD3 46 These pins go to the low level during a reset, i.e., when the RES pin is low. Output These pins go to the low level during a reset, i.e., when the RES pin is low. I/O ports PE0 47 PE1 48 PE2 49 PE3 50 These pins are switched between input and output as follows: Once an input instruction (IN, TPT, or TPF) is executed, these pins latch in the input mode. Once an output instruction (OUT, SPB, or RPB) is executed, they latch in the output mode. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACKUP mode these pins go to the input mode with input disabled. I/O I/O ports PF0 51 These pins are switched between input and output by the FPC instruction. PF1 52 The I/O states of this port can be specified for individual pins. PF2 53 PF3 54 These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACKUP mode these pins go to the input mode with input disabled. PG0 59 PG1 60 Dedicated input ports PG2 61 Input through these pins is disabled in BACKUP mode. PG3 62 Input Continued on next page. No. 5378-7/13 LC72322R, 72323R Continued from preceding page. Pin Pin No. Functions I/O I/O circuit type Dedicated output ports PH0 55 PH1 56 PH2/DAC*1 57 PH3/DAC*2 58 Since these pins are high-breakdown voltage n-channel transistor open-drain outputs, they can be effectively used for functions such as band power supply switching. And, PH2 and PH3 can also be used for DAC1 and DAC2 output ports respectively. (*: DAC is contained in LC72322R only.) Output These ports go to the high impedance state during a reset, i.e., when the RES pin is low, and in BACKUP mode. Dedicated output ports While these pins have a CMOS output circuit structure, they can be switched to function as LCD drivers. Their function is switched by the SS and RS instructions. These pins cannot be switched individually. PI0/S25 26 PI1/S26 27 PI2/S27 28 The LCD driver function is selected and a segment-off signal is output when power is first applied or when RES is low. PI3/S28 29 These pins are held at the low level in BACKUP mode. Output Note that when the general-purpose port use option is specified, these pins output the contents of IPORT when LPC is 1, and the contents of the general-purpose output port LATCH when LPC is 0. LCD driver segment outputs A frame frequency of 100 Hz and a 1/2 duty, 1/2 bias drive type are used. S1 to S24 2 to 25 A segment-off signal is output when power is first applied or when RES is low. Output These pins are held at the low level in BACKUP mode. The use of these pins as general-purpose output ports can be specified as an option. LCD driver common outputs COM1 80 COM2 1 A 1/2 duty, 1/2 bias drive type is used. The output when power is first applied or when RES is low is identical to the normal operating mode output. Output These pins are held at the low level in BACKUP mode. FMIN 71 FM VCO (local oscillator) input The input must be capacitor coupled. The input frequency range is from 10 to 130 MHz. (Max. 150 MHz) AM VCO (local oscillator) input The input must be capacitor coupled AMIN 70 Input The band supported by this pin can be selected using the PLL instruction. High (2 to 40 MHz) → SW Low (0.5 to 10 MHz) → LW and MW Continued on next page. No. 5378-8/13 LC72322R, 72323R Continued from preceding page. Pin Pin No. Functions I/O I/O circuit type Universal counter input HCTR 75 The input must be capacitor coupled. The input frequency range is from 0.4 to 12 MHz. This input can be effectively used for FM IF or AM IF counting. Universal counter input The input must be capacitor coupled for input frequencies in the range 100 to 150 kHz. LCTR 74 Input Capacitor coupling is not required for input frequencies from 1 Hz to 20 kHz. This input can be effectively used for AM IF counting. A/D converter input ADI 76 A 1.28 ms period is required for a 6-bit sequential comparison conversion. The full scale input is ((63/96) · VDD) for a data value of 3FH. Input External interrupt request input An interrupt is generated when the INTEN flag is set (by an SS instruction) and a falling edge is input. INT 79 EO1 68 Reference frequency and programmable divider phase comparison error outputs EO2 67 Charge pump circuits are built in. Input Output EO1 and EO2 are the same. SNS 73 Input pin used to determine if a power outage has occurred in BACKUP mode Input This pin can also be used as a normal input port. Input pin used to force the ICs to HOLD mode HOLD 78 The IC goes to HOLD mode when the HOLDEN flag is set (by an SS instruction) and the HOLD input goes low. Input A high-breakdown voltage circuit is used so that this input can be used in conjunction with the normal power switch. System reset input RES 77 This signal should be held low for 75 ms after power is first applied to effect a power-up reset. Input The reset starts when a low level has been input for at least six reference clock cycles. XIN 64 XOUT 65 TEST1 66 TEST2 63 VDD 34, 72 VSS 69 Crystal oscillator connections (4.5 MHz) A feedback resistor is built in. Input Output LSI test pins. These pins must be connected to VSS. — Power supply — No. 5378-9/13 LC72322R, 72323R Mask Options No. 1 Description WDT (watchdog timer) inclusion selection 2 Port A pull-down resistor inclusion selection 3 Cycle time selection Selections WDT included No WDT Pull-down resistors included No pull-down resistors 2.67 µs 13.33 µs 40.00 µs 4 LCD port/general-purpose port selection LCD ports General-purpose output ports Development Environment • The LC72P321R is used for OTP. • The LC72EV321 is used as the evaluation chip. • A total debugging system is available in which the TB-72EV32 evaluation chip board and the RE32 multifunction emulator are controlled by a personal computer. No. 5378-10/13 LC72322R, 72323R LC72322R, 72323R Instruction Table Instruction Group Abbreviations: ADDR: Program memory address [12 bits] b: Borrow B: Bank number [2 bits] C: Carry DH: Data memory address high (row address) [2 bits] DL: Data memory address low (column address) [4 bits] I: Immediate data [4 bits] M: Data memory address N: Bit position [4 bits] Pn: Port number [4 bits] r: General register (one of the locations 00 to 0FH in bank 0) Rn: Register number [4 bits] ( ): Contents of register or memory ( )N: Contents of bit N of register or memory Operand Subtraction instructions Addition instructions AD Comparison instructions Machine code Mnemonic Function Operation 1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 r M Add M to r r ← (r) + (M) 0 1 0 0 0 0 Add M to r, then skip if carry r ← (r) + (M) skip if carry DH DL Rn 0 1 0 0 0 1 DH DL Rn ADS r M AC r M Add M to r with carry r ← (r) + (M) + C 0 1 0 0 1 0 DH DL Rn Add M to r with carry, then skip if carry r ← (r) + (M) + C skip if carry 0 1 0 0 1 1 DH DL Rn ACS r M AI M I Add I to M M ← (M) + I 0 1 0 1 0 0 DH DL I Add I to M, then skip if carry M ← (M) + I skip if carry 0 1 0 1 0 1 DH DL I AIS M I AIC M I Add I to M with carry M ← (M) + I + C 0 1 0 1 1 0 DH DL I Add I to M with carry, then skip if carry M ← (M) + I + C skip if carry 0 1 0 1 1 1 DH DL I AICS M I SU r M Subtract M from r r ← (r) – (M) 0 1 1 0 0 0 DH DL Rn r ← (r) – (M) skip if borrow 0 1 1 0 0 1 DH DL Rn SUS r M Subtract M from r, then skip if borrow SB r M Subtract M from r with borrow r ← (r) – (M) – b 0 1 1 0 1 0 DH DL Rn SBS r M Subtract M from r with borrow, then skip if borrow r ← (r) – (M) – b skip if borrow 0 1 1 0 1 1 DH DL Rn SI M I Subtract I from M M ← (M) – I 0 1 1 1 0 0 DH DL I M ← (M) – I skip if borrow 0 1 1 1 0 1 DH DL I SIS M I Subtract I from M, then skip if borrow SIB M I Subtract I from M with borrow M ← (M) – I – b 0 1 1 1 1 0 DH DL I SIBS M I Subtract I from M with borrow, then skip if borrow M ← (M) – I – b skip if borrow 0 1 1 1 1 1 DH DL I SEQ r M Skip if r equals M r–M skip if zero 0 0 0 0 0 1 DH DL Rn SGE r M Skip if r is greater than or equal to M r–M skip if not borrow (r) ≥ (M) 0 0 0 0 1 1 DH DL Rn SEQI M I Skip if M equal to I M–I skip if zero 0 0 1 1 0 1 DH DL I SGEI M I Skip if M is greater than or equal to I M–I skip if not borrow (M) ≥ I 0 0 1 1 1 1 DH DL I Continued on next page. No. 5378-11/13 LC72322R, 72323R Operand Mnemonic Machine code Function Operation 1st 2nd D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 AND M I AND I with M M ← (M) I 0 0 1 1 0 0 DH DL I OR M I OR I with M M ← (M) I 0 0 1 1 1 0 DH DL I EXL r M Exclusive OR M with r r ← (r) (M) 0 0 1 0 0 0 DH DL Rn LD r M Load M to r r ← (M) 1 0 0 0 0 0 DH DL Rn ST M r Store r to M M ← (r) 1 0 0 0 0 1 DH DL Rn MVRD r M Move M to destination M referring to r in the same row [DH, Rn] ← (M) 1 0 0 0 1 0 DH DL Rn MVRS M r Move source M referring to r to M in the same row M ← [DH, Rn] 1 0 0 0 1 1 DH DL Rn MVSR M1 M2 Move M to M in the same row [DH, DL1] ← [DH, DL2] 1 0 0 1 0 0 DH DL1 DL2 MVI M I Move I to M M←I 1 0 0 1 0 1 DH DL I PLL r ← PLL DATA 1 0 0 1 1 0 DH DL Rn M r M N Test M bits, then skip if all bits specified are true if M (N) = all 1, then skip 1 0 1 0 0 1 DH DL N TMF M N Test M bits, then skip if all bits specified are false if M (N) = all 0, then skip 1 0 1 0 1 1 DH DL N TMT JMP ADDR Jump to the address PC ← ADDR 1 0 1 1 ADDR (12 bits) CAL ADDR Call subroutine Stack ← (PC) + 1 1 1 0 0 ADDR (12 bits) Return from subroutine PC ← Stack 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Return from interrupt BANK ← Stack PC ← Stack CARRY ← Stack 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 N Bank switching instructions Status register instructions F/F test instructions Bit test instructions PLL Load M to PLL registers Jump and subroutine call Transfer instructions Logical operation instructions Instruction Group Continued from preceding page. RT RTI TTM N Test timer F/F then skip if it has not been set if timer F/F = 0, then skip 1 1 0 1 0 1 1 0 0 0 0 0 TUL N Test unlock F/F then skip if it has not been set if UL F/F = 0, then skip 1 1 0 1 0 1 1 1 0 0 0 0 N SS N Set status register (Status register 1) N←1 1 1 0 1 1 1 0 0 0 0 0 0 N RS N Reset status register (Status register 1) N←0 1 1 0 1 1 1 0 1 0 0 0 0 N TST N Test status register true if (Status register 2) N = all 1, then skip 1 1 0 1 1 1 1 0 0 0 0 0 N TSF N Test status register false if (Status register 2) N = all 0, then skip 1 1 0 1 1 1 1 1 0 0 0 0 N BANK B Select bank BANK ← B 1 1 0 1 0 0 B 0 0 0 0 0 0 0 Continued on next page. No. 5378-12/13 LC72322R, 72323R Other instructions Universal counter instructions I/O instructions Instruction Group Continued from preceding page. Operand Machine code Mnemonic Function Operation 1st 2nd D15 14 13 12 11 10 9 8 LCD M I Output segment pattern to LCD digit direct LCD (DIGIT) ← M 1 1 1 0 0 0 LCP M I Output segment pattern to LCD digit through PLA LCD (DIGIT) ← PLA ← M 1 1 1 0 0 1 7 6 5 4 3 2 1 D0 DH DL DIGIT DH DL DIGIT IN M P Input port data to M M ← (Port (P)) 1 1 1 0 1 0 DH DL P OUT M P Output contents of M to port (Port (P)) ← M 1 1 1 0 1 1 DH DL P SPB P N Set port bits (Port (P)) N ← 1 1 1 1 1 0 0 0 0 P N RPB P N Reset port bits (Port (P)) N ← 0 1 1 1 1 0 1 0 1 P N TPT P N Test port bits, then skip if all bits specified are true if (Port (P)) N = all 1, then skip 1 1 1 1 1 0 1 0 P N TPF P N Test port bits, then skip if all bits specified are false if (Port (P)) N = all 0, then skip 1 1 1 1 1 1 1 1 P N UCS I Set I to UCCW1 UCCW1 ← I 0 0 0 0 0 0 0 1 0 0 0 0 I UCC I Set I to UCCW2 UCCW2 ← I 0 0 0 0 0 0 1 1 0 0 0 0 I FPC N F port I/O control FPC latch ← N 0 0 0 1 0 0 0 0 0 0 0 0 Clock stop Stop clock if HOLD = 0 0 0 0 1 0 0 0 1 0 0 0 0 Load M to D/A registers DA reg ← DAC DATA 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKSTP DAC* NOP I No operation N 0 0 0 0 I 0 0 0 0 Note: * DAC is contained in LC72322R only. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5378-13/13