Ordering number : EN4841C CMOS LSI LC74723, 74723M On-Screen Display Controller Overview Package Dimensions The LC74723 and LC74723M are on-screen display controller CMOS LSIs that display characters and patterns on a TV screen under microprocessor control. Characters are 8 × 8 dots, and a dot interpolation function is provided. The LC74723 can display 24 characters × 10 lines of text. unit: mm 3067-DIP24S [LC74723] Features • Screen structure: 24 characters × 10 lines (up to 240 characters) • Character structure: 8 (horizontal) × 8 (vertical) (interpolation function supported) • Character sizes: Two horizontal and two vertical sizes • Number of characters: 64 • Display start position: 64 horizontal and 64 vertical positions • Blinking: In character units • Blinking types: Two, with periods of 0.5 and 1.0 seconds • Blue background screen display: (in internal synchronization mode) • External control inputs: 8-bit serial input interface • Built-in sync separator circuit • Video output: Compound NTSC and PAL-M output • Packages: 24-pin plastic MFP (375 mil) 24-pin plastic DIP (300 mil) SANYO: DIP24S unit: mm 3045B-MFP24 [LC74723M] SANYO: MFP24 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 63097HA (OT)/41596TH (OT)/83194TH (OT) No. 4841-1/12 LC74723, 74723M Pin Assignment Pin Functions Pin No. Symbol 1 VSS1 2 XtalIN 3 XtalOUT 4 CTRL1 5 CSYNOUT Function Description Ground Ground (digital system ground) Crystal oscillator connection Used either for connecting the external crystal and capacitor that are used for internal synchronization signal generation, or to input an external clock signal (2fsc or 4fsc). Crystal oscillator input switching Switches the LC74723 between external clock input mode and crystal oscillator mode. Low = crystal oscillator mode, high = external clock mode Composite synchronization signal output Outputs a composite synchronization signal. Outputs the crystal oscillator clock on reset, i.e., when RST is low. LC oscillator Connections for the coil and capacitor that form the oscillator used to generate the character output dot clock. External synchronization signal judgment output Outputs the result of judging whether or not there is an external synchronization signal. Outputs a high level when an external synchronization signal is present. Outputs the dot clock (LC oscillator) on reset, i.e., when RST is low. (The LC74723 can be set not to output this signal on reset using control data.) Enable input Enables serial data input. Serial data input is enabled when this input is low. There is a built-in pull-up resistor on this input (hysteresis input). Inputs the clock signal used for serial data input. There is a built-in pull-up resistor on this input (hysteresis input). 6 OSCIN 7 OSCOUT 8 SYNCJDG 9 CS 10 SCLK Clock input 11 SIN Data input Serial data input. There is a built-in pull-up resistor on this input (hysteresis input). Power supply Power supply (analog system power supply) for composite video signal level adjustment. Video signal output Composite video signal output 12 VDD2 13 CVOUT 14 NC 15 CVIN Video signal input Composite video signal input 16 VDD1 Power supply Power supply (+5 V: digital system power supply) 17 SYNIN Sync separator circuit input Video signal input for the built-in sync separator circuit (When the built-in sync separator circuit is not used, input either the horizontal synchronization signal or the composite synchronization signal.) 18 SEPC Sync separator circuit bias voltage Built-in sync separator circuit bias voltage monitor 19 SEPOUT 20 SEPIN Must be either connected to ground or left open. Composite synchronization signal output Outputs the built-in sync separator circuit's composite synchronization signal. (Outputs the SYNIN input signal when the built-in sync separator circuit is not used.) Vertical synchronization signal input Inputs the vertical synchronization signal by integrating the output signal from the SEPOUT pin. An integration circuit must be connected between the SEPOUT pin and this pin. Hold at VDD1 if this input is unused. Continued on next page. No. 4841-2/12 LC74723, 74723M Continued from preceding page. Pin No. Symbol Function Description 21 CTRL2 NTSC/PAL-M switch input Switches the synchronization signal generation between NTSC and PAL-M. Low = NTSC, high = PAL-M 22 CTRL3 SEPIN input control Controls whether the VSYNC signal is input to SEPIN. Low = Input VSYNC, high = do not input. 23 RST Reset input System reset input There is a built-in pull-up resistor on this input (hysteresis input). 24 VDD1 Power supply (+5 V) Power supply (+5 V: digital system power supply) Note: * Both the VDD1 pins (pins 16 and 24) must be connected. Specifications Absolute Maximum Ratings at Ta = 25°C Ratings Unit Maximum supply voltage Parameter VDD max Symbol VDD1, VDD2 VSS – 0.3 to VSS + 7.0 V Maximum input voltage VIN max All input pins VSS – 0.3 to VDD + 0.3 V CSYNOUT, SYNCJDG, SEPOUT VSS – 0.3 to VDD + 0.3 Maximum output voltage VOUT max Allowable power dissipation Pd max Conditions Ta = 25°C 350 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C max Unit Allowable Operating Ranges at Ta = –30 to +70°C Parameter Supply voltage Input high level voltage Input low level voltage Pull-up resistance Composite video input voltage Input voltage Oscillator frequency Symbol Conditions min typ VDD1 VDD1 4.5 5.0 5.5 VDD2 VDD2 4.5 5.0 1.27 VDD1 V VIH1 RST, CS, SIN, SCLK 0.8 VDD1 VDD1 + 0.3 V VIH2 CTRL1, CTRL2, CTRL3, SEPIN 0.7 VDD1 VDD1 + 0.3 V VIL1 RST, CS, SIN, SCLK VSS – 0.3 0.2 VDD1 V VIL2 CTRL1, CTRL2, CTRL3, SEPIN VSS – 0.3 0.3 VDD1 V RPU Applies to the RST, CS, SIN, and SCLK pins and to the pins specified by options. 25 50 90 V kΩ VIN1 CVIN; VDD1 = 5 V 2.0 VIN2 SYNIN; VDD1 = 5 V 2.0 VIN3 XtalIN (when external clock input is used) fin = 2fsc or 4fsc; VDD1 = 5 V fosc1 XtalIN and XtalOUT oscillator pins (2fsc: NTSC) 7.159 MHz fosc1 XtalIN and XtalOUT oscillator pins (4fsc: NTSC) 14.318 MHz fosc1 XtalIN and XtalOUT oscillator pins (2fsc: PAL-M) 7.151 MHz fosc1 XtalIN and XtalOUT oscillator pins (4fsc: PAL-M) 14.302 fosc2 OSCIN and OSCOUT oscillator pins (LC oscillator) Vp-p 0.1 2.5 Vp-p 5.0 Vp-p MHz 5 12 MHz Note: When the XtalIN pin is used in clock input mode, be extremely careful of input noise. Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified max Unit Input off leakage current Parameter Ileak1 CVIN 1 µA Output off leakage current Ileak2 CVOUT 1 µA Output high level voltage VOH1 CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOH = –1.0 mA Output low level voltage VOL1 CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOL = 1.0 mA Input current Current drain (operating) Symbol Conditions IIH RST, CS, SIN, SCLK, CTRL1, CTRL2, CTRL3, SEPIN; VIN = VDD1 IIL CTRL1, CTRL2, CTRL3, OSCIN; VIN = VSS1 min typ 3.5 V 1.0 V 1 µA –1 µA IDD1 VDD1; All outputs open, Xtal: 7.159 MHz, LC: 8 MHz 15 mA IDD2 VDD2; VDD2 = 5 V 20 mA Continued on next page. No. 4841-3/12 LC74723, 74723M Continued from preceding page. Parameter Sync level Symbol VSN Pedestal level Color burst low level Color burst high level Background color low level Background color high level Trimming level 0 Trimming level 1 Character level VPD VCBL VCBH VRSL VRSH VBK0 VBK1 VCHA min typ When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V Conditions 0.69 0.81 0.93 max Unit V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 0.89 1.01 1.13 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.28 1.40 1.52 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.47 1.59 1.71 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 0.97 1.09 1.21 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.16 1.28 1.40 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.60 1.72 1.84 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.79 1.91 2.03 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.44 1.56 1.68 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.63 1.75 1.87 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.96 2.08 2.20 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 2.16 2.28 2.40 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 1.43 1.55 1.67 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 1.61 1.73 1.85 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 2.01 2.13 2.25 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 2.18 2.30 2.42 V When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V 2.57 2.69 2.81 V When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V 2.76 2.88 3.00 V min typ Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V Parameter Minimum input pulse width Data setup time Data hold time One word write time Symbol tW (SCLK) Conditions SCLK tW (CS) CS (the period while CS is high) max Unit 200 ns 1 µs ns tSU (CS) CS 200 tSU (SIN) SIN 200 ns th (CS) CS 2 µs th (SIN) SIN 200 ns The time to write 8 bits of data 4.2 µs 1 µs tword twt The RAM data write time Serial Data Input Timing No. 4841-4/12 Sync separator Character output dot clock generator Composite synchronization signal separation control Sync detector 8-bit latch + command decoder Line control counter Character control counter Synchronization signal generator Vertical display position detection Horizontal display position detection Timing generator Vertical dot counter Horizontal dot counter Vertical size counter Horizontal size counter Vertical display position register Horizontal display position register Vertical direction character size register Horizontal direction character size register Display control register Character output control Background control Video output control Blinking and reversal control circuit Blinking and reversal control register RAM write address counter Decoder Serial to parallel converter Shift register Font ROM Decoder Display RAM LC74723, 74723M System Block Diagram No. 4841-5/12 LC74723, 74723M Display Control Commands Display control commands are input as serial data in 8-bit units. Commands consist of a first byte that includes the command identifier code and data in the following second byte. The LC74723 supports the following six commands. 1. 2. 3. 4. 5. 6. COMMAND0: Set display memory (VRAM) write address COMMAND1: Set up display character data write COMMAND2: Set vertical display start position and vertical character size COMMAND3: Set horizontal display start position and horizontal character size COMMAND4: Display control COMMAND5: Display control Display Control Command Table First byte Command Second byte Command identifier code Data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 COMMAND0 (Set write address) 1 0 0 0 V3 V2 V1 V0 0 0 0 H4 H3 H2 H1 H0 COMMAND1 (Write character) 1 0 0 1 0 0 0 0 at 0 c5 c4 c3 c2 c1 c0 COMMAND 2 (Vertical display start position and vertical character size) 1 0 1 0 0 VS 20 0 VS 10 0 FS VP 5 VP 4 VP 3 VP 2 VP 1 VP 0 COMMAND3 (Horizontal display start position and horizontal character size) 1 0 1 1 EGP HS 20 0 HS 10 0 LC HP 5 HP 4 HP 3 HP 2 HP 1 HP 0 COMMAND4 (Display control) 1 1 0 0 TST RAM OSC MOD ERS STP SYS RST 0 EGL NON EG BK 1 BK 0 RV DSP ON COMMAND5 (Synchronization signal control) 1 1 0 1 INT — — — — — — — — 0 PH RSN Once written, the command identifier code in the first byte is stored until the next first byte is written. However, when the display character data write command (COMMAND1) is written, the LC74723 locks into the display character data write mode, and another first byte cannot be written. When a high level is input to the CS pin, the LC74723 is set to COMMAND0 (display memory write address setting mode). 1. COMMAND0 (Display memory write address setting command) • First byte Contents DA 0 to 7 Register name State 7 — 1 6 — 0 5 — 0 4 — 0 3 V3 2 V2 1 V1 0 V0 Function Remarks Command 0 identification code Set display memory write address. 0 1 0 1 0 Display memory address (0 to 9 hexadecimal) 1 0 1 No. 4841-6/12 LC74723, 74723M • Second byte Contents DA 0 to 7 Register name State 7 — 0 6 — 0 5 — 0 4 H4 3 H3 2 H2 1 H1 0 H0 Function Remarks Second byte identification code 0 1 0 1 0 1 Display memory address (0 to 17 hexadecimal) 0 1 0 1 Note: The register states are all set to zero when the LC74723 is reset with the RST pin. 2. COMMAND1 (Display character data write setup command) • First byte Contents DA 0 to 7 Register name State 7 — 1 6 — 0 5 — 0 4 — 1 3 — 0 2 — 0 1 — 0 0 — 0 Function Command 1 identification code Set up display character data write. Remarks When this command is input, the LC74723 locks into the display character data write mode until the CS pin goes high. • Second byte DA 0 to 7 Register name 7 at 6 — 5 c5 4 c4 3 c3 2 c2 1 c1 0 c0 Contents State Function 0 Character attribute off 1 Character attribute on Remarks 0 0 1 0 1 0 1 0 Character code (00 to 3F hexadecimal) 1 0 1 0 1 Note: The register states are all set to zero when the LC74723 is reset with the RST pin. No. 4841-7/12 LC74723, 74723M 3. COMMAND2 (Vertical display start position and vertical character size setting command) • First byte Contents DA 0 to 7 Register name State 7 — 1 6 — 0 5 — 1 4 — 0 3 — 0 2 VS20 1 — 0 VS10 Function Remarks Command 2 identification code Set vertical display start position and vertical character size. 0 1H per dot 1 2H per dot Second line vertical character size 0 0 1H per dot 1 2H per dot First line vertical character size • Second byte Contents DA 0 to 7 Register name State 7 — 0 Second byte identification code 0 Crystal oscillator frequency: 2fsc 1 Crystal oscillator frequency: 4fsc 0 If VS is the vertical display start position then: 6 FS 5 VP5 (MSB) 4 VP4 3 VP3 2 VP2 1 VP1 0 VP0 (LSB) 1 0 1 Function Remarks 5 VS = H × (2Σ 2n VPn) n=0 H: the horizontal synchronization pulse period 0 The vertical display start position is set by the 6 bits VP0 to VP5. The weight of the low-order bit is 2H. 1 0 1 0 1 0 1 Note: The register states are all set to zero when the LC74723 is reset with the RST pin. 4. COMMAND3 (Horizontal display start position and horizontal character size setting command) • First byte Contents DA 0 to 7 Register name State 7 — 1 6 — 0 5 — 1 4 — 1 3 EGP 2 HS20 1 — 0 HS10 Function Remarks Command 3 identification code Set horizontal display start position and horizontal character size. 0 Correction: on 1 Correction: off 0 1Tc per dot 1 2Tc per dot Trimming specifications when the horizontal character size is doubled Second line horizontal character size 0 0 1Tc per dot 1 2Tc per dot First line horizontal character size No. 4841-8/12 LC74723, 74723M • Second byte Contents DA 0 to 7 Register name State 7 — 0 Second byte identification code 0 An LC oscillator is used for the dot clock 6 5 LC HP5 (MSB) 4 HP4 3 HP3 2 HP2 1 HP1 0 HP0 (LSB) Function 1 A crystal oscillator is used for the dot clock 0 If HS is the horizontal display start position then: 1 0 1 Remarks Selects the dot clock used for horizontal direction character display. 5 HS = Tc × (2Σ 2n HPn) n=0 Tc: The oscillator period of the OSCIN and OUT pin oscillator in operating mode 0 1 The horizontal display start position is set by the 6 bits HP0 to HP5. 0 The weight of the low-order bit is 2Tc. 1 0 1 0 1 Note: The register states are all set to zero when the LC74723 is reset with the RST pin. 5. COMMAND4 (Display control command) • First byte Contents DA 0 to 7 Register name State 7 — 1 6 — 1 5 — 0 4 — 0 3 TSTMOD 2 RAMERS 1 OSCSTP 0 SYSRST Function Command 4 identification code Set display control. 0 Normal operating mode 1 Test mode This bit must be zero. 0 1 Remarks Erase display RAM (set to 3F hexadecimal) The RAM erase operation requires about 500 µs (It is executed in the DSPOFF state.) 0 Do not stop the crystal oscillator or LC oscillator circuits. 1 Stop the crystal oscillator or LC oscillator circuits. Valid when character display is off in external synchronization mode. Reset all registers and turn the display off. Reset occurs when the CS pin is low, and the reset is cleared when CS is high. 0 1 • Second byte Contents DA 0 to 7 Register name State 7 — 0 Second byte identification code 0 Trimming level 0 (VBK0) 1 Trimming level 1 (VBK1) 0 Interlace (256.5 H per field) 1 Non-interlace (263 H per field) 0 Trimming off 1 Trimming on 0 Blinking period: about 0.5 s 1 Blinking period: about 1.0 s 0 Blinking off 6 EGL 5 NON 4 EG 3 BK1 2 BK0 1 0 RV DSPON Function 1 Blinking on 0 Reverse (character reversing) off 1 Reverse (character reversing) on 0 Character display off 1 Character display on Remarks Trimming level switching Interlace/non-interlace switching Blinking state switching When blinking is specified for reversed characters, the blinking will be between normal character and reversed character display. Note: The register states are all set to zero when the LC74723 is reset with the RST pin. No. 4841-9/12 LC74723, 74723M 6. COMMAND5 (Display control command) • First byte Contents DA 0 to 7 Register name State 7 — 1 6 — 1 5 — 0 4 — 1 3 — 0 2 PH 1 0 Function Command 5 identification code Synchronization signal control setup 0 Green background 1 Blue background 0 External synchronization signal detection control: Disabled 1 External synchronization signal detection control: Enabled 0 External synchronization 1 Internal synchronization RSN INT Note Background color switching (Only valid in NTSC mode, only a blue background color is supported in PAL-M mode.) External synchronization signal detection control Judges whether the signal has gone from present to absent or from absent to present. External/internal synchronization switching Note: The register states are all set to zero when the LC74723 is reset with the RST pin. Display Screen Structure The display consists of 24 characters × 10 rows for a maximum of 240 characters. The maximum number of characters is reduced when the character size is enlarged. Display memory addresses are specified as row (0 to 9 decimal) and column (0 to 23 decimal) addresses. Display Screen Structure (display memory addresses) No. 4841-10/12 LC74723, 74723M Composite Video Signal Output Level (internally generated level) CVOUT output level waveform (VDD2 = 5.00 V) Output voltage ➀ [V] Output voltage ➁ [V] VCHA: Character 2.69 2.88 VRSH: Background color high 2.08 2.28 VCBH: Color burst high 1.72 1.91 VRSL: Background color low 1.56 1.75 Output level VBK1: Trimming 2.13 2.30 VBK0: Trimming 1.55 1.73 VPD: Pedestal 1.40 1.59 VCBL: Color burst low 1.09 1.28 VSN: Sync 0.81 1.01 Note: VDD2 = 5.00 V No. 4841-11/12 LC74723, 74723M ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1997. Specifications and information herein are subject to change without notice. No. 4841-12/12