Ordering number : EN*5396 CMOS LSI LC74751 On-Screen Display LSI Preliminary Overview Package Dimensions The LC74751 is a CMOS LSI that supports on-screen display of characters and patterns on a TV screen under the control of a microcontroller. The LC74751 includes an on-chip character ROM that provides 128 characters in a 12 × 18 dot format. This IC supports display of up to 12 lines of 24 characters each for a maximum of 288 characters. unit: mm 3059-DIP22S [LC74751] Features • Display format: 24 characters by 12 rows • Characters displayed: Up to 288 characters • Display control ROM (line ROM): ROM for 64 lines (Control in line units: lines consisting of 24 characters) • Display RAM: 176 characters (Used for the specification of user-defined characters.) • Character format: 12 (horizontal) × 18 (vertical) dots • Characters in font: 128 • Character sizes: Four sizes each in the horizontal and vertical directions • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable in character units • Blinking types: — Two periods supported: 1.0 second and 0.5 second — Three duty types supported: 25%, 50%, and 75% • Blanking: Over the whole font (12 × 18 dots) • Background color — 8 background colors (in internal synchronization mode): 4fsc (NTSC/PAL/PAL-M/PAL-N) — 4 background colors (in internal synchronization mode): 2fsc (NTSC) — Single background color (blue) (in internal synchronization mode): 2fsc (PAL/PAL-M/PAL-N) • External control input: Serial data input • Synchronizing signals: Supports switching between internal and external synchronizing signals. • On-chip sync separator circuit • Video output: Composite video output in the NTSC, PAL, PAL-M, or PAL-N format • Superimpose function: Superimposes the character output on the composite video output. SANYO: DIP22S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 83096HA (OT) No. 5396-1/15 LC74751 Pin Assignment Specifications Absolute Maximum Ratings Ratings Unit Supply voltage Parameter VDD VDD1 and VDD2 VSS–0.3 to VSS+7.0 V Input voltage VIN All input pins VSS–0.3 to VDD+0.3 V Output voltage Symbol Conditions VOUT Allowable power dissipation Pd max VSS–0.3 to VDD+0.3 Ta = 25°C 300 V mW Operating temperature Topr –30 to +70 °C Storage temperature Tstg –40 to +125 °C Allowable Operating Ranges Parameter Supply voltage Symbol Conditions Ratings min typ Unit max VDD1 VDD1 4.5 5.0 5.5 V VDD2 VDD2 4.5 5.0 1.27 VDD1 V Input high-level voltage VIH CS, SIN, RST, SCLK, and SEPIN 0.8 VDD1 VDD1 + 0.3 V Input low-level voltage VIL CS, SIN, RST, SCLK, and SEPIN VSS – 0.3 0.2 VDD1 V Composite video input voltage Oscillator frequency VIN1 CVIN 2 Vp-p VIN2 SYNIN 2 Vp-p V 2.5 Vp-p V fOSC1 Crystal oscillator pins (NTSC: 2fsc mode) 7.15909 MHz fOSC2 Crystal oscillator pins (NTSC: 4fsc mode) 14.31818 MHz fOSC3 Crystal oscillator pins (PAL: 4fsc mode) 17.73447 MHz fOSC4 Crystal oscillator pins (PAL-M: 4fsc mode) 14.30244 MHz fOSC5 Crystal oscillator pins (PAL-N: 4fsc mode) 14.32822 fOSC6 LC oscillator pin (When an LC oscillator is used) 5 7 MHz 11 MHz Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified Parameter Symbol Conditions Output off leakage current Ileak CVOUT Output high-level voltage VOH1 SEPOUT: VDD1 = 4.5 V, IOH = –1.0 mA Output low-level voltage VOL1 SEPOUT: VDD1 = 4.5 V, IOL = 1.0 mA Input current Operating current drain IIH CS, SIN, RST, SCLK, and SEPIN: VIN = VDD1 IIL OSCIN: VIN = VSS Ratings min typ Unit max 10 3.5 µA V 1.0 V 1 µA –1 µA IDD1 VDD1; All outputs open, Xtal: 17.734MHz, LC = 7MHz 10 mA IDD2 VDD2; VDD2 = 5.0 V 15 mA No. 5396-2/15 LC74751 Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5±0.5 V Parameter Minimum input pulse width Data setup time Data hold time One-word write time Symbol tW(SCLK) Conditions SCLK Ratings min typ max Unit 200 ns 1 µs CS 200 ns tSU(SIN) SIN 200 ns th(CS) CS 2 µs th(SIN) SIN 200 ns 10 µs 1 µs tW(CS) CS (the period when CS is high) tSU(CS) tword twt The time to write 16 bits of data The time to write data to RAM Serial Data Input Timing No. 5396-3/15 LC74751 Pin Functions Pin no. Pin Function 1 VSS Ground Notes Ground (digital system ground) 2 XtalIN 3 XtalOUT 4 TEST Test output Test data output 5 RST Reset input System reset input (This input has hysteresis characteristics.) 6 SCLK Clock input Clock input for the serial data input function (This input has hysteresis characteristics.) 7 SIN Data input Serial data input (This input has hysteresis characteristics.) Data is input in 16-bit units. 8 CS Enable input Crystal oscillator 9 LVBK Blanking level adjustment input 10 LVCHA Character level adjustment input 11 VDD2 Power supply Video signal output 12 CVOUT 13 NC 14 CVIN Connections for the crystal and capacitors used to form the crystal oscillator for generating internal synchronizing signals. Serial data input enable input (This input has hysteresis characteristics.) Serial data input is enabled when this pin is low. Level input signal used to adjust the blanking level. Level input signal used to adjust the character level. Composite video signal adjustment power supply (analog system power supply) Composite video signal output This pin must be either connected to ground or left open. Video signal input Composite video signal input 15 VDD1 Power supply 16 SYNIN Sync separator circuit input 17 SEPC Sync separator circuit adjustment 18 SEPOUT Composite sync signal output 19 SEPIN Vertical synchronizing signal input Connect an integration circuit between the SEPOUT pin and this pin, which inputs the vertical synchronizing signal, to integrate the output signal from the SEPOUT pin. 20 OSCOUT 21 OSCIN LC oscillator Connections for the coil and capacitor that form the oscillator used to generate the character output dot clock. 22 VDD1 Power supply (+5 V) Power supply (+5 V) Input to the composite sync signal sync separator circuit Sync separator circuit adjustment Sync separator circuit composite sync signal output Power supply (+5 V) No. 5396-4/15 LC74751 System Block Diagram Display Screen Structure The display mode has a 24-character by 12-row format. The maximum number of characters that can be displayed is 288. When character sizes are enlarged, the maximum number of characters that can be displayed is reduced. Display ROM (12-line specification) and display RAM (for 176 characters) • Specify fixed characters in the display line ROM. • Application programs use the display RAM to specify characters for sections of the display in which the characters change. No. 5396-5/15 LC74751 Memory Organization (display RAM and control RAM) Both memory addresses and data are 16-bit quantities. The locations at addresses 000 (000 hexadecimal) to 175 (0AF hexadecimal) hold display memory (RAM) data. The locations at addresses 176 (0B0 hexadecimal) to 191 (0BF hexadecimal) hold display control register data. Bit DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA F E D C B A 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ATTR C6 C5 C4 C3 C2 C1 C0 Notes Address 000 (000h) ATTR 175 (0AFh) 0 0 0 Display RAM 0 0 0 0 ATTR C6 C5 C4 C3 C2 C1 C0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the first line 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the second line 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the third line 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the fourth line 180 (0B4h) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the fifth line 181 (0B5h) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the sixth line 182 (0B6h) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the seventh line 183 (0B7h) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the eighth line 184 (0B8h) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the ninth line 185 (0B9h) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the tenth line 186 (0BAh) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the eleventh line 187 (0BBh) 0 0 0 0 0 ADR A ADR 9 ADR 8 ADR 7 ADR 6 ADR 5 ADR 4 ADR 3 ADR 2 ADR 1 ADR 0 Display line ROM specification First character in the twelfth line 188 (0BCh) 0 0 0 0 HSZ 31 HSZ 30 HSZ 21 HSZ 20 HSZ 11 HSZ 10 HP5 HP4 HP3 HP2 HP1 HP0 Horizontal display position Horizontal character size 189 (0BDh) 0 0 0 0 VSZ 31 VSZ 30 VSZ 21 VSZ 20 VSZ 11 VSZ 10 VP5 VP4 VP3 VP2 VP1 VP0 Vertical display position Vertical character size 190 (0BEh) 0 0 0 0 INT/ NON LC/ XTAL 2fsc/ 4fsc OSC STP DSP ON MUTE SYS RST SIG MD1 SIG PHASE PHASE PHASE Video signal and other items MD0 2 1 0 191 (0BFh) 0 0 0 0 TST MOD VSN SEP 0 BLK 1 BLK 0 RVS ON 176 (0B0h) 0 0 0 177 (0B1h) 0 0 178 (0B2h) 0 179 (0B3h) 0 Character code BLINK BLINK BLINK 2 1 0 EXT/ INT CBOFF BCOL Control register No. 5396-6/15 LC74751 Address 188 (0BC hexadecimal) DA 0 to C 0 Contents Register HP0 (LSB) Notes State 0 1 0 1 Function If HS is the horizontal start position then: The 6 bits HP5:0 specify the horizontal display start position. 5 HS = Tc × (4 Σ 2n HPn) The weight of the low order bit is 4·Tc. n=0 HP1 1 Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating mode. 0 2 HP2 1 0 3 HP3 1 0 4 HP4 1 5 HP5 (MSB) 0 1 0 6 7 HSZ10 0 0 1 Tc/dot 2 Tc/dot 1 3 Tc/dot 4 Tc/dot 0 1 HSZ11 HSZ20 1 HSZ21 0 1 Tc/dot 2 Tc/dot 1 3 Tc/dot 4 Tc/dot 0 1 HSZ21 0 B The horizontal character size for line 2 HSZ20 0 1 A 1 HSZ11 0 9 0 1 1 8 The horizontal character size for line 1 HSZ10 HSZ30 The horizontal character size for lines 2 HSZ30 1 HSZ31 0 0 1 Tc/dot 2 Tc/dot 1 3 Tc/dot 4 Tc/dot HSZ31 1 through 12 Note: The states of all registers are set to zero when the IC is reset by the RST pin. No. 5396-7/15 LC74751 Address 189 (0BD hexadecimal) DA 0 to C 0 Contents Register VP0 (LSB) Notes State 0 1 0 1 Function If VS is the vertical display start position then: The 6 bits VP5:0 specify the vertical display start position. 5 VS = H × (4 Σ 2n VPn) The weight of the low order bit is 4·H. n=0 VP1 1 H: the horizontal synchronization pulse period 0 2 VP2 1 0 3 VP3 1 0 4 VP4 1 5 VP5 (MSB) 0 1 0 6 7 VSZ10 0 0 1 H/dot 2 H/dot 1 3 H/dot 4 H/dot 0 1 VSZ11 VSZ20 VSZ21 0 0 1 H/dot 2 H/dot 1 3 H/dot 4 H/dot 0 1 VSZ21 0 B The vertical character size for line 2 VSZ20 1 1 A 1 VSZ11 0 9 0 1 1 8 The vertical character size for line 1 VSZ10 VSZ30 The vertical character size for lines 3 through 12 VSZ30 1 VSZ31 0 0 1 H/dot 2 H/dot 1 3 H/dot 4 H/dot VSZ31 1 Note: The states of all registers are set to zero when the IC is reset by the RST pin. No. 5396-8/15 LC74751 Address 190 (0BE hexadecimal) DA 0 to C Contents Register Notes State Function 0 0 PHASE2 PHASE1 PHASE0 PHASE0 1 0 1 2 Background color (phase) NTSC PAL (PAL-M, N) 0 0 0 π/2 ± π/2 0 0 1 π In phase +- π/2 0 1 0 3π/2 0 1 1 In phase ±π 1 1 0 0 π/4 ±3π/4 1 0 1 3π/4 0 1 1 0 5π/4 +- π/4 1 1 1 7π/4 ±3π/4 SIGMD1 SIGMD0 Signal format 0 0 NTSC 0 1 PAL 1 0 PAL-M 1 1 PAL-N PHASE1 PHASE2 Background color The phase of the background color with respect to the color burst signal. ±π/4 1 0 3 SIGMD0 1 0 4 SIGMD1 1 0 5 6 7 8 9 A B SYSRST 1 Resets all registers and turns display off. 0 Normal output 1 CVIN is cut and CVOUT is fixed at the pedestal level. 0 Character display off 1 Character display on 0 Crystal oscillator and LC oscillator circuits are not stopped. 1 Stops the crystal oscillator and LC oscillator circuits. 2fsc/ 4fsc/ 0 Clock frequency: 2fsc 1 Clock frequency: 4fsc LC/ XTAL 0 The LC oscillator is used for the dot clock. 1 The crystal oscillator is used for the dot clock. INT/ NON 0 Interlaced (262.5 H per field: NTSC, 312.5 H per field: PAL) 1 Noninterlaced (263 H per field: NTSC, 313 H per field: PAL) The IC is reset by a low level on the CS pin, and the reset state is cleared by a high level on that pin. MUTE DSPON OSCSTP Only valid in external synchronization mode when character display is off. Crystal oscillator circuit frequency The OSCIN pin must be tied to VDD if the LC oscillator circuit is not used. Switches interlaced and noninterlaced display. Note: The states of all registers are set to zero when the IC is reset by the RST pin. No. 5396-9/15 LC74751 Address 191 (0BF hexadecimal) DA 0 to C 0 1 2 Contents Register Notes State Function 0 Background color provided (only valid in internal synchronization mode) 1 No background color (Only the background level is set) 0 The burst signal is always output. 1 The burst signal is not output when BCOL is high. 0 External synchronization 1 Internal synchronization BCOL CBOFF EXT/ INT 0 3 4 8 1 BLINK1 0 0 Blinking off 25% duty 1 50% duty 75% duty BLINK1 Blinking period: 0.5 s Changes the blinking period. BLINK2 1 Blinking period: 1.0 s 0 Reverse video off 1 Reverse video on RVSON 0 7 0 1 0 6 Changes the blinking duty ratio. BLINK0 BLINK0 1 5 Switches between external and internal sources for the HSYNC and VSYNC signals. Changes the blanking size BLK0 BLK0 0 1 1 BLK1 0 0 Blinking off Character size 1 Frame size Whole area size BLK1 1 0 9 — 1 A B 0 External V input used (SEPIN: pin 19) 1 Internal V separation circuit used 0 Normal operating mode 1 Test mode VSNSEP Selects V input when superimpose mode is used. This bit must be set to 0. TSTMOD Note: The states of all registers are set to zero when the IC is reset by the RST pin. No. 5396-10/15 LC74751 Memory (Display ROM) Organization This memory has addresses ranging from 0 (000 hexadecimal) to 1535 (5FF hexadecimal). Data has 8 bits. Bit DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA F E D C B A 9 8 7 6 5 4 3 2 1 0 000 (000h) 0 0 0 0 0 0 0 0 ROM/ RAM ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Line ROM: First character in the first line 0023 (017h) 0 0 0 0 0 0 0 0 ROM/ RAM ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Line ROM: 24th character in the first line 0024 (018h) 0 0 0 0 0 0 0 0 ROM/ RAM ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Line ROM: First character in the second line ADR1 ADR0 Line ROM: 24th character in the 64th line Notes Address ROM/ RAM 1535 (5FFh) DA 0 to 8 0 0 0 0 0 0 0 0 ROM/ RAM ADR6 ADR5 ADR4 ADR3 ADR2 Contents Register Notes State Function 0 Specifies an address in character ROM. When specifying display control RAM, DA7 must be set to 1 and ADR0 to ADR6 must be set to 0. The address specification range for character ROM is 0 to 127 (7F hexadecimal). ADR0 1 0 1 0 Character code ADR1 1 0 2 ADR2 1 0 3 ADR3 1 0 4 ADR4 1 0 5 ADR5 1 0 6 ADR6 1 7 ROM/ RAM 0 Data is read directly from character ROM. 1 Data is read from character ROM through RAM. No. 5396-11/15 LC74751 Display Line ROM: Line Address Table Line no. Address Line no. Address Line 1 000HEX (0000) Line 33 300HEX (0768) Line 2 018HEX (0024) Line 34 318HEX (0792) Line 3 030HEX (0048) Line 35 330HEX (0816) Line 4 048HEX (0072) Line 36 348HEX (0840) Line 5 060HEX (0096) Line 37 360HEX (0864) Line 6 078HEX (0120) Line 38 378HEX (0888) Line 7 090HEX (0144) Line 39 390HEX (0912) Line 8 0A8HEX (0168) Line 40 3A8HEX (0936) Line 9 0C0HEX (0129) Line 41 3C0HEX (0960) Line 10 0D8HEX (0216) Line 42 3D8HEX (0984) Line 11 0F0HEX (0240) Line 43 3F0HEX (1008) Line 12 108HEX (0264) Line 44 408HEX (1032) Line 13 120HEX (0288) Line 45 420HEX (1056) Line 14 138HEX (0312) Line 46 438HEX (1080) Line 15 150HEX (0336) Line 47 450HEX (1104) Line 16 168HEX (0360) Line 48 468HEX (1128) Line 17 180HEX (0384) Line 49 480HEX (1152) Line 18 198HEX (0408) Line 50 498HEX (1176) Line 19 1B0HEX (0432) Line 51 4B0HEX (1200) Line 20 1C8HEX (0456) Line 52 4C8HEX (1224) Line 21 1E0HEX (0480) Line 53 4E0HEX (1248) Line 22 1F8HEX (0504) Line 54 4F8HEX (1272) Line 23 210HEX (0528) Line 55 510HEX (1296) Line 24 228HEX (0552) Line 56 528HEX (1320) Line 25 240HEX (0576) Line 57 540HEX (1344) Line 26 258HEX (0600) Line 58 558HEX (1368) Line 27 270HEX (0624) Line 59 570HEX (1392) Line 28 288HEX (0648) Line 60 588HEX (1416) Line 29 2A0HEX (0672) Line 61 5A0HEX (1440) Line 30 2B8HEX (0696) Line 62 5B8HEX (1464) Line 31 2D0HEX (0720) Line 63 5D0HEX (1488) Line 32 2E8HEX (0744) Line 64 5E8HEX (1512) No. 5396-12/15 LC74751 Display Screen Structure (Display Example) Specify the display of line 12 for display line ROM (64 lines). From within line ROM, specify display control RAM for the sections where the characters are variable. The addresses in display control RAM are automatically allocated in display order from 0 to 175 (AF hexadecimal). Items enclosed in thick lines specify characters in display control RAM, and items enclosed in thin lines are character specified in line ROM. Control Data External Input Timing Data is input in a 16-bit serial format that includes both an address and data items. ①An address has 16 bits. The lower 8 bits are the valid address bits. The upper 8 bits must be set to 0. ②Data consists of 16 bits. • For addresses 000 to 0AF (hexadecimal) the lower 8 bits are valid data. The upper 8 bits must be set to 0. • For addresses 0B0 to 0BB (hexadecimal) the lower 11 bits are valid data. The upper 5 bits must be set to 0. • For addresses 0BC to 0BF (hexadecimal) the lower 12 bits are valid data. The upper 4 bits must be set to 0. ③When data is input, the first 16 bits after the fall of the CS signal are acquired as the address, and then data is acquired in 16-bit units. The address is automatically incremented ever 16 bits. No. 5396-13/15 LC74751 Composite Video Signal Output Levels (Internally Generated Levels) CVOUT output level waveform (VDD2 = 5.00 V) Output level Output voltage (1) (VDC) Output voltage (2) (VDC) VCHA: Character 2.650 2.875 VRSH: Background color high 2.075 2.275 VCBH: Color burst high 1.700 1.900 VRSL: Background color low 1.500 1.700 VBK: Frame 1.500 1.700 VPD: Pedestal level 1.375 1.575 VCBL: Color burst low 1.050 1.250 VSN: Sync 0.800 1.000 VDD2 = 5.000VDC No. 5396-14/15 LC74751 Application Circuit Example ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1996. Specifications and information herein are subject to change without notice. No. 5396-15/15