Ordering number : EN*5557
CMOS LSI
LC74794, 74794M
On-Screen Display Controller LSI
Preliminary
Overview
Package Dimensions
The LC74794 and LC74794M are CMOS LSIs for onscreen display, a function that displays characters and
patterns on a TV screen under microprocessor control.
They feature a built-in PDC/VPS/UDT interface circuit.
These LSIs support 12 × 18 dot characters and can display
12 lines by 24 characters of text.
unit: mm
3196-DIP30SD
[LC74794]
Features
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal) × 18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 128
• Initial display positions: 64 horizontal positions and 64
vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported: 1.0 second and
0.5 second
• Blanking: Over the whole font (12 × 18 dots)
• Background color
— Background coloring: 8 colors (internal synchronization
mode): 4fsc
— Background coloring: 6 colors (internal synchronization
mode): 2fsc
— Blue background only: NTSC
• Line background color
— Can be set for 3 lines
— Line background coloring: 8 colors (internal synchronization mode): 4fsc
— Line background coloring: 6 colors (internal synchronization mode): 2fsc
• External control input: 8-bit serial input format
• On-chip sync separator and AFC circuits
• PDC/VPS/UDT interface circuit
• Composite video output in the PAL or NTSC format
SANYO: DIP30SD
unit: mm
3216A-MFP30S
[LC74794M]
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT)/No. 5557-1/30
LC74794, 74794M
Pin Assignment
Pin Functions
Pin no.
Pin
1
VSS1
2
XtalIN
3
4
XtalOUT
(MUTE)
Notes
Ground connection (digital system ground)
Crystal oscillator
(MUTE input)
These pins are used either to connect a crystal and capacitor to form an external crystal
oscillator to generate internal synchronizing signals, or to input an external clock signal (2fsc
or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin.
When the MUTE pin is set low, the video output is held at the pedestal level. (A pull-up
resistor is built in so the input has hysteresis characteristics.)
CTRL1 Crystal oscillator input switching
(CHABLK) (CHABLK output)
Switches the mode between external clock input and crystal oscillator operation. A low level
selects crystal oscillator operation and a high level selects external clock input. As a mask
option, the CTRL1 input pin can be set to function as the CHABLK (character · border)
output. This is a 3-value output.
Enable input 2
PDC/VPS data output enable input. Data output is enabled by a low-level input. (A pull-up
resistor is built in so the input has hysteresis characteristics.)
SCLK2
Clock input 2
Clock input for PDC/VPS data output
(A pull-up resistor is built in so the input has hysteresis characteristics.)
DOUT
Data output
PDC/VPS data output
(This is either an n-channel open-drain output or a CMOS output.)
5
CS2
6
7
8
Function
Ground
External synchronizing signal judgment
SYNCJDG
output
Outputs the state of the external synchronizing signal presence/absence judgment.
Outputs a high level when synchronizing signals are present.
Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not
output on command resets.)
Continued on next page.
No. 5557-2/30
LC74794, 74794M
Continued from preceding page.
Pin no.
Pin
Function
Notes
Enable input 1
Enable input for OSD serial data input
Serial data input is enabled by a low-level input.
(A pull-up resistor is built in so the input has hysteresis characteristics.)
SCLK1
Clock input 1
Serial data clock input
(A pull-up resistor is built in so the input has hysteresis characteristics.)
11
SIN1
Data input 1
Serial data input (A pull-up resistor is built in so the input has hysteresis characteristics.)
12
VDD2
Power supply
Composite video signal level adjustment power supply (analog system power supply)
13
CPOUT
Charge pump output
The charge pump output. Connect a low-pass filter to this pin.
14
VCOIN
Oscillator control voltage input
VCO control voltage input
15
VSS3
Ground
Ground (VCO ground)
16
VDD3
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
17
VCOR
Oscillator range adjustment
Connection for the VCO range adjustment resistor
9
CS1
10
18
DAV
Data present output
Outputs a low level when PDC/VPS data has been received.
19
CVOUT
Video signal output
Composite video signal output
20
VSS2
Ground
Ground (analog system ground)
21
CVIN
Video signal input
Composite video signal input
22
CVCR
Video signal input
SECAM chrominance signal input
23
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
24
SYNIN
Sync separator circuit input
Internal sync separator circuit video signal input
25
SEPC
Sync separator circuit adjustment
Internal sync separator circuit adjustment input
26
SEPOUT
Composite synchronizing signal output
Composite synchronizing signal output for the built-in sync separator circuit. Can be
switched to function as an output for the signal (high or ST. pulse) due to MOD0 by setting
SEL0 high.
27
SEPIN
Vertical synchronizing signal input
Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output
signal.
An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1
if unused.
28
CDLR
Background color phase adjustment
Background color phase adjustment resistor connection
29
RST
Reset input
System reset input
A pull-up resistor is built in so the input has hysteresis characteristics.
30
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
No. 5557-3/30
LC74794, 74794M
Specifications
Absolute Maximum Ratings at Ta = 25°C
Ratings
Unit
Supply voltage
Parameter
VDD
VDD1 and VDD2
VSS – 0.3 to VSS + 7.0
V
Input voltage
VIN
All input pins
VSS – 0.3 to VDD + 0.3
V
DAV, DOUT, SEPOUT, and SYNCJDG
VSS – 0.3 to VDD + 0.3
Output voltage
Symbol
VOUT
Allowable power dissipation
Conditions
Pd max
350
V
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Pull-up resistance
Composite video signal input voltage
Input voltage
Oscillator frequency
Symbol
Ratings
Conditions
min
typ
Unit
max
VDD1
VDD1 and VDD2
4.5
5.0
5.5
V
VDD2
VDD2
5.5
5.0
1.27 VDD1
V
VIH1
RST, CS1, CS2, SIN1, SCLK1, SCLK2,
and MUTE
0.8 VDD1
VDD1 + 0.3
V
VIH2
CTRL1
0.7 VDD1
VDD1 + 0.3
V
VIL1
RST, CS1, CS2, SIN1, SCLK1, SCLK2,
and MUTE
VSS – 0.3
0.2 VDD1
V
VIL2
CTRL1
VSS – 0.3
0.3 VDD1
V
RPU
RST, CS1, CS2, SIN1, SCLK1, SCLK2,
and MUTE
VIN1
CVIN and CVCR; VDD1 = 5 V
VIN2
SYNIN; VDD1 = 5 V
VIN3
XtalIN (in external clock input mode)
fin = 2 fsc or 4 fsc ; VDD1 = 5 V
25
50
90
2.0
1.5
2.0
0.10
kΩ
Vp-p
2.5
Vp-p
5.0
Vp-p
FOSC1
XtalIN and XtalOUT oscillator pins (2 fsc: PAL)
8.867
MHz
FOSC2
XtalIN and XtalOUT oscillator pins (4 fsc: PAL)
17.734
MHz
Note: When the XtalIN pin is used in clock input mode, extreme care must be taken to prevent noise from entering the input signal.
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Input off leakage current
Ileak1
CVIN and CVCR
1
µA
Output off leakage current
Ileak2
CVOUT
1
µA
Output high-level voltage
VOH1
DAV, DOUT, SEPOUT, CPOUT, SYNCJDG ;
VDD1 = 4.5 V, IOH = –1.0 mA
Output low-level voltage
VOL1
DAV, DOUT, SEPOUT, CPOUT, SYNCJDG ;
VDD1 = 4.5 V, IOL = 1.0 mA
CHABLK ; VDD1 = 5.0 V
Three-value output voltage
Input current
VO
IIH
IIL
Operating current drain
SYNC level
Pedestal level
Color burst low level
IDD1
1.0
H
3.3
5.0
V
1.8
2.3
V
L
0
0.8
V
1
µA
CTRL1, SEPIN, and VCOIN ; VIN = VSS1
VDD2; VDD2 = 5 V
VSN
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
V
M
–1
µA
VDD1; with all outputs open
Xtal : 17.734 MHz, VCO : 27 MHz
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
VCBL
V
RST, CS1, CS2, SIN, SCLK1, SCLK2,
CTRL1, MUTE, SEPIN, and VCOIN
VIN = VDD1
IDD2
VPD
3.5
➀
➁
➂
➀
➁
➂
➀
➁
➂
40
mA
20
mA
0.80
V
1.00
V
1.30
V
1.37
V
1.57
V
1.87
V
1.07
V
1.27
V
1.57
V
Continued on next page.
No. 5557-4/30
LC74794, 74794M
Continued from preceding page.
Parameter
Color burst high level
Background color low level
Background color high level
Frame level 0
Symbol
VCBH
VRSL
VRSH
VBK0
Frame level 1
VBK1
Character level
VCHA
Ratings
Conditions
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
CVOUT; VDD1 = 5.0 V
VDD2 = 5.0 V
min
typ
➀
➁
➂
➀
➁
➂
➀
➁
➂
➀
➁
➂
➀
➁
➂
➀
➁
➂
max
Unit
1.67
V
1.87
V
2.17
V
1.23 (1.16)
V
1.43 (1.36)
V
1.73 (1.66)
V
2.37 (2.01)
V
2.57 (2.21)
V
2.87 (2.51)
V
1.50
V
1.70
V
2.00
V
2.08
V
2.28
V
2.58
V
2.65
V
2.85
V
3.15
V
Notes: ➀ When the sync level is 0.8 V.
➁ When the sync level is 1.0 V.
➂ When the sync level is 1.3 V.
The values in parentheses for the background color high and low levels are the values for a blue background.
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V
OSD write (See Figure 1.)
Parameter
Minimum input pulse width
Data setup time
Data hold time
One word write time
Symbol
Conditions
tW(SCLK)
SCLK1
tW(CS1)
CS1 (The period when CS1 is high)
tSU(CS1)
Ratings
min
typ
max
Unit
200
ns
1
µs
CS1
200
ns
tSU(SIN)
SIN1
200
ns
th(CS1)
CS1
2
µs
th(SIN)
SIN1
200
ns
The time to write 8 bits of data
4.2
µs
1
µs
tword
twt
The RAM data write time
PDC/VPS reads (For the n-channel open-drain output circuit. See Figure 2.)
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
tCKCY
SCLK2
2
µs
tCKL
SCLK2
1
µs
tCKH
SCLK2
1
µs
Setup time
tICK
SCLK2
10
Output delay time
tCKO
DOUT
Minimum input pulse width
µs
0.5
µs
Note: Timings follow those for OSD write when the CMOS output circuit is used.
No. 5557-5/30
LC74794, 74794M
Figure 1 OSD Serial Data Input Timing
Note: DOUT goes to the high-impedance state while CS2 is high.
Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output)
No. 5557-6/30
LC74794, 74794M
System Block Diagram
No. 5557-7/30
LC74794, 74794M
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of
a command identification code in the first byte and command data in the following bytes. The following commands are
supported.
1 COMMAND0: Display memory (VRAM) write address setup command
2 COMMAND1: Display character data write command
3 COMMAND2: Vertical display start position and vertical character size setup command
4 COMMAND3: Horizontal display start position and horizontal character size setup command
5 COMMAND4: Display control setup command
6 COMMAND5: Display control setup command
7 COMMAND6: Synchronizing signal detection setup command
8 COMMAND7 to COMMAND12: Display control setup commands
9 COMMAND13 to COMMAND17: VPS/PDC commands
Display Control Command Table
First byte
Command
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
COMMAND0
Write address setup
1
0
0
0
V3
V2
V1
V0
0
0
0
H4
H3
H2
H1
H0
COMMAND1
Character write
1
0
0
1
0
0
0
0
at
c6
c5
c4
c3
c2
c1
c0
COMMAND2
Vertical character size and
vertical display start position
1
0
1
0
VS
21
VS
20
VS
11
VS
10
0
FS
VP
5
VP
4
VP
3
VP
2
VP
1
VP
0
COMMAND3
Horizontal character size and
horizontal display start position
1
0
1
1
HS
21
HS
20
HS
11
HS
10
0
HP
5
HP
4
HP
3
HP
2
HP
1
HP
0
COMMAND4
Display control
1
1
0
0
TST RAM
MOD ERS
OSC
STP
SYS
RST
0
BLK
2
BLK
1
BLK
0
BK
1
BK
0
RV
DSP
ON
COMMAND5
Display control
1
1
0
1
NP1
NP0
NON
INT
0
0
HLF
INT
BCL
CB
PH
2
PH
1
PH
0
COMMAND6
Synchronizing signal detection
1
1
1
0
SEL
0
MOD
0
DIS
LIN
MUT
0
RN
2
RN
1
RN
0
SN
3
SN
2
SN
1
SN
0
COMMAND7
Display control
1
1
1
1
0
0
0
0
0
CIN
SEL
CIN
CTL
VNP
SEL
VSP
SEL
MSK
ERS
MSK
SEL
EGL
COMMAND8
Display control
1
1
1
1
0
0
0
1
0
LNA
3
LNA
2
LNA
1
LNA
0
LPA
2
LPA
1
LPA
0
COMMAND9
Display control
1
1
1
1
0
0
1
0
0
LNB
3
LNB
2
LNB
1
LNB
0
LPB
2
LPB
1
LPB
0
COMMAND10
Display control
1
1
1
1
0
0
1
1
0
LNC
3
LNC
2
LNC
1
LNC
0
LPC
2
LPC
1
LPC
0
COMMAND11
Display control
1
1
1
1
0
1
0
0
0
0
0
0
LNC
SEL
MOD
3
LNB
SEL
MOD
2
COMMAND12
Display control
1
1
1
1
0
1
0
1
0
0
0
0
0
SEL
2
SEL
1
CTL
3
COMMAND13
VPS/PDC control
1
1
1
1
0
1
1
0
0
CPA
1
CPA
0
0
VPM
3
VPM
2
VPM
1
VPM
0
COMMAND14
VPS/PDC control
1
1
1
1
0
1
1
1
0
0
0
HBS
2
HBS
1
BMS
EMS
DCE
COMMAND15
VPS/PDC control
1
1
1
1
1
0
0
0
0
0
ECV
15
ECV
14
ECV
13
ECV
12
ECV
11
ECV
5
COMMAND16
VPS/PDC control
1
1
1
1
1
0
0
1
0
ECP
19
ECP
18
ECP
17
ECP
16
ECP
15
ECP
14
ECP
13
COMMAND17
VPS/PDC control
1
1
1
1
1
0
1
0
0
0
ECP
25
ECP
24
ECP
23
ECP
22
ECP
21
ECP
20
Once written, the command identification code in the first byte is stored until the next first byte is written. However,
when the display character data write command (COMMAND1) is written, the LC74794/M locks into the display
character data write mode, and another first byte cannot be written.
When the CS1 pin is set high, the LC74794/M is set to the COMMAND0 (display memory write address setup mode)
state.
No. 5557-8/30
LC74794, 74794M
COMMAND0 (Display memory write address setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
0
5
—
0
4
—
0
3
V3
2
V2
1
V1
0
V0
State
Function
Notes
Command 0 identification code
Sets the display memory write address.
0
1
0
1
Display memory line address (0 to B hexadecimal)
0
1
0
1
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
—
0
4
H4
3
H3
2
H2
1
H1
0
H0
State
Function
Notes
Second byte identification code
0
1
0
1
0
Display memory column address (0 to 17 hexadecimal)
1
0
1
0
1
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
COMMAND1 (Display character data write setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
0
5
—
0
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
State
Function
Command 1 identification code
Sets up display character data write mode.
Notes
When this command is input, the LC74794/M
locks in the display character data write mode
until the CS1 pin goes high.
No. 5557-9/30
LC74794, 74794M
Second byte
DA
0 to 7
Register
7
at
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
Contents
State
Notes
Function
0
Character attribute off
1
Character attribute on
0
1
0
1
0
1
0
Character code (00 to 7F hexadecimal)
1
0
1
0
1
0
1
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
COMMAND2 (Vertical display start position and vertical character size setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
0
5
—
1
4
—
3
2
1
0
VS21
VS20
VS11
VS10
State
Notes
Function
Command 2 identification code
Sets the vertical display start position and the vertical character size
0
0
VS20
0
1
0
0
1H/dot
2H/dot
1
1
3H/dot
1H/dot
VS21
1
0
VS10
0
1
0
0
1H/dot
2H/dot
1
1
3H/dot
1H/dot
VS11
1
Second line vertical character size
First line vertical character size
Second byte
DA
0 to 7
Register
7
—
6
5
FS
VP5
(MSB)
4
VP4
3
VP3
2
VP2
1
0
VP1
VP0
(LSB)
Contents
State
Function
0
Second byte identification bit
0
Crystal oscillator frequency: 2fsc
1
Crystal oscillator frequency: 4fsc
0
If VS is the vertical display start position then:
1
VS = H × (2 Σ 2n VPn)
0
1
0
1
0
Notes
5
n=0
H: the horizontal synchronization pulse period
The vertical display start position is set by the
6 bits VP0 to VP5.
The weight of bit 1 is 2H.
1
0
1
0
1
No. 5557-10/30
LC74794, 74794M
COMMAND3 (Horizontal display start position and horizontal size setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
0
5
—
1
4
—
1
3
HS21
2
HS20
1
HS11
0
HS10
State
Notes
Function
Command 3 identification code
Sets the horizontal display start position and the horizontal character size.
0
HS20
0
1
0
0
1Tc/dot
2Tc/dot
1
1
3Tc/dot
1Tc/dot
HS21
1
0
HS10
0
1
0
0
1Tc/dot
2Tc/dot
1
1
3Tc/dot
1Tc/dot
HS11
1
Second line horizontal character size
First line horizontal character size
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
HP5
(MSB)
0
4
HP4
3
HP3
2
HP2
1
HP1
0
HP0
(LSB)
State
Function
Notes
Second byte identification bit
1
0
1
If HS is the horizontal start position then:
0
HS = Tc × (2 Σ 2n HPn)
1
0
1
5
n=0
Tc: Period of the oscillator connected to OSCIN/OSCOUT in operating
mode.
The horizontal display start position is set by
the 6 bits HP0 to HP5.
The weight of bit 1 is 2Tc.
0
1
0
1
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-11/30
LC74794, 74794M
COMMAND4 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
0
4
—
0
3
TSTMOD
2
RAMERS
1
OSCSTP
0
SYSRST
State
Notes
Function
Command 4 identification code
Display control setup
0
Normal operating mode
1
Test mode
This bit must be set to 0.
0
Erasing RAM takes about 500 µs. (This operation
must be executed in the DSPOFF state.)
1
Erase display RAM. (Set the RAM data to 7F hexadecimal.)
0
Do not stop the crystal and LC oscillators.
1
Stop the crystal and LC oscillators.
Valid in external synchronization mode when
character display is off.
Reset all registers and turn display off.
The registers are reset when the CS1 pin is low,
and the reset state is cleared when CS1 is set high.
0
1
Second byte
DA
0 to 7
Register
7
—
6
BLK2
5
BLK1
4
BLK0
3
BK1
2
1
0
BK0
RV
DSPON
Contents
State
Notes
Function
0
Second byte identification bit
0
Character display area
1
Video display area
Specifies the size for complete fill-in
0
BLK0
0
1
0
0
Blanking off
Character size
1
1
Border size
Complete fill in
BLK1
1
0
Changes the blanking size
Blinking period: About 0.5 s
1
Blinking period: About 1.0 s
0
Blinking off
1
Blinking on
0
Reverse video off
1
Reverse video on
0
Character display off
1
Character display on
Switches the blinking period
Blinking in reverse video mode switches the
display between normal character display and
reverse video display.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-12/30
LC74794, 74794M
COMMAND5 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
0
4
—
3
NP1
2
NP0
1
NON
0
INT
State
Notes
Function
Command 5 identification code
Display control setup
1
0
NP0
NPP1
1
0
1
0
0
NTSC (525)
NTSC (625)
1
1
PAL (525)
PAL (625)
1
Interlaced
0
Noninterlaced
0
External synchronization
1
Internal synchronization
Switches between NTSC and PAL.
( ) external input V
Switches between interlaced and
noninterlaced video.
Switches between external and internal
synchronization
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
HLFINT
4
BCL
3
CB
2
PH2
State
0
Normal mode
No background coloring (Only the background level is set)
0
Background coloring on
1
No background coloring (Only the background level is set)
0
Color burst signal output
1
Color burst signal output stopped
1
0
PH1
1
0
0
Second byte identification bit
1
0
1
Notes
Function
PH0
1
Only valid in internal synchronization mode.
Only valid when BCL is high.
PH2
PH1
PH0
0
0
0
Background color (phase)
Cyan
0
0
1
Yellow
*
0
1
0
Red
*
*
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
*
Background color specification
*
*
*: When 2 fsc is used.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-13/30
LC74794, 74794M
COMMAND6 (Synchronizing signal detection setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
3
SEL0
2
MOD0
1
DISLIN
0
MUT
State
Notes
Function
Command 6 identification code
Sets up synchronizing signal control.
0
0
Sync separator signal
1
Output signal set by MOD0
0
High-level output
1
ST pulse signal
0
12 lines
1
10 lines
0
Normal output
1
CVIN is cut and CVOUT is held at the pedestal level.
Switches the SEPOUT (pin 19) output.
Only valid when SEL0 is high.
Switches the number of lines displayed.
CVOUT switching
Second byte
DA
0 to 7
Register
7
—
6
5
4
3
2
RN2
RN1
RN0
SN3
SN2
1
SN1
0
SN0
Contents
State
0
0
1
0
1
0
1
Notes
Function
Second byte identification bit
RN2
RN1
RN0
Number of times HSYNC detected
0
0
0
0 times
0
0
1
4 times
0
1
0
8 times
1
0
0
16 times
External synchronizing signal detection control
Signal absent → signal present transition
detection
Sets the sampling period in which SYNC can
be detected continuously in the horizontal
synchronizing signal period (1H).
0
1
SN3
SN2
SN1
SN0
Number of times HSYNC detected
0
0
0
0
0
Not detected
32 times
1
0
0
0
1
0
0
0
1
0
64 times
1
0
1
0
0
128 times
0
1
0
0
0
256 times
External synchronizing signal detection control
Signal present → signal absent transition
detection
Sets the sampling period in which SYNC
cannot be detected continuously in the
horizontal synchronizing signal period (1H).
1
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-14/30
LC74794, 74794M
COMMAND7 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
State
Function
Notes
Command 7 identification code
Display control setup
Extended command 0 identification code
Second byte
DA
0 to 7
Register
7
—
6
CINSEL
5
CINCTL
4
VNPSEL
3
VSPSEL
2
MSKERS
1
MSKSEL
0
EGL
Contents
State
Function
0
Second byte identification bit
0
Blank area (the logical OR of the character and frame signals)
1
Video signal display area
0
CVCR: off
1
CVCR:: on
0
V falling edge detection
1
V rising edge detection
0
VSEP: about 8.9 µs (NTSC)
1
VSEP: about 17.8 µs (NTSC)
0
Mask valid
1
Mask invalid
0
3H (NTSC)
1
20H (NTSC)
0
Border level 0 only (VBK0)
1
Two-stage border level (VBK0 and VBK1)
Notes
CVCR on signal switching
Turns CVCR on or off.
Switches the V acquisition polarity in external
mode when internal V separation is used.
Switches the internal V separation period.
Clears the HSYNC and VSYNK masks.
Switches the VSYNC mask.
Switches the border level.
(Only valid when BLK0 is 0 and BLK1 is 1.)
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-15/30
LC74794, 74794M
COMMAND8 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
0
—
1
State
Notes
Function
Command 7 identification code
Display control setup
Extended command 1 identification code
Second byte
DA
0 to 7
Register
7
—
6
LNA3
Contents
State
0
0
1
0
5
LNA2
1
0
4
LNA1
1
0
3
LNA0
Notes
Function
Second byte identification bit
LNA3 LNA2 LNA1 LNA0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
—
—
Line 12
Specifies the line whose background is to be
changed
(Specifying the same line with LNA*, LNB*,
and LNC* is not allowed.)
1
0
2
LPA2
1
0
1
LPA1
1
0
0
LPA0
1
LPA2
LPA1
LPA0
0
0
0
Background color (phase)
Cyan
0
0
1
Yellow
*
0
1
0
Red
*
*
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
*
Specifies the background color.
*
*
*: When 2 fsc is used.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-16/30
LC74794, 74794M
COMMAND9 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
1
0
—
0
State
Notes
Function
Command 7 identification code
Display control setup
Extended command 2 identification code
Second byte
DA
0 to 7
Register
7
—
6
LNB3
Contents
State
0
0
1
0
5
LNB2
1
0
4
LNB1
1
0
3
LNB0
Notes
Function
Second byte identification bit
LNB3 LNB2 LNB1 LNB0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
—
—
Line 12
Specifies the line whose background is to be
changed.
(Specifying the same line with LNA*, LNB*,
and LNC* is not allowed.)
1
0
2
LPB2
1
0
1
LPB1
1
0
0
LPB0
1
LPB2
LPB1
LPB0
0
0
0
Background color (phase)
Cyan
0
0
1
Yellow
*
0
1
0
Red
*
*
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
*
Specifies the background color.
*
*
*: When 2 fsc is used.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-17/30
LC74794, 74794M
COMMAND10 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
1
0
—
1
State
Notes
Function
Command 7 identification code
Display control setup
Extended command 3 identification code
Second byte
DA
0 to 7
Register
7
—
6
LNC3
Contents
State
0
0
1
0
5
LNC2
1
0
4
LNC1
1
0
3
LNC0
Notes
Function
Second byte identification bit
LNC3 LNC2 LNC1 LNC0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
—
—
Line 12
Specifies the line whose background is to be
changed.
(Specifying the same line with LNA*, LNB*,
and LNC* is not allowed.)
1
0
2
LPC2
1
0
1
LPC1
1
0
0
LPC0
1
LPC2
LPC1
LPC0
0
0
0
Background color (phase)
Cyan
0
0
1
Yellow
*
0
1
0
Red
*
*
0
1
1
Blue
1
0
0
Cyan - blue
1
0
1
Green
1
1
0
Orange
1
1
1
Magenta
*
Specifies the background color.
*
*
*: When 2 fsc is used.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-18/30
LC74794, 74794M
COMMAND11 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
0
0
—
0
State
Function
Notes
Command 7 identification code
Display control setup
Extended command 4 identification code
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
—
0
4
—
0
3
LNCSEL
2
MOD3
1
LNBSEL
0
MOD2
State
Function
Notes
Second byte identification bit
Switches the background color in RV mode for
RV specified characters on LNB* specified
lines.
0
Normal line background color operation
1
RV characters have the color of the PH* specified background color and
RV characters have a white background.
0
The specifications when LNCSEL is set to 1.
1
RV characters have the background color specified by PH* and the RV
characters themselves are white.
Valid when LNCSEL is high.
0
Normal line background color operation
1
RV characters have the color of the PH* specified background color and
RV characters have a white background.
Switches the background color in RV mode for
RV specified characters on LNB* specified
lines.
0
The specifications when LNBSEL is set to 1.
1
RV characters have the background color specified by PH* and the RV
characters themselves are white.
Valid when LNBSEL is high.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-19/30
LC74794, 74794M
COMMAND12 (Display control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
0
0
—
1
State
Function
Notes
Command 7 identification code
Display control setup
Extended command 5 identification code
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
—
0
4
—
0
3
—
2
SEL2
1
SEL1
0
CTL3
State
Function
Notes
Second byte identification bit
0
0
External synchronizing signal judgment output signal
1
O/E signal
0
Internal slice data
1
External slice data
0
Use internal V separation.
1
Do not use internal V separation.
SYNCJDG (pin 8) output switching
Signal input from SEPIN (pin 27) when set to 1
V separation switching
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-20/30
LC74794, 74794M
COMMAND13 (VPS/PDC control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
1
0
—
0
State
Notes
Function
Command 7 identification code
Display control setup
Extended command 6 identification code
Second byte
DA
0 to 7
Register
7
—
6
CPA1
Contents
State
0
Notes
Function
Second byte identification bit
0
1
0
5
CPA0
CPA1
CPA0
Clock
0
0
No.1
0
1
No.2
1
0
No.3
1
1
No.4
Data acquisition clock switching
1
4
—
3
VPM3
0
0
VPM3 VPM2 VPM1 VPM0
1
0
2
VPM2
1
0
1
VPM1
1
0
0
VPM0
Operating mode
0
0
0
0
VPS
0
0
0
1
8/30/2 (PDC)
0
0
1
0
Automatic PDC and VPS switching
0
0
1
1
8/30/1 (UDT)
0
1
0
0
Header time 1
0
1
0
1
Header time 2
0
1
1
0
Header time 3
0
1
1
1
Header time 4
1
0
0
0
Status display 1
1
0
0
1
Status display 2
1
0
1
0
Status display 3
1
0
1
1
Status display 4
1
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-21/30
LC74794, 74794M
COMMAND14 (VPS/PDC control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
1
0
—
1
State
Notes
Function
Command 7 identification code
Display control setup
Extended command 7 identification code
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
—
4
HBS2
3
HBS1
State
1
0
Discrimination mode 1
1
Discrimination mode 2
0
Discrimination mode 1
1
Discrimination mode 2
Framing code
1
0
Data hold
1
Data write (In VPS mode, the error bit is set to 0.)
0
0
Clock line
Error checking enabled (Error checking can be turned on or off on a per-byte When 0, bytes for which error checking is
basis.)
specified and that have no errors are written to
P-S. When 1, all bytes are written to P-S
Error checking disabled (Applications can select whether to hold or write
regardless of errors.
data with errors on a per-byte basis.)
BMS
EMS
Second byte identification bit
0
0
2
Notes
Function
DCE
1
The handling of bytes for which error checking
is turned off when error checking is enabled.
Error checking turned on for data unused bytes.
VPS: bytes 3, 4, and 6 to 10. PDCC (8/30/2): bytes 7 to 12. Header 1: bytes
14 to 37. Header 2: bytes 14 to 29, Header 3: bytes 14 to 21. Status 1 (3):
Error checking specification for bytes whose
bytes 7 to 25. Status 2 (4): bytes 7 to 35.
data is unused.
Bi-phase (VPS), Hamming (PDC), or odd
Error checking turned off for data unused bytes.
VPS: bytes 3, 4, and 6 to 10. PDCC (8/30/2): bytes 7 to 12. Header 1: bytes parity (header)
14 to 37. Header 2: bytes 14 to 29, Header 3: bytes 14 to 21. Status 1 (3):
bytes 7 to 25. Status 2 (4): bytes 7 to 35.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-22/30
LC74794, 74794M
COMMAND15 (VPS/PDC control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
0
0
—
0
State
Function
Notes
Command 7 identification code
Display control setup
Extended command 8 identification code
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
ECV15
4
ECV14
3
2
1
0
ECV13
ECV12
ECV11
ECV5
State
Function
Notes
Second byte identification bit
0
Byte 15 bi-phase error check on (data held)
1
Byte 15 bi-phase error check off (data written)
0
Byte 14 bi-phase error check on (data held)
1
Byte 14 bi-phase error check off (data written)
0
Byte 13 bi-phase error check on (data held)
1
Byte 13 bi-phase error check off (data written)
0
Byte 12 bi-phase error check on (data held)
1
Byte 12 bi-phase error check off (data written)
0
Byte 11 bi-phase error check on (data held)
1
Byte 11 bi-phase error check off (data written)
0
Byte 5 bi-phase error check on (data held)
1
Byte 5 bi-phase error check off (data written)
Settings when the VPS data BMS = 0.
Settings in parentheses apply when BMS = 1.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-23/30
LC74794, 74794M
COMMAND16 (VPS/PDC control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
0
0
—
1
State
Function
Notes
Command 7 identification code
Display control setup
Extended command 9 identification code
Second byte
DA
0 to 7
Register
7
—
6
5
4
3
2
1
0
Contents
State
Function
0
Second byte identification bit
0
Byte 19 Hamming error check on (data held)
{Byte 44, 28, 36, 20, 32, 42, 32, and 42}
1
Byte 19 Hamming error check off (data written)
{Byte 44, 28, 36, 20, 32, 42, 32, and 42}
0
Byte 18 Hamming error check on (data held)
{Byte 43, 27, 35, 19, 31, 41, 31, and 41}
1
Byte 18 Hamming error check off (data written)
{Byte 43, 27, 35, 19, 31, 41, 31, and 41}
0
Byte 17 Hamming error check on (data held)
{Byte 42, 26, 34, 18, 30, 40, 30, and 40}
1
Byte 17 Hamming error check off (data written)
{Byte 42, 26, 34, 18, 30, 40, 30, and 40}
0
Byte 16 Hamming error check on (data held)
{Byte 41, 25, 33, 17, 29, 39, 29, and 39}
1
Byte 16 Hamming error check off (data written)
{Byte 41, 25, 33, 17, 29, 39, 29, and 39}
0
Byte 15 Hamming error check on (data held)
{Byte 40, 24, 32, 16, 28, 38, 28, and 38}
1
Byte 15 Hamming error check off (data written)
{Byte 40, 24, 32, 16, 28, 38, 28, and 38}
0
Byte 14 Hamming error check on (data held)
{Byte 39, 23, 31, 15, 27, 37, 27, and 37}
1
Byte 14 Hamming error check off (data written)
{Byte 39, 23, 31, 15, 27, 37, 27, and 37}
0
Byte 13 Hamming error check on (data held)
{Byte 38, 22, 30, 14, 26, 36, 26, and 36}
1
Byte 13 Hamming error check off (data written)
{Byte 38, 22, 30, 14, 26, 36, 26, and 36}
ECP19
ECP18
ECP17
ECP16
ECP15
ECP14
ECP13
Notes
Settings when the PDC data (8/30/2) BMS = 0.
Settings in parentheses apply when BMS = 1.
The items in curly brackets are the bytes for which the
odd parity check is turned on and off in header modes
1, 2, 3, and 4 and status modes 1, 2, 3, and 4,
respectively.
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-24/30
LC74794, 74794M
COMMAND17 (VPS/PDC control setup command)
First byte
Contents
DA
0 to 7
Register
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
1
0
—
0
State
Function
Notes
Command 7 identification code
Display control setup
Extended command A identification code
Second byte
Contents
DA
0 to 7
Register
7
—
0
6
—
0
5
4
3
2
1
0
State
Function
Notes
Second byte identification bit
0
Byte 25 Hamming error check on (data held)
1
Byte 25 Hamming error check off (data written)
0
Byte 24 Hamming error check on (data held)
1
Byte 24 Hamming error check off (data written)
0
Byte 23 Hamming error check on (data held)
1
Byte 23 Hamming error check off (data written)
0
Byte 22 Hamming error check on (data held)
{Byte ,,, 35, 45, 35, and 45}
1
Byte 22 Hamming error check off (data written)
{Byte ,,, 35, 45, 35, and 45}
0
Byte 21 Hamming error check on (data held)
{Byte ,,, 34, 44, 34, and 44}
1
Byte 21 Hamming error check off (data written)
{Byte ,,, 34, 44, 34, and 44}
0
Byte 20 Hamming error check on (data held)
{Byte 45, 29, 37, 21, 33, 43, 33, and 43}
1
Byte 20 Hamming error check off (data written)
{Byte 45, 29, 37, 21, 33, 43, 33, and 43}
ECP25
Settings when the PDC data (8/30/2) BMS = 0.
Settings in parentheses apply when BMS = 1.
The items in curly brackets are the bytes for which the
odd parity check is turned off in header modes 1, 2, 3,
and 4 and status modes 1, 2, 3, and 4, respectively.
ECP24
ECP23
ECP22
ECP21
ECP20
Note: All registers are set to 0 when the LC74794/M is reset by the RST pin.
No. 5557-25/30
LC74794, 74794M
PDC/VPS Output Data Formats
Data is read out in order starting with bytes 1 and 7
PDC 8/30 mode
Output data
Format1
Format2
VPS mode
Header time mode 1 (3)
Header time mode 2 (4)
Data update bits *: The value is 0 when data is updated and 1 when not updated.
Byte 1 Bit 7
6
5
4
3
2
1
0
byte 15 bit 0
1
2
3
4
5
6
7
byte 16 bit 0
1
2
3
byte 17 bit 0
1
2
3
byte 11 bit 0
1
2
3
4
5
6
7
byte 38 bit 0
(30) 1
2
3
4
5
6
7
byte 22 bit 0
(14) 1
2
3
4
5
6
7
Byte 2 Bit 7
6
5
4
3
2
1
0
byte 16 bit 0
1
2
3
4
5
6
7
byte 18 bit 0
1
2
3
byte 19 bit 0
1
2
3
byte 12 bit 0
1
2
3
4
5
6
7
byte 39 bit 0
(31) 1
2
3
4
5
6
7
byte 23 bit 0
(15) 1
2
3
4
5
6
7
Byte 3 Bit 7
6
5
4
3
2
1
0
byte 17 bit 0
1
2
3
4
5
6
7
byte 20 bit 0
1
2
3
byte 21 bit 0
1
2
3
byte 13 bit 0
1
2
3
4
5
6
7
byte 40 bit 0
(32) 1
2
3
4
5
6
7
byte 24 bit 0
(16) 1
2
3
4
5
6
7
Byte 4 Bit 7
6
5
4
3
2
1
0
byte 18 bit 0
1
2
3
4
5
6
7
byte 22 bit 0
1
2
3
byte 23 bit 0
1
2
3
byte 14 bit 0
1
2
3
4
5
6
7
byte 41 bit 0
(33) 1
2
3
4
5
6
7
byte 25 bit 0
(17) 1
2
3
4
5
6
7
Byte 5 Bit 7
6
5
4
3
2
1
0
byte 19 bit 0
1
2
3
4
5
6
7
byte 14 bit 0
1
2
3
byte 15 bit 0
1
2
3
byte 5 bit 0
1
2
3
4
5
6
7
byte 42 bit 0
(34) 1
2
3
4
5
6
7
byte 26 bit 0
(18) 1
2
3
4
5
6
7
Byte 6 Bit 7
6
5
4
3
2
1
0
byte 20 bit 0
1
2
3
4
5
6
7
byte 24 bit 0
1
2
3
byte 25 bit 0
1
2
3
byte 15 bit 0
1
2
3
4
5
6
7
byte 43 bit 0
(35) 1
2
3
4
5
6
7
byte 27 bit 0
(19) 1
2
3
4
5
6
7
Continued on next page.
No. 5557-26/30
LC74794, 74794M
Continued from preceding page.
PDC 8/30 mode
Output data
Header time mode 1 (3)
Header time mode 2 (4)
1
1
1
1
1
1
1
1
1
1
1
0
byte 44 bit 0
(36) 1
2
3
4
5
6
7
byte 28 bit 0
(20) 1
2
3
4
5
6
7
byte 13 bit 0
1
2
3
4
5
6
7
Error
byte 16
information 1
17
18
19
20
21
22
23
Error
byte 11
information 1
12
13
14
5
15
0
0
byte 45 bit 0
(37) 1
2
3
4
5
6
7
byte 29 bit 0
(21) 1
2
3
4
5
6
7
Byte 9 Bit 7
6
5
4
3
2
1
0
byte 14 bit 0
1
2
3
4
5
6
7
Error
byte 14
information 2
15
24
25
13
0
0
0
Byte 10 Bit 7
6
5
4
3
2
1
0
byte 22 bit 0
1
2
3
4
5
6
7
Byte 11 Bit 7
6
5
4
3
2
1
0
byte 23 bit 0
1
2
3
4
5
6
7
Byte 12 Bit 7
6
5
4
3
2
1
0
byte 24 bit 0
1
2
3
4
5
6
7
Byte 13 Bit 7
6
5
4
3
2
1
0
byte 25 bit 0
1
2
3
4
5
6
7
Format1
Format2
Byte 7 Bit 7
6
5
4
3
2
1
0
byte 21 bit 0
1
2
3
4
5
6
7
byte 13 bit 0
1
2
3
Byte 8 Bit 7
6
5
4
3
2
1
0
VPS mode
Error
byte 38 (30)
information
39 (31)
40 (32)
41 (33)
42 (34)
43 (35)
44 (36)
45 (37)
Error
byte 22 (14)
information
23 (15)
24 (16)
25 (17)
26 (18)
27 (19)
28 (20)
29 (21)
Bits for which there is no data setting are 1.
No. 5557-27/30
LC74794, 74794M
Data is read out in order starting with bytes 1 and 7
1, 2 : 8/30/2 3, 4 : 8/30/1
Output data
Status display
mode 1 (3)
Status display
mode 2 (4)
Data update bits *: The value is 0 when data is updated.
Byte 1 Bit 7
6
5
4
3
2
1
0
byte 26 bit 0
(26) 1
2
3
4
5
6
7
byte 36 bit 0
(36) 1
2
3
4
5
6
7
Byte 2 Bit 7
6
5
4
3
2
1
0
byte 27 bit 0
(27) 1
2
3
4
5
6
7
byte 37 bit 0
(37) 1
2
3
4
5
6
7
Byte 3 Bit 7
6
5
4
3
2
1
0
byte 28 bit 0
(28) 1
2
3
4
5
6
7
byte 38 bit 0
(38) 1
2
3
4
5
6
7
Byte 4 Bit 7
6
5
4
3
2
1
0
byte 29 bit 0
(29) 1
2
3
4
5
6
7
byte 39 bit 0
(39) 1
2
3
4
5
6
7
Byte 5 Bit 7
6
5
4
3
2
1
0
byte 30 bit 0
(30) 1
2
3
4
5
6
7
byte 40 bit 0
(40) 1
2
3
4
5
6
7
Byte 6 Bit 7
6
5
4
3
2
1
0
byte 31 bit 0
(31) 1
2
3
4
5
6
7
byte 41 bit 0
(41) 1
2
3
4
5
6
7
Byte 7 Bit 7
6
5
4
3
2
1
0
byte 32 bit 0
(32) 1
2
3
4
5
6
7
byte 42 bit 0
(42) 1
2
3
4
5
6
7
Status display
mode 1 (3)
Status display
mode 2 (4)
Byte 8 Bit 7
6
5
4
3
2
1
0
byte 33 bit 0
(33) 1
2
3
4
5
6
7
byte 43 bit 0
(43) 1
2
3
4
5
6
7
Byte 9 Bit 7
6
5
4
3
2
1
0
byte 34 bit 0
(34) 1
2
3
4
5
6
7
byte 44 bit 0
(44) 1
2
3
4
5
6
7
Byte 10 Bit 7
6
5
4
3
2
1
0
byte 35 bit 0
(35) 1
2
3
4
5
6
7
byte 45 bit 0
(45) 1
2
3
4
5
6
7
Byte 11 Bit 7
6
5
4
3
2
1
0
Error
byte 26 (26)
information 1 27 (27)
28 (28)
29 (29)
30 (30)
31 (31)
32 (32)
33 (33)
Error
byte 36 (36)
information 1 37 (37)
38 (38)
39 (39)
40 (40)
41 (41)
42 (42)
43 (43)
Byte 12 Bit 7
6
5
4
3
2
1
0
Error
byte 34 (34)
information 2 35 (35)
0
0
0
0
0
0
Error
byte 44 (44)
information 2 45 (45)
0
0
0
0
0
0
Output data
Byte 13 Bit 7
6
5
4
3
2
1
0
Bits for which there is no data setting are 1.
No. 5557-28/30
LC74794, 74794M
Display Screen Structure
The display consists of 12 lines of 24 characters each.
Up to 288 characters can be displayed.
The number of characters that can be displayed is reduced from the normal total of 288 when enlarged characters are
displayed.
Display memory addresses are specified as row (0 to b hexadecimal) and column (0 to 17 hexadecimal) addresses.
Display Screen Structure (display memory addresses)
24 characters × 12 rows
No. 5557-29/30
LC74794, 74794M
Composite Video Signal Output Levels (internally generated levels)
CVOUT output level waveform (VDD2 = 5.0 V)
Output level
VCHA: Character
VRSH: Background color high
VCBH: Color burst high
VRSL: Background color low
Output voltage (1) [V]
Output voltage (2) [V]
2.65
2.85
Output voltage (3) [V]
3.15
2.37 (2.01)
2.57 (2.21)
2.87 (2.51)
1.67
1.87
2.17
1.23 (1.16)
1.43 (1.36)
1.73 (1.66)
VBK1: Border
2.08
2.28
2.58
VBK0: Border
1.50
1.70
2.00
VPD: Pedestal
1.37
1.57
1.87
VCBL: Color burst low
1.07
1.27
1.57
VSN: Sync
0.80
1.00
1.30
Note: VDD2 = 5.0 V. Values in parentheses for VRSH and VRSL apply when the background color is blue.
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 5557-30/30